ShuriZma
/
stella
mirror of https://github.com/stella-emu/stella.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fixed #537 (writes to read ports)

This commit is contained in:
thrust26 2020-03-24 12:02:51 +01:00
parent a3b536c94d
commit f88a932d1e
5 changed files with 96 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
src/emucore/Cart3EPlus.cxx
View File

@ -143,10 +143,22 @@ bool Cartridge3EPlus::poke(uInt16 address, uInt8 value)
if(whichBankIsThere & BITMASK_ROMRAM)
{
uInt32 byteOffset = address & BITMASK_RAM_BANK;
uInt32 baseAddress = ((whichBankIsThere & BIT_BANK_MASK) << RAM_BANK_TO_POWER) + byteOffset;
pokeRAM(myRAM[baseAddress], address, value);
changed = true;
if(address & RAM_BANK_SIZE)
{
uInt32 byteOffset = address & BITMASK_RAM_BANK;
uInt32 baseAddress = ((whichBankIsThere & BIT_BANK_MASK) << RAM_BANK_TO_POWER) + byteOffset;
pokeRAM(myRAM[baseAddress], address, value);
changed = true;
}
else
{
// Writing to the read port should be ignored, but trigger a break if option enabled
uInt8 dummy;
pokeRAM(dummy, address, value);
myRamWriteAccess = address;
changed = false;
}
}
}

17
src/emucore/CartCV.cxx
View File

@ -104,8 +104,21 @@ uInt8 CartridgeCV::peek(uInt16 address)
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
bool CartridgeCV::poke(uInt16 address, uInt8 value)
{
pokeRAM(myRAM[address & 0x03FF], address, value);
return true;
if(address & 0x0400)
{
pokeRAM(myRAM[address & 0x03FF], address, value);
return true;
}
else
{
// Writing to the read port should be ignored, but trigger a break if option enabled
uInt8 dummy;
pokeRAM(dummy, address, value);
myRamWriteAccess = address;
return false;
}
}
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

17
src/emucore/CartCVPlus.cxx
View File

@ -104,9 +104,22 @@ bool CartridgeCVPlus::poke(uInt16 address, uInt8 value)
return mySystem->tia().poke(address, value);
}
else
pokeRAM(myRAM[address & 0x03FF], pokeAddress, value);
{
if(address & 0x0400)
{
pokeRAM(myRAM[address & 0x03FF], pokeAddress, value);
return true;
}
else
{
// Writing to the read port should be ignored, but trigger a break if option enabled
uInt8 dummy;
return true;
pokeRAM(dummy, pokeAddress, value);
myRamWriteAccess = pokeAddress;
return false;
}
}
}
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

20
src/emucore/CartDASH.cxx
View File

@ -135,10 +135,22 @@ bool CartridgeDASH::poke(uInt16 address, uInt8 value)
if(whichBankIsThere & BITMASK_ROMRAM)
{
uInt32 byteOffset = address & BITMASK_RAM_BANK;
uInt32 baseAddress = ((whichBankIsThere & BIT_BANK_MASK) << RAM_BANK_TO_POWER) + byteOffset;
pokeRAM(myRAM[baseAddress], address, value);
changed = true;
if(address & RAM_BANK_SIZE)
{
uInt32 byteOffset = address & BITMASK_RAM_BANK;
uInt32 baseAddress = ((whichBankIsThere & BIT_BANK_MASK) << RAM_BANK_TO_POWER) + byteOffset;
pokeRAM(myRAM[baseAddress], address, value);
changed = true;
}
else
{
// Writing to the read port should be ignored, but trigger a break if option enabled
uInt8 dummy;
pokeRAM(dummy, address, value);
myRamWriteAccess = address;
changed = false;
}
}
}

39
src/emucore/CartMNetwork.cxx
View File

@ -137,13 +137,42 @@ bool CartridgeMNetwork::poke(uInt16 address, uInt8 value)
// All RAM writes are mapped here
if((myCurrentSlice[0] == myRAMSlice) && (address < BANK_SIZE / 2))
{
pokeRAM(myRAM[address & (BANK_SIZE / 2 - 1)], pokeAddress, value);
return true;
// RAM slices
if(!(address & 0x0400))
{
pokeRAM(myRAM[address & (BANK_SIZE / 2 - 1)], pokeAddress, value);
return true;
}
else
{
// Writing to the read port should be ignored, but trigger a break if option enabled
uInt8 dummy;
pokeRAM(dummy, pokeAddress, value);
myRamWriteAccess = pokeAddress;
return false;
}
}
else if((address >= 0x0800) && (address <= 0x08FF))
else
{
pokeRAM(myRAM[0x0400 + (myCurrentRAM << 8) + (address & 0x00FF)], pokeAddress, value);
return true;
// fixed 256 bytes of RAM
if((address >= 0x0800) && (address <= 0x09FF))
{
if(!(address & 0x100))
{
pokeRAM(myRAM[0x0400 + (myCurrentRAM << 8) + (address & 0x00FF)], pokeAddress, value);
return true;
}
else
{
// Writing to the read port should be ignored, but trigger a break if option enabled
uInt8 dummy;
pokeRAM(dummy, pokeAddress, value);
myRamWriteAccess = pokeAddress;
return false;
}
}
}
return false;