diff --git a/src/emucore/Cart3EPlus.cxx b/src/emucore/Cart3EPlus.cxx
index 23f833976..139cda4b7 100644
--- a/src/emucore/Cart3EPlus.cxx
+++ b/src/emucore/Cart3EPlus.cxx
@@ -143,10 +143,22 @@ bool Cartridge3EPlus::poke(uInt16 address, uInt8 value)
 
     if(whichBankIsThere & BITMASK_ROMRAM)
     {
-      uInt32 byteOffset = address & BITMASK_RAM_BANK;
-      uInt32 baseAddress = ((whichBankIsThere & BIT_BANK_MASK) << RAM_BANK_TO_POWER) + byteOffset;
-      pokeRAM(myRAM[baseAddress], address, value);
-      changed = true;
+      if(address & RAM_BANK_SIZE)
+      {
+        uInt32 byteOffset = address & BITMASK_RAM_BANK;
+        uInt32 baseAddress = ((whichBankIsThere & BIT_BANK_MASK) << RAM_BANK_TO_POWER) + byteOffset;
+        pokeRAM(myRAM[baseAddress], address, value);
+        changed = true;
+      }
+      else
+      {
+        // Writing to the read port should be ignored, but trigger a break if option enabled
+        uInt8 dummy;
+
+        pokeRAM(dummy, address, value);
+        myRamWriteAccess = address;
+        changed = false;
+      }
     }
   }
 
diff --git a/src/emucore/CartCV.cxx b/src/emucore/CartCV.cxx
index 73c55954b..e5ca47788 100644
--- a/src/emucore/CartCV.cxx
+++ b/src/emucore/CartCV.cxx
@@ -104,8 +104,21 @@ uInt8 CartridgeCV::peek(uInt16 address)
 // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 bool CartridgeCV::poke(uInt16 address, uInt8 value)
 {
-  pokeRAM(myRAM[address & 0x03FF], address, value);
-  return true;
+
+  if(address & 0x0400)
+  {
+    pokeRAM(myRAM[address & 0x03FF], address, value);
+    return true;
+  }
+  else
+  {
+    // Writing to the read port should be ignored, but trigger a break if option enabled
+    uInt8 dummy;
+
+    pokeRAM(dummy, address, value);
+    myRamWriteAccess = address;
+    return false;
+  }
 }
 
 // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
diff --git a/src/emucore/CartCVPlus.cxx b/src/emucore/CartCVPlus.cxx
index eb3bb1023..c70c53b0d 100644
--- a/src/emucore/CartCVPlus.cxx
+++ b/src/emucore/CartCVPlus.cxx
@@ -104,9 +104,22 @@ bool CartridgeCVPlus::poke(uInt16 address, uInt8 value)
     return mySystem->tia().poke(address, value);
   }
   else
-    pokeRAM(myRAM[address & 0x03FF], pokeAddress, value);
+  {
+    if(address & 0x0400)
+    {
+      pokeRAM(myRAM[address & 0x03FF], pokeAddress, value);
+      return true;
+    }
+    else
+    {
+    // Writing to the read port should be ignored, but trigger a break if option enabled
+      uInt8 dummy;
 
-  return true;
+      pokeRAM(dummy, pokeAddress, value);
+      myRamWriteAccess = pokeAddress;
+      return false;
+    }
+  }
 }
 
 // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
diff --git a/src/emucore/CartDASH.cxx b/src/emucore/CartDASH.cxx
index f721a1edb..2c85ada47 100644
--- a/src/emucore/CartDASH.cxx
+++ b/src/emucore/CartDASH.cxx
@@ -135,10 +135,22 @@ bool CartridgeDASH::poke(uInt16 address, uInt8 value)
 
     if(whichBankIsThere & BITMASK_ROMRAM)
     {
-      uInt32 byteOffset = address & BITMASK_RAM_BANK;
-      uInt32 baseAddress = ((whichBankIsThere & BIT_BANK_MASK) << RAM_BANK_TO_POWER) + byteOffset;
-      pokeRAM(myRAM[baseAddress], address, value);
-      changed = true;
+      if(address & RAM_BANK_SIZE)
+      {
+        uInt32 byteOffset = address & BITMASK_RAM_BANK;
+        uInt32 baseAddress = ((whichBankIsThere & BIT_BANK_MASK) << RAM_BANK_TO_POWER) + byteOffset;
+        pokeRAM(myRAM[baseAddress], address, value);
+        changed = true;
+      }
+      else
+      {
+        // Writing to the read port should be ignored, but trigger a break if option enabled
+        uInt8 dummy;
+
+        pokeRAM(dummy, address, value);
+        myRamWriteAccess = address;
+        changed = false;
+      }
     }
   }
 
diff --git a/src/emucore/CartMNetwork.cxx b/src/emucore/CartMNetwork.cxx
index cffec53b6..b433c4d72 100644
--- a/src/emucore/CartMNetwork.cxx
+++ b/src/emucore/CartMNetwork.cxx
@@ -137,13 +137,42 @@ bool CartridgeMNetwork::poke(uInt16 address, uInt8 value)
   // All RAM writes are mapped here
   if((myCurrentSlice[0] == myRAMSlice) && (address < BANK_SIZE / 2))
   {
-    pokeRAM(myRAM[address & (BANK_SIZE / 2 - 1)], pokeAddress, value);
-    return true;
+    // RAM slices
+    if(!(address & 0x0400))
+    {
+      pokeRAM(myRAM[address & (BANK_SIZE / 2 - 1)], pokeAddress, value);
+      return true;
+    }
+    else
+    {
+      // Writing to the read port should be ignored, but trigger a break if option enabled
+      uInt8 dummy;
+
+      pokeRAM(dummy, pokeAddress, value);
+      myRamWriteAccess = pokeAddress;
+      return false;
+    }
   }
-  else if((address >= 0x0800) && (address <= 0x08FF))
+  else
   {
-    pokeRAM(myRAM[0x0400 + (myCurrentRAM << 8) + (address & 0x00FF)], pokeAddress, value);
-    return true;
+    // fixed 256 bytes of RAM
+    if((address >= 0x0800) && (address <= 0x09FF))
+    {
+      if(!(address & 0x100))
+      {
+        pokeRAM(myRAM[0x0400 + (myCurrentRAM << 8) + (address & 0x00FF)], pokeAddress, value);
+        return true;
+      }
+      else
+      {
+        // Writing to the read port should be ignored, but trigger a break if option enabled
+        uInt8 dummy;
+
+        pokeRAM(dummy, pokeAddress, value);
+        myRamWriteAccess = pokeAddress;
+        return false;
+      }
+    }
   }
 
   return false;