mirror of https://github.com/stella-emu/stella.git
Complete vcslib bootstrap.
This commit is contained in:
parent
54e65a9c03
commit
bc83f56924
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@ -204,15 +204,6 @@ void CartridgeELF::reset()
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myIsBusDriven = false;
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myIsBusDriven = false;
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myDriveBusValue = 0;
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myDriveBusValue = 0;
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myTransactionQueue
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.reset()
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.injectROM(0x00, 0x1ffc)
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.injectROM(0x10)
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.setNextInjectAddress(0x1000);
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myVcsLib.vcsCopyOverblankToRiotRam();
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myVcsLib.vcsStartOverblank();
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std::memset(mySectionStack.get(), 0, STACK_SIZE);
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std::memset(mySectionStack.get(), 0, STACK_SIZE);
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std::memset(mySectionText.get(), 0, TEXT_SIZE);
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std::memset(mySectionText.get(), 0, TEXT_SIZE);
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std::memset(mySectionData.get(), 0, DATA_SIZE);
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std::memset(mySectionData.get(), 0, DATA_SIZE);
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@ -228,6 +219,17 @@ void CartridgeELF::reset()
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std::memcpy(mySectionTables.get(), LOOKUP_TABLES, sizeof(LOOKUP_TABLES));
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std::memcpy(mySectionTables.get(), LOOKUP_TABLES, sizeof(LOOKUP_TABLES));
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myCortexEmu.reset();
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myCortexEmu.reset();
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myTransactionQueue
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.reset()
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.injectROM(0x00, 0x1ffc)
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.injectROM(0x10)
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.setNextInjectAddress(0x1000);
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myVcsLib.vcsCopyOverblankToRiotRam();
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myVcsLib.vcsStartOverblank();
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myVcsLib.vcsEndOverblank();
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myVcsLib.vcsNop2n(1024);
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}
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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@ -70,6 +70,11 @@ BusTransactionQueue& BusTransactionQueue::setNextInjectAddress(uInt16 address)
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return *this;
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return *this;
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}
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}
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uInt16 BusTransactionQueue::getNextInjectAddress() const
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{
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return myNextInjectAddress;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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BusTransactionQueue& BusTransactionQueue::injectROM(uInt8 value)
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BusTransactionQueue& BusTransactionQueue::injectROM(uInt8 value)
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{
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{
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@ -39,6 +39,8 @@ class BusTransactionQueue {
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BusTransactionQueue& reset();
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BusTransactionQueue& reset();
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BusTransactionQueue& setNextInjectAddress(uInt16 address);
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BusTransactionQueue& setNextInjectAddress(uInt16 address);
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uInt16 getNextInjectAddress() const;
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BusTransactionQueue& injectROM(uInt8 value);
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BusTransactionQueue& injectROM(uInt8 value);
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BusTransactionQueue& injectROM(uInt8 value, uInt16 address);
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BusTransactionQueue& injectROM(uInt8 value, uInt16 address);
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@ -55,6 +55,24 @@ void VcsLib::vcsStartOverblank()
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.yield(0x0080);
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.yield(0x0080);
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}
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}
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void VcsLib::vcsEndOverblank()
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{
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myTransactionQueue
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.injectROM(0x00, 0x1fff)
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.yield(0x00ac)
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.setNextInjectAddress(0x1000);
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}
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void VcsLib::vcsNop2n(uInt16 n)
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{
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if (n == 0) return;
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myTransactionQueue.injectROM(0xea);
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myTransactionQueue.setNextInjectAddress(
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myTransactionQueue.getNextInjectAddress() + (n - 1)
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);
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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CortexM0::err_t VcsLib::fetch16(uInt32 address, uInt16& value, uInt8& op, CortexM0& cortex)
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CortexM0::err_t VcsLib::fetch16(uInt32 address, uInt16& value, uInt8& op, CortexM0& cortex)
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{
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{
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@ -84,7 +102,8 @@ CortexM0::err_t VcsLib::fetch16(uInt32 address, uInt16& value, uInt8& op, Cortex
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FatalEmulationError::raise("unimplemented: vcsNop2");
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FatalEmulationError::raise("unimplemented: vcsNop2");
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case ADDR_VCS_NOP2N:
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case ADDR_VCS_NOP2N:
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FatalEmulationError::raise("unimplemented: vcsNop2n");
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vcsNop2n(cortex.getRegister(0));
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return returnFromStub(value, op);
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case ADDR_VCS_WRITE5:
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case ADDR_VCS_WRITE5:
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FatalEmulationError::raise("unimplemented: vcsWrite5");
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FatalEmulationError::raise("unimplemented: vcsWrite5");
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@ -131,7 +150,8 @@ CortexM0::err_t VcsLib::fetch16(uInt32 address, uInt16& value, uInt8& op, Cortex
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return returnFromStub(value, op);
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return returnFromStub(value, op);
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case ADDR_VCS_END_OVERBLANK:
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case ADDR_VCS_END_OVERBLANK:
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FatalEmulationError::raise("unimplemented: vcsEndOverblank");
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vcsEndOverblank();
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return returnFromStub(value, op);
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case ADDR_VCS_READ4:
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case ADDR_VCS_READ4:
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FatalEmulationError::raise("unimplemented: vcsRead4");
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FatalEmulationError::raise("unimplemented: vcsRead4");
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@ -32,6 +32,8 @@ class VcsLib: public CortexM0::BusTransactionDelegate {
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void vcsWrite5(uInt8 zpAddress, uInt8 value);
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void vcsWrite5(uInt8 zpAddress, uInt8 value);
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void vcsCopyOverblankToRiotRam();
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void vcsCopyOverblankToRiotRam();
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void vcsStartOverblank();
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void vcsStartOverblank();
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void vcsEndOverblank();
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void vcsNop2n(uInt16 n);
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private:
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private:
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CortexM0::err_t returnFromStub(uInt16& value, uInt8& op);
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CortexM0::err_t returnFromStub(uInt16& value, uInt8& op);
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