mirror of https://github.com/stella-emu/stella.git
First pass at reorganizing the disassembler code. The entire functionality
will be integrated intp CpuDebug, which will also be merged with distella. git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1914 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
This commit is contained in:
stephena
parent
e8604d426a
commit
88df583c23
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@ -126,96 +126,96 @@ int CpuDebug::disassemble(int address, string& result, EquateList& list)
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// Are we looking at a read or write operation?
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// It will determine what type of label to use
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bool isRead = (M6502::ourAccessModeTable[opcode] == M6502::Read);
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bool isRead = (M6502::AccessModeTable[opcode] == M6502::Read);
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switch(M6502::ourAddressingModeTable[opcode])
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switch(M6502::AddressModeTable[opcode])
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{
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case M6502::Absolute:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " "
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buf << M6502::InstructionMnemonicTable[opcode] << " "
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<< list.getLabel(dpeek(mySystem, address + 1), isRead, 4) << " ; "
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<< M6502::ourInstructionProcessorCycleTable[opcode];
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<< M6502::InstructionCycleTable[opcode];
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count = 3;
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break;
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case M6502::AbsoluteX:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " "
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buf << M6502::InstructionMnemonicTable[opcode] << " "
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<< list.getLabel(dpeek(mySystem, address + 1), isRead, 4) << ",x ; "
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<< M6502::ourInstructionProcessorCycleTable[opcode];
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<< M6502::InstructionCycleTable[opcode];
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count = 3;
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break;
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case M6502::AbsoluteY:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " "
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buf << M6502::InstructionMnemonicTable[opcode] << " "
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<< list.getLabel(dpeek(mySystem, address + 1), isRead, 4) << ",y ; "
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<< M6502::ourInstructionProcessorCycleTable[opcode];
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<< M6502::InstructionCycleTable[opcode];
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count = 3;
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break;
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case M6502::Immediate:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " #$"
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buf << M6502::InstructionMnemonicTable[opcode] << " #$"
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<< hex << setw(2) << setfill('0') << (int) mySystem.peek(address + 1) << " ; "
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<< dec << M6502::ourInstructionProcessorCycleTable[opcode];
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<< dec << M6502::InstructionCycleTable[opcode];
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count = 2;
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break;
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case M6502::Implied:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " ; "
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<< M6502::ourInstructionProcessorCycleTable[opcode];
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buf << M6502::InstructionMnemonicTable[opcode] << " ; "
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<< M6502::InstructionCycleTable[opcode];
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count = 1;
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break;
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case M6502::Indirect:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " ("
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buf << M6502::InstructionMnemonicTable[opcode] << " ("
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<< list.getLabel(dpeek(mySystem, address + 1), isRead, 4) << ") ; "
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<< M6502::ourInstructionProcessorCycleTable[opcode];
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<< M6502::InstructionCycleTable[opcode];
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count = 3;
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break;
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case M6502::IndirectX:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " ("
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buf << M6502::InstructionMnemonicTable[opcode] << " ("
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<< list.getLabel(mySystem.peek(address + 1), isRead, 2) << ",x) ; "
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<< M6502::ourInstructionProcessorCycleTable[opcode];
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<< M6502::InstructionCycleTable[opcode];
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count = 2;
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break;
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case M6502::IndirectY:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " ("
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buf << M6502::InstructionMnemonicTable[opcode] << " ("
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<< list.getLabel(mySystem.peek(address + 1), isRead, 2) << "),y ; "
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<< M6502::ourInstructionProcessorCycleTable[opcode];
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<< M6502::InstructionCycleTable[opcode];
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count = 2;
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break;
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case M6502::Relative:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " "
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buf << M6502::InstructionMnemonicTable[opcode] << " "
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<< list.getLabel(address + 2 + ((Int16)(Int8)mySystem.peek(address + 1)), isRead, 4)
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<< " ; " << M6502::ourInstructionProcessorCycleTable[opcode];
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<< " ; " << M6502::InstructionCycleTable[opcode];
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count = 2;
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break;
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case M6502::Zero:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " "
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buf << M6502::InstructionMnemonicTable[opcode] << " "
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<< list.getLabel(mySystem.peek(address + 1), isRead, 2) << " ; "
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<< M6502::ourInstructionProcessorCycleTable[opcode];
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<< M6502::InstructionCycleTable[opcode];
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count = 2;
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break;
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case M6502::ZeroX:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " "
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buf << M6502::InstructionMnemonicTable[opcode] << " "
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<< list.getLabel(mySystem.peek(address + 1), isRead, 2) << ",x ; "
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<< M6502::ourInstructionProcessorCycleTable[opcode];
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<< M6502::InstructionCycleTable[opcode];
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count = 2;
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break;
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case M6502::ZeroY:
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buf << M6502::ourInstructionMnemonicTable[opcode] << " "
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buf << M6502::InstructionMnemonicTable[opcode] << " "
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<< list.getLabel(mySystem.peek(address + 1), isRead, 2) << ",y ; "
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<< M6502::ourInstructionProcessorCycleTable[opcode];
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<< M6502::InstructionCycleTable[opcode];
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count = 2;
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break;
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default:
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buf << "dc $" << hex << setw(2) << setfill('0') << (int) opcode << " ; "
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<< dec << M6502::ourInstructionProcessorCycleTable[opcode];
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<< dec << M6502::InstructionCycleTable[opcode];
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count = 1;
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break;
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}
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@ -50,7 +50,7 @@ M6502::M6502(uInt32 systemCyclesPerProcessorCycle)
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// Compute the System Cycle table
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for(uInt32 t = 0; t < 256; ++t)
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{
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myInstructionSystemCycleTable[t] = ourInstructionProcessorCycleTable[t] *
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myInstructionSystemCycleTable[t] = InstructionCycleTable[t] *
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mySystemCyclesPerProcessorCycle;
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}
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@ -418,6 +418,7 @@ bool M6502::load(Serializer& in)
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return true;
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}
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#if 0
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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ostream& operator<<(ostream& out, const M6502::AddressingMode& mode)
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{
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@ -465,9 +466,78 @@ ostream& operator<<(ostream& out, const M6502::AddressingMode& mode)
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}
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return out;
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}
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#endif
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#ifdef DEBUGGER_SUPPORT
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void M6502::attach(Debugger& debugger)
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{
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// Remember the debugger for this microprocessor
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myDebugger = &debugger;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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M6502::AddressingMode M6502::ourAddressingModeTable[256] = {
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unsigned int M6502::addCondBreak(Expression *e, const string& name)
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{
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myBreakConds.push_back(e);
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myBreakCondNames.push_back(name);
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return myBreakConds.size() - 1;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void M6502::delCondBreak(unsigned int brk)
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{
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if(brk < myBreakConds.size())
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{
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delete myBreakConds[brk];
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myBreakConds.remove_at(brk);
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myBreakCondNames.remove_at(brk);
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}
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void M6502::clearCondBreaks()
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{
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for(uInt32 i = 0; i < myBreakConds.size(); i++)
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delete myBreakConds[i];
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myBreakConds.clear();
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myBreakCondNames.clear();
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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const StringList& M6502::getCondBreakNames() const
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{
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return myBreakCondNames;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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int M6502::evalCondBreaks()
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{
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for(uInt32 i = 0; i < myBreakConds.size(); i++)
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if(myBreakConds[i]->evaluate())
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return i;
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return -1; // no break hit
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void M6502::setBreakPoints(PackedBitArray *bp)
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{
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myBreakPoints = bp;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void M6502::setTraps(PackedBitArray *read, PackedBitArray *write)
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{
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myReadTraps = read;
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myWriteTraps = write;
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}
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#endif
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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M6502::AddressingMode M6502::AddressModeTable[256] = {
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Implied, IndirectX, Invalid, IndirectX, // 0x0?
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Zero, Zero, Zero, Zero,
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Implied, Immediate, Implied, Immediate,
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@ -550,7 +620,7 @@ M6502::AddressingMode M6502::ourAddressingModeTable[256] = {
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};
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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M6502::AccessMode M6502::ourAccessModeTable[256] = {
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M6502::AccessMode M6502::AccessModeTable[256] = {
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None, Read, None, Write, // 0x0?
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None, Read, Write, Write,
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None, Read, Write, Read,
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@ -633,7 +703,7 @@ M6502::AccessMode M6502::ourAccessModeTable[256] = {
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};
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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uInt32 M6502::ourInstructionProcessorCycleTable[256] = {
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uInt32 M6502::InstructionCycleTable[256] = {
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// 0 1 2 3 4 5 6 7 8 9 a b c d e f
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7, 6, 2, 8, 3, 3, 5, 5, 3, 2, 2, 2, 4, 4, 6, 6, // 0
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2, 5, 2, 8, 4, 4, 6, 6, 2, 4, 2, 7, 4, 4, 7, 7, // 1
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@ -654,7 +724,7 @@ uInt32 M6502::ourInstructionProcessorCycleTable[256] = {
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};
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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const char* M6502::ourInstructionMnemonicTable[256] = {
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const char* M6502::InstructionMnemonicTable[256] = {
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"BRK", "ORA", "n/a", "slo", "nop", "ORA", "ASL", "slo", // 0x0?
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"PHP", "ORA", "ASLA", "anc", "nop", "ORA", "ASL", "slo",
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@ -703,71 +773,3 @@ const char* M6502::ourInstructionMnemonicTable[256] = {
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"BEQ", "SBC", "n/a", "isb", "nop", "SBC", "INC", "isb", // 0xF?
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"SED", "SBC", "nop", "isb", "nop", "SBC", "INC", "isb"
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};
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#ifdef DEBUGGER_SUPPORT
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void M6502::attach(Debugger& debugger)
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{
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// Remember the debugger for this microprocessor
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myDebugger = &debugger;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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unsigned int M6502::addCondBreak(Expression *e, const string& name)
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{
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myBreakConds.push_back(e);
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myBreakCondNames.push_back(name);
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return myBreakConds.size() - 1;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void M6502::delCondBreak(unsigned int brk)
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{
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if(brk < myBreakConds.size())
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{
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delete myBreakConds[brk];
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myBreakConds.remove_at(brk);
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myBreakCondNames.remove_at(brk);
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}
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void M6502::clearCondBreaks()
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{
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for(uInt32 i = 0; i < myBreakConds.size(); i++)
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delete myBreakConds[i];
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myBreakConds.clear();
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myBreakCondNames.clear();
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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const StringList& M6502::getCondBreakNames() const
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{
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return myBreakCondNames;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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int M6502::evalCondBreaks()
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{
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for(uInt32 i = 0; i < myBreakConds.size(); i++)
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if(myBreakConds[i]->evaluate())
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return i;
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return -1; // no break hit
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void M6502::setBreakPoints(PackedBitArray *bp)
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{
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myBreakPoints = bp;
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}
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// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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void M6502::setTraps(PackedBitArray *read, PackedBitArray *write)
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{
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myReadTraps = read;
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myWriteTraps = write;
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}
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#endif
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@ -49,31 +49,9 @@ typedef Common::Array<Expression*> ExpressionList;
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*/
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class M6502 : public Serializable
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{
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public:
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/**
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The 6502 debugger class is a friend who needs special access
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*/
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// The 6502 debugger class is a friend who needs special access
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friend class CpuDebug;
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public:
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/**
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Enumeration of the 6502 addressing modes
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*/
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enum AddressingMode
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{
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Absolute, AbsoluteX, AbsoluteY, Immediate, Implied,
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Indirect, IndirectX, IndirectY, Invalid, Relative,
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Zero, ZeroX, ZeroY
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};
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/**
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Enumeration of the 6502 access modes
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*/
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enum AccessMode
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{
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Read, Write, None
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};
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public:
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/**
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Create a new 6502 microprocessor with the specified cycle
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@ -182,14 +160,6 @@ class M6502 : public Serializable
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*/
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uInt32 distinctAccesses() const { return myNumberOfDistinctAccesses; }
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/**
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Overload the ostream output operator for addressing modes.
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@param out The stream to output the addressing mode to
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@param mode The addressing mode to output
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*/
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friend ostream& operator<<(ostream& out, const AddressingMode& mode);
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/**
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Saves the current state of this device to the given Serializer.
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@ -213,25 +183,6 @@ class M6502 : public Serializable
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*/
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string name() const { return "M6502"; }
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public:
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/**
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Get the addressing mode of the specified instruction
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@param opcode The opcode of the instruction
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@return The addressing mode of the instruction
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*/
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AddressingMode addressingMode(uInt8 opcode) const
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{ return ourAddressingModeTable[opcode]; }
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/**
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Get the access mode of the specified instruction
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@param opcode The opcode of the instruction
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@return The access mode of the instruction
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*/
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AccessMode accessMode(uInt8 opcode) const
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{ return ourAccessModeTable[opcode]; }
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#ifdef DEBUGGER_SUPPORT
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public:
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/**
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@ -364,22 +315,40 @@ class M6502 : public Serializable
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#endif
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private:
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/**
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Enumeration of the 6502 addressing modes
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*/
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enum AddressingMode
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{
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Absolute, AbsoluteX, AbsoluteY, Immediate, Implied,
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Indirect, IndirectX, IndirectY, Invalid, Relative,
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Zero, ZeroX, ZeroY
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};
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/**
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Enumeration of the 6502 access modes
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*/
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enum AccessMode
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{
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Read, Write, None
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};
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/// Addressing mode for each of the 256 opcodes
|
||||
/// This specifies how the opcode argument is addressed
|
||||
static AddressingMode ourAddressingModeTable[256];
|
||||
static AddressingMode AddressModeTable[256];
|
||||
|
||||
/// Access mode for each of the 256 opcodes
|
||||
/// This specifies how the opcode will access its argument
|
||||
static AccessMode ourAccessModeTable[256];
|
||||
static AccessMode AccessModeTable[256];
|
||||
|
||||
/**
|
||||
Table of instruction processor cycle times. In some cases additional
|
||||
cycles will be added during the execution of an instruction.
|
||||
*/
|
||||
static uInt32 ourInstructionProcessorCycleTable[256];
|
||||
static uInt32 InstructionCycleTable[256];
|
||||
|
||||
/// Table of instruction mnemonics
|
||||
static const char* ourInstructionMnemonicTable[256];
|
||||
static const char* InstructionMnemonicTable[256];
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue