OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
//============================================================================
|
|
|
|
//
|
|
|
|
// SSSS tt lll lll
|
|
|
|
// SS SS tt ll ll
|
|
|
|
// SS tttttt eeee ll ll aaaa
|
|
|
|
// SSSS tt ee ee ll ll aa
|
|
|
|
// SS tt eeeeee ll ll aaaaa -- "An Atari 2600 VCS Emulator"
|
|
|
|
// SS SS tt ee ll ll aa aa
|
|
|
|
// SSSS ttt eeeee llll llll aaaaa
|
|
|
|
//
|
2013-01-04 19:49:01 +00:00
|
|
|
// Copyright (c) 1995-2013 by Bradford W. Mott, Stephen Anthony
|
2010-04-10 21:37:23 +00:00
|
|
|
// and the Stella Team
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
//
|
2010-04-10 21:37:23 +00:00
|
|
|
// See the file "License.txt" for information on usage and redistribution of
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
// this file, and for a DISCLAIMER OF ALL WARRANTIES.
|
|
|
|
//
|
|
|
|
// $Id$
|
|
|
|
//============================================================================
|
|
|
|
|
|
|
|
#ifndef DISTELLA_HXX
|
|
|
|
#define DISTELLA_HXX
|
|
|
|
|
|
|
|
#include <queue>
|
2010-01-31 02:07:19 +00:00
|
|
|
#include <sstream>
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
|
|
|
#include "Array.hxx"
|
|
|
|
#include "bspf.hxx"
|
2010-02-01 20:00:50 +00:00
|
|
|
#include "CartDebug.hxx"
|
2010-10-18 18:39:57 +00:00
|
|
|
#include "DebuggerParser.hxx"
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
2010-01-31 02:07:19 +00:00
|
|
|
/**
|
|
|
|
This class is a wrapper around the Distella code. Much of the code remains
|
2010-01-31 19:41:57 +00:00
|
|
|
exactly the same, except that generated data is now redirected to a
|
|
|
|
DisassemblyList structure rather than being printed.
|
|
|
|
|
|
|
|
All 7800-related stuff has been removed, as well as all commandline options.
|
2013-02-21 21:57:42 +00:00
|
|
|
Over time, some of the configurability of Distella may be added again.
|
2010-01-31 02:07:19 +00:00
|
|
|
|
|
|
|
@author Stephen Anthony
|
|
|
|
*/
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
class DiStella
|
|
|
|
{
|
2013-03-04 23:35:26 +00:00
|
|
|
public:
|
|
|
|
// A list of options that can be applied to the disassembly
|
|
|
|
// This will eventually grow to include all options supported by
|
|
|
|
// standalone Distella
|
|
|
|
typedef struct {
|
|
|
|
BaseFormat gfx_format;
|
2013-03-10 22:12:37 +00:00
|
|
|
bool show_addresses; // Show PC addresses (always off for external output)
|
|
|
|
bool aflag; // Turns 'A' off in accumulator instructions (-a in Distella)
|
2013-03-04 23:35:26 +00:00
|
|
|
bool fflag; // Forces correct address length (-f in Distella)
|
|
|
|
bool rflag; // Relocate calls out of address range (-r in Distella)
|
2013-03-10 22:12:37 +00:00
|
|
|
int bwidth; // Number of bytes to use per line (with .byte xxx)
|
2013-03-04 23:35:26 +00:00
|
|
|
} Settings;
|
|
|
|
static Settings settings; // Default settings
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
public:
|
2010-02-01 20:00:50 +00:00
|
|
|
/**
|
|
|
|
Disassemble the current state of the System from the given start address.
|
|
|
|
|
2010-06-03 12:41:49 +00:00
|
|
|
@param dbg The CartDebug instance containing all label information
|
2010-04-10 20:00:16 +00:00
|
|
|
@param list The results of the disassembly are placed here
|
2010-11-07 18:10:58 +00:00
|
|
|
@param info Various info about the current bank
|
2013-03-04 23:35:26 +00:00
|
|
|
@param settings The various distella flags/options to use
|
2010-11-07 18:10:58 +00:00
|
|
|
@param labels Array storing label info determined by Distella
|
|
|
|
@param directives Array storing directive info determined by Distella
|
2013-03-05 18:01:55 +00:00
|
|
|
@param reserved The TIA/RIOT addresses referenced in the disassembled code
|
2010-04-10 20:00:16 +00:00
|
|
|
@param resolvedata If enabled, try to determine code vs. data sections
|
2010-02-01 20:00:50 +00:00
|
|
|
*/
|
2010-06-03 12:41:49 +00:00
|
|
|
DiStella(const CartDebug& dbg, CartDebug::DisassemblyList& list,
|
2013-03-04 23:35:26 +00:00
|
|
|
CartDebug::BankInfo& info, const DiStella::Settings& settings,
|
2013-03-05 18:01:55 +00:00
|
|
|
uInt8* labels, uInt8* directives,
|
|
|
|
CartDebug::ReservedEquates& reserved, bool resolvedata);
|
2010-02-07 21:23:26 +00:00
|
|
|
|
|
|
|
~DiStella();
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
|
|
|
|
private:
|
2010-01-31 19:41:57 +00:00
|
|
|
// Indicate that a new line of disassembly has been completed
|
|
|
|
// In the original Distella code, this indicated a new line to be printed
|
2010-01-31 02:07:19 +00:00
|
|
|
// Here, we add a new entry to the DisassemblyList
|
2010-08-30 12:04:56 +00:00
|
|
|
void addEntry(CartDebug::DisasmType type);
|
|
|
|
|
|
|
|
// Process directives given in the list
|
|
|
|
// Directives are basically the contents of a distella configuration file
|
|
|
|
void processDirectives(const CartDebug::DirectiveList& directives);
|
2010-01-31 02:07:19 +00:00
|
|
|
|
|
|
|
// These functions are part of the original Distella code
|
2010-02-28 17:12:16 +00:00
|
|
|
void disasm(uInt32 distart, int pass);
|
2010-10-07 22:34:22 +00:00
|
|
|
bool check_range(uInt16 start, uInt16 end) const;
|
Properly implemented an hierarchy wrt marking an address in the disassembly
in a consistent way. Directives set manually have top priority, then the
results from a dynamic analysis (aka, from actually running the code), and
finally from a static analysis (aka, Distella itself).
Sometimes Distella will mark a section as CODE even if it hasn't been
marked as such dynamically. This occurs after a relative branch, which
Distella has no idea how to evaluate. It's possible that the code will
be executed eventually, but also that it will never be executed. As such,
these lines are marked with a '*', indicating that disassembly results
are tentative. If you get weird looking disassembly for these addresses,
it's probably a hint that it isn't really code at all.
PC addresses in the disassembly labels are now aligned with labels, and
shown in a lighter color. These can still be toggled on and off.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2162 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-10-23 20:57:31 +00:00
|
|
|
int mark(uInt32 address, uInt8 mask, bool directive = false);
|
2010-10-09 17:55:22 +00:00
|
|
|
bool check_bit(uInt16 address, uInt8 mask) const;
|
2010-01-31 02:07:19 +00:00
|
|
|
|
|
|
|
private:
|
2010-06-03 12:41:49 +00:00
|
|
|
const CartDebug& myDbg;
|
2010-02-28 17:12:16 +00:00
|
|
|
CartDebug::DisassemblyList& myList;
|
2013-03-04 23:35:26 +00:00
|
|
|
const Settings& mySettings;
|
2013-03-05 18:01:55 +00:00
|
|
|
CartDebug::ReservedEquates& myReserved;
|
2010-03-05 22:02:12 +00:00
|
|
|
stringstream myDisasmBuf;
|
2010-01-31 02:07:19 +00:00
|
|
|
queue<uInt16> myAddressQueue;
|
2010-04-06 15:15:44 +00:00
|
|
|
uInt16 myOffset, myPC, myPCBeg, myPCEnd;
|
2010-01-31 02:07:19 +00:00
|
|
|
|
|
|
|
struct resource {
|
|
|
|
uInt16 start;
|
|
|
|
uInt16 end;
|
2010-04-06 15:15:44 +00:00
|
|
|
uInt16 length;
|
2010-01-31 02:07:19 +00:00
|
|
|
} myAppData;
|
|
|
|
|
Properly implemented an hierarchy wrt marking an address in the disassembly
in a consistent way. Directives set manually have top priority, then the
results from a dynamic analysis (aka, from actually running the code), and
finally from a static analysis (aka, Distella itself).
Sometimes Distella will mark a section as CODE even if it hasn't been
marked as such dynamically. This occurs after a relative branch, which
Distella has no idea how to evaluate. It's possible that the code will
be executed eventually, but also that it will never be executed. As such,
these lines are marked with a '*', indicating that disassembly results
are tentative. If you get weird looking disassembly for these addresses,
it's probably a hint that it isn't really code at all.
PC addresses in the disassembly labels are now aligned with labels, and
shown in a lighter color. These can still be toggled on and off.
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2162 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-10-23 20:57:31 +00:00
|
|
|
/* Stores info on how each address is marked, both in the general
|
|
|
|
case as well as when manual directives are enabled (in which case
|
|
|
|
the directives take priority
|
2013-03-05 18:01:55 +00:00
|
|
|
The address mark type is defined in CartDebug.hxx
|
|
|
|
*/
|
2010-11-07 18:10:58 +00:00
|
|
|
uInt8 *myLabels, *myDirectives;
|
2010-01-31 02:07:19 +00:00
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
|
|
|
/**
|
|
|
|
Enumeration of the 6502 addressing modes
|
|
|
|
*/
|
|
|
|
enum AddressingMode
|
|
|
|
{
|
|
|
|
IMPLIED, ACCUMULATOR, IMMEDIATE,
|
|
|
|
ZERO_PAGE, ZERO_PAGE_X, ZERO_PAGE_Y,
|
|
|
|
ABSOLUTE, ABSOLUTE_X, ABSOLUTE_Y,
|
|
|
|
ABS_INDIRECT, INDIRECT_X, INDIRECT_Y,
|
|
|
|
RELATIVE, ASS_CODE
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
Enumeration of the 6502 access modes
|
|
|
|
*/
|
|
|
|
enum AccessMode
|
|
|
|
{
|
|
|
|
M_NONE, M_AC, M_XR, M_YR, M_SP, M_SR, M_PC, M_IMM, M_ZERO, M_ZERX, M_ZERY,
|
|
|
|
M_ABS, M_ABSX, M_ABSY, M_AIND, M_INDX, M_INDY, M_REL, M_FC, M_FD, M_FI,
|
|
|
|
M_FV, M_ADDR, M_,
|
|
|
|
|
|
|
|
M_ACIM, /* Source: AC & IMMED (bus collision) */
|
|
|
|
M_ANXR, /* Source: AC & XR (bus collision) */
|
|
|
|
M_AXIM, /* Source: (AC | #EE) & XR & IMMED (bus collision) */
|
|
|
|
M_ACNC, /* Dest: M_AC and Carry = Negative */
|
|
|
|
M_ACXR, /* Dest: M_AC, M_XR */
|
|
|
|
|
|
|
|
M_SABY, /* Source: (ABS_Y & SP) (bus collision) */
|
|
|
|
M_ACXS, /* Dest: M_AC, M_XR, M_SP */
|
|
|
|
M_STH0, /* Dest: Store (src & Addr_Hi+1) to (Addr +0x100) */
|
|
|
|
M_STH1,
|
|
|
|
M_STH2,
|
|
|
|
M_STH3
|
|
|
|
};
|
|
|
|
|
2010-02-27 21:24:24 +00:00
|
|
|
/**
|
|
|
|
Enumeration of the 6502 read/write mode
|
|
|
|
(if the opcode is reading or writing its operand)
|
|
|
|
*/
|
|
|
|
enum ReadWriteMode
|
|
|
|
{
|
|
|
|
READ, WRITE, NONE
|
|
|
|
};
|
|
|
|
|
OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
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struct Instruction_tag {
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const char* mnemonic;
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AddressingMode addr_mode;
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AccessMode source;
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2010-02-27 21:24:24 +00:00
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ReadWriteMode rw_mode;
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OK, this is the first pass at a huge reorganization of the debugger
classes. First off, the distella code has been integrated into a
DiStella class. This code isn't yet tied to the debugger, but it does
at least compile and generate valid output.
The RamDebug class has been replaced by a CartDebug class, which
takes responsibility for the previous RamDebug stuff as well as
things related to Cart address space (read from write ports,
disassembly, etc).
Fixed E7 bankswitching when reading from the write port in the upper
256byte area.
Fixed 'read from write port functionality' in general for all carts
that supported it previously. Basically, if _rwport is enabled, the
address is checked to be an actual read (vs. one that's part of a
normal write cycle), *and* it's actually an illegal access (each
cart/bankswitch type now provides a hint to indicate this condition).
Still TODO is clean up the rework, properly integrate DiStella, and
fix labels and defines (which seem to be completely broken).
git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@1922 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
2010-01-17 16:48:45 +00:00
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uInt8 cycles;
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};
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static const Instruction_tag ourLookup[256];
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};
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#endif
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