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Fix reset of NMI pending flag.

This commit is contained in:
Brandon Wright 2018-05-02 10:00:27 -05:00
parent b9dd7021cf
commit 070d5e5dbf
6 changed files with 9 additions and 11 deletions
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2
cpu.cpp
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@ -227,7 +227,7 @@ static void S9xSoftResetCPU (void)
CPU.V_Counter = 0; CPU.V_Counter = 0;
CPU.Flags = CPU.Flags & (DEBUG_MODE_FLAG | TRACE_FLAG); CPU.Flags = CPU.Flags & (DEBUG_MODE_FLAG | TRACE_FLAG);
CPU.PCBase = NULL; CPU.PCBase = NULL;
CPU.NMILine = FALSE; CPU.NMIPending = FALSE;
CPU.IRQLine = FALSE; CPU.IRQLine = FALSE;
CPU.IRQTransition = FALSE; CPU.IRQTransition = FALSE;
CPU.IRQLastState = FALSE; CPU.IRQLastState = FALSE;

8
cpuexec.cpp
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@ -209,11 +209,11 @@ void S9xMainLoop (void)
{ {
for (;;) for (;;)
{ {
if (CPU.NMILine) if (CPU.NMIPending)
{ {
if (Timings.NMITriggerPos <= CPU.Cycles) if (Timings.NMITriggerPos <= CPU.Cycles)
{ {
CPU.NMILine = FALSE; CPU.NMIPending = FALSE;
Timings.NMITriggerPos = 0xffff; Timings.NMITriggerPos = 0xffff;
if (CPU.WaitingForInterrupt) if (CPU.WaitingForInterrupt)
{ {
@ -439,8 +439,6 @@ void S9xDoHEventProcessing (void)
// FIXME: reading $4210 will wait 2 cycles, then perform reading, then wait 4 more cycles. // FIXME: reading $4210 will wait 2 cycles, then perform reading, then wait 4 more cycles.
Memory.FillRAM[0x4210] = Model->_5A22; Memory.FillRAM[0x4210] = Model->_5A22;
CPU.NMILine = FALSE;
Timings.NMITriggerPos = 0xffff;
ICPU.Frame++; ICPU.Frame++;
PPU.HVBeamCounterLatched = 0; PPU.HVBeamCounterLatched = 0;
@ -507,7 +505,7 @@ void S9xDoHEventProcessing (void)
{ {
// FIXME: triggered at HC=6, checked just before the final CPU cycle, // FIXME: triggered at HC=6, checked just before the final CPU cycle,
// then, when to call S9xOpcode_NMI()? // then, when to call S9xOpcode_NMI()?
CPU.NMILine = TRUE; CPU.NMIPending = TRUE;
Timings.NMITriggerPos = 6 + 6; Timings.NMITriggerPos = 6 + 6;
} }

2
dma.cpp
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@ -1288,7 +1288,7 @@ bool8 S9xDoDMA (uint8 Channel)
} }
} }
if (CPU.NMILine && (Timings.NMITriggerPos != 0xffff)) if (CPU.NMIPending && (Timings.NMITriggerPos != 0xffff))
{ {
Timings.NMITriggerPos = CPU.Cycles + Timings.NMIDMADelay; Timings.NMITriggerPos = CPU.Cycles + Timings.NMIDMADelay;
if (Timings.NMITriggerPos >= Timings.H_Max) if (Timings.NMITriggerPos >= Timings.H_Max)

2
ppu.cpp
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@ -1513,7 +1513,7 @@ void S9xSetCPU (uint8 Byte, uint16 Address)
{ {
// FIXME: triggered at HC+=6, checked just before the final CPU cycle, // FIXME: triggered at HC+=6, checked just before the final CPU cycle,
// then, when to call S9xOpcode_NMI()? // then, when to call S9xOpcode_NMI()?
CPU.NMILine = TRUE; CPU.NMIPending = TRUE;
Timings.NMITriggerPos = CPU.Cycles + 6 + 6; Timings.NMITriggerPos = CPU.Cycles + 6 + 6;
} }

4
snapshot.cpp
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@ -384,7 +384,7 @@ static FreezeData SnapCPU[] =
DELETED_INT_ENTRY(6, 7, WaitAddress, 4), DELETED_INT_ENTRY(6, 7, WaitAddress, 4),
DELETED_INT_ENTRY(6, 7, WaitCounter, 4), DELETED_INT_ENTRY(6, 7, WaitCounter, 4),
DELETED_INT_ENTRY(6, 7, PBPCAtOpcodeStart, 4), DELETED_INT_ENTRY(6, 7, PBPCAtOpcodeStart, 4),
INT_ENTRY(7, NMILine), INT_ENTRY(7, NMIPending),
INT_ENTRY(7, IRQLine), INT_ENTRY(7, IRQLine),
INT_ENTRY(7, IRQTransition), INT_ENTRY(7, IRQTransition),
INT_ENTRY(7, IRQLastState), INT_ENTRY(7, IRQLastState),
@ -1745,7 +1745,7 @@ int S9xUnfreezeFromStream (STREAM stream)
{ {
printf("Converting old snapshot version %d to %d\n...", version, SNAPSHOT_VERSION); printf("Converting old snapshot version %d to %d\n...", version, SNAPSHOT_VERSION);
CPU.NMILine = (CPU.Flags & (1 << 7)) ? TRUE : FALSE; CPU.NMIPending = (CPU.Flags & (1 << 7)) ? TRUE : FALSE;
CPU.IRQLine = (CPU.Flags & (1 << 11)) ? TRUE : FALSE; CPU.IRQLine = (CPU.Flags & (1 << 11)) ? TRUE : FALSE;
CPU.IRQTransition = FALSE; CPU.IRQTransition = FALSE;
CPU.IRQLastState = FALSE; CPU.IRQLastState = FALSE;

2
snes9x.h
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@ -303,7 +303,7 @@ struct SCPUState
int32 PrevCycles; int32 PrevCycles;
int32 V_Counter; int32 V_Counter;
uint8 *PCBase; uint8 *PCBase;
bool8 NMILine; bool8 NMIPending;
bool8 IRQLine; bool8 IRQLine;
bool8 IRQTransition; bool8 IRQTransition;
bool8 IRQLastState; bool8 IRQLastState;