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Merge pull request #850 from raven02/patch-4 

Stub DCBI instruction
This commit is contained in:
Alexandro Sánchez Bach 2014-10-26 11:59:39 +01:00
parent d26f7f696d f54a5c6591
commit 7258ddc318
6 changed files with 22 additions and 13 deletions
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5
rpcs3/Emu/Cell/PPUDisAsm.h
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@ -1600,7 +1600,10 @@ private:
default: DisAsm_IMM_R1("mtspr", spr, rs); break; default: DisAsm_IMM_R1("mtspr", spr, rs); break;
} }
} }
/*0x1d6*///DCBI void DCBI(u32 ra, u32 rb)
{
DisAsm_R2("dcbi", ra, rb);
}
void NAND(u32 ra, u32 rs, u32 rb, bool rc) void NAND(u32 ra, u32 rs, u32 rb, bool rc)
{ {
DisAsm_R3_RC("nand", ra, rs, rb, rc); DisAsm_R3_RC("nand", ra, rs, rb, rc);

4
rpcs3/Emu/Cell/PPUInstrTable.h
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@ -527,7 +527,7 @@ namespace PPU_instr
/*0x1c9*/bind_instr(g1f_list, DIVDU, RD, RA, RB, OE, RC); /*0x1c9*/bind_instr(g1f_list, DIVDU, RD, RA, RB, OE, RC);
/*0x1cb*/bind_instr(g1f_list, DIVWU, RD, RA, RB, OE, RC); /*0x1cb*/bind_instr(g1f_list, DIVWU, RD, RA, RB, OE, RC);
/*0x1d3*/bind_instr(g1f_list, MTSPR, SPR, RS); /*0x1d3*/bind_instr(g1f_list, MTSPR, SPR, RS);
/*0x1d6*///DCBI /*0x1d6*/bind_instr(g1f_list, DCBI, RA, RB);
/*0x1dc*/bind_instr(g1f_list, NAND, RA, RS, RB, RC); /*0x1dc*/bind_instr(g1f_list, NAND, RA, RS, RB, RC);
/*0x1e7*/bind_instr(g1f_list, STVXL, VS, RA, RB); /*0x1e7*/bind_instr(g1f_list, STVXL, VS, RA, RB);
/*0x1e9*/bind_instr(g1f_list, DIVD, RD, RA, RB, OE, RC); /*0x1e9*/bind_instr(g1f_list, DIVD, RD, RA, RB, OE, RC);
@ -629,4 +629,4 @@ namespace PPU_instr
static auto BLR = std::bind(BCLR, 0x10 | 0x04, 0, 0, 0); static auto BLR = std::bind(BCLR, 0x10 | 0x04, 0, 0, 0);
#undef bind_instr #undef bind_instr
}; };

4
rpcs3/Emu/Cell/PPUInterpreter.h
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@ -2858,7 +2858,9 @@ private:
{ {
GetRegBySPR(spr) = CPU.GPR[rs]; GetRegBySPR(spr) = CPU.GPR[rs];
} }
/*0x1d6*///DCBI void DCBI(u32 ra, u32 rb)
{
}
void NAND(u32 ra, u32 rs, u32 rb, bool rc) void NAND(u32 ra, u32 rs, u32 rb, bool rc)
{ {
CPU.GPR[ra] = ~(CPU.GPR[rs] & CPU.GPR[rb]); CPU.GPR[ra] = ~(CPU.GPR[rs] & CPU.GPR[rb]);

4
rpcs3/Emu/Cell/PPULLVMRecompiler.cpp
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@ -1592,6 +1592,10 @@ void PPULLVMRecompiler::CRXOR(u32 crbd, u32 crba, u32 crbb) {
//InterpreterCall("CRXOR", &PPUInterpreter::CRXOR, crbd, crba, crbb); //InterpreterCall("CRXOR", &PPUInterpreter::CRXOR, crbd, crba, crbb);
} }
void PPULLVMRecompiler::DCBI(u32 ra, u32 rb) {
InterpreterCall("DCBI", &PPUInterpreter::DCBI, ra, rb);
}
void PPULLVMRecompiler::CRNAND(u32 crbd, u32 crba, u32 crbb) { void PPULLVMRecompiler::CRNAND(u32 crbd, u32 crba, u32 crbb) {
auto cr_i32 = GetCr(); auto cr_i32 = GetCr();
auto ba_i32 = GetBit(cr_i32, crba); auto ba_i32 = GetBit(cr_i32, crba);

2
rpcs3/Emu/Cell/PPULLVMRecompiler.h
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@ -330,7 +330,7 @@ protected:
void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override;
void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override;
void MTSPR(u32 spr, u32 rs) override; void MTSPR(u32 spr, u32 rs) override;
//DCBI void DCBI(u32 ra, u32 rb) override;
void NAND(u32 ra, u32 rs, u32 rb, bool rc) override; void NAND(u32 ra, u32 rs, u32 rb, bool rc) override;
void STVXL(u32 vs, u32 ra, u32 rb) override; void STVXL(u32 vs, u32 ra, u32 rb) override;
void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override; void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override;

16
rpcs3/Emu/Cell/PPUOpcodes.h
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@ -276,7 +276,7 @@ namespace PPU_opcodes
LVEHX = 0x027, //Load Vector Element Halfword Indexed LVEHX = 0x027, //Load Vector Element Halfword Indexed
SUBF = 0x028, SUBF = 0x028,
LDUX = 0x035, //Load Doubleword with Update Indexed LDUX = 0x035, //Load Doubleword with Update Indexed
DCBST = 0x036, DCBST = 0x036, //Data Cache Block Store
LWZUX = 0x037, LWZUX = 0x037,
CNTLZD = 0x03a, CNTLZD = 0x03a,
ANDC = 0x03c, ANDC = 0x03c,
@ -285,7 +285,7 @@ namespace PPU_opcodes
MULHD = 0x049, MULHD = 0x049,
MULHW = 0x04b, MULHW = 0x04b,
LDARX = 0x054, LDARX = 0x054,
DCBF = 0x056, DCBF = 0x056, //Data Cache Block Flush
LBZX = 0x057, LBZX = 0x057,
LVX = 0x067, //Load Vector Indexed LVX = 0x067, //Load Vector Indexed
NEG = 0x068, NEG = 0x068,
@ -311,11 +311,11 @@ namespace PPU_opcodes
MULLD = 0x0e9, MULLD = 0x0e9,
ADDME = 0x0ea, ADDME = 0x0ea,
MULLW = 0x0eb, MULLW = 0x0eb,
DCBTST = 0x0f6, DCBTST = 0x0f6, //Data Cache Block Touch for Store
STBUX = 0x0f7, STBUX = 0x0f7,
DOZ = 0x108, DOZ = 0x108,
ADD = 0x10a, ADD = 0x10a,
DCBT = 0x116, DCBT = 0x116, //Data Cache Block Touch
LHZX = 0x117, LHZX = 0x117,
EQV = 0x11c, EQV = 0x11c,
ECIWX = 0x136, ECIWX = 0x136,
@ -338,7 +338,7 @@ namespace PPU_opcodes
DIVDU = 0x1c9, DIVDU = 0x1c9,
DIVWU = 0x1cb, DIVWU = 0x1cb,
MTSPR = 0x1d3, MTSPR = 0x1d3,
DCBI = 0x1d6, DCBI = 0x1d6, //Data Cache Block Invalidate
NAND = 0x1dc, NAND = 0x1dc,
STVXL = 0x1e7, //Store Vector Indexed Last STVXL = 0x1e7, //Store Vector Indexed Last
DIVD = 0x1e9, DIVD = 0x1e9,
@ -382,8 +382,8 @@ namespace PPU_opcodes
EXTSB = 0x3ba, EXTSB = 0x3ba,
STFIWX = 0x3d7, STFIWX = 0x3d7,
EXTSW = 0x3da, EXTSW = 0x3da,
ICBI = 0x3d6, ICBI = 0x3d6, //Instruction Cache Block Invalidate
DCBZ = 0x3f6, DCBZ = 0x3f6, //Data Cache Block Set to Zero
}; };
enum G_3aOpcodes //Field 30 - 31 enum G_3aOpcodes //Field 30 - 31
@ -738,7 +738,7 @@ public:
virtual void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; virtual void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
virtual void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; virtual void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
virtual void MTSPR(u32 spr, u32 rs) = 0; virtual void MTSPR(u32 spr, u32 rs) = 0;
//DCBI virtual void DCBI(u32 ra, u32 rb) = 0;
virtual void NAND(u32 ra, u32 rs, u32 rb, bool rc) = 0; virtual void NAND(u32 ra, u32 rs, u32 rb, bool rc) = 0;
virtual void STVXL(u32 vs, u32 ra, u32 rb) = 0; virtual void STVXL(u32 vs, u32 ra, u32 rb) = 0;
virtual void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; virtual void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;