From f54a5c6591e6006ea5327e4f4bc49d231575163c Mon Sep 17 00:00:00 2001
From: raven02 <jacky.kktsui@yahoo.com.hk>
Date: Sun, 26 Oct 2014 04:53:55 +0800
Subject: [PATCH] Stub DCBI instruction

---
 rpcs3/Emu/Cell/PPUDisAsm.h           |  5 ++++-
 rpcs3/Emu/Cell/PPUInstrTable.h       |  4 ++--
 rpcs3/Emu/Cell/PPUInterpreter.h      |  4 +++-
 rpcs3/Emu/Cell/PPULLVMRecompiler.cpp |  4 ++++
 rpcs3/Emu/Cell/PPULLVMRecompiler.h   |  2 +-
 rpcs3/Emu/Cell/PPUOpcodes.h          | 16 ++++++++--------
 6 files changed, 22 insertions(+), 13 deletions(-)

diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h
index 81cd3029d4..8a04164f2e 100644
--- a/rpcs3/Emu/Cell/PPUDisAsm.h
+++ b/rpcs3/Emu/Cell/PPUDisAsm.h
@@ -1600,7 +1600,10 @@ private:
 		default: DisAsm_IMM_R1("mtspr", spr, rs); break;
 		}
 	}
-	/*0x1d6*///DCBI
+	void DCBI(u32 ra, u32 rb)
+	{
+		DisAsm_R2("dcbi", ra, rb);
+	}
 	void NAND(u32 ra, u32 rs, u32 rb, bool rc)
 	{
 		DisAsm_R3_RC("nand", ra, rs, rb, rc);
diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h
index 4c5b42c4db..77f742d467 100644
--- a/rpcs3/Emu/Cell/PPUInstrTable.h
+++ b/rpcs3/Emu/Cell/PPUInstrTable.h
@@ -527,7 +527,7 @@ namespace PPU_instr
 	/*0x1c9*/bind_instr(g1f_list, DIVDU, RD, RA, RB, OE, RC);
 	/*0x1cb*/bind_instr(g1f_list, DIVWU, RD, RA, RB, OE, RC);
 	/*0x1d3*/bind_instr(g1f_list, MTSPR, SPR, RS);
-	/*0x1d6*///DCBI
+	/*0x1d6*/bind_instr(g1f_list, DCBI, RA, RB);
 	/*0x1dc*/bind_instr(g1f_list, NAND, RA, RS, RB, RC);
 	/*0x1e7*/bind_instr(g1f_list, STVXL, VS, RA, RB);
 	/*0x1e9*/bind_instr(g1f_list, DIVD, RD, RA, RB, OE, RC);
@@ -629,4 +629,4 @@ namespace PPU_instr
 	static auto BLR = std::bind(BCLR, 0x10 | 0x04, 0, 0, 0);
 
 	#undef bind_instr
-};
\ No newline at end of file
+};
diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h
index cdb7a2d2ce..bf0ead8dd5 100644
--- a/rpcs3/Emu/Cell/PPUInterpreter.h
+++ b/rpcs3/Emu/Cell/PPUInterpreter.h
@@ -2858,7 +2858,9 @@ private:
 	{
 		GetRegBySPR(spr) = CPU.GPR[rs];
 	}
-	/*0x1d6*///DCBI
+	void DCBI(u32 ra, u32 rb)
+	{
+	}
 	void NAND(u32 ra, u32 rs, u32 rb, bool rc)
 	{
 		CPU.GPR[ra] = ~(CPU.GPR[rs] & CPU.GPR[rb]);
diff --git a/rpcs3/Emu/Cell/PPULLVMRecompiler.cpp b/rpcs3/Emu/Cell/PPULLVMRecompiler.cpp
index bca47723e3..eba1940139 100644
--- a/rpcs3/Emu/Cell/PPULLVMRecompiler.cpp
+++ b/rpcs3/Emu/Cell/PPULLVMRecompiler.cpp
@@ -1592,6 +1592,10 @@ void PPULLVMRecompiler::CRXOR(u32 crbd, u32 crba, u32 crbb) {
     //InterpreterCall("CRXOR", &PPUInterpreter::CRXOR, crbd, crba, crbb);
 }
 
+void PPULLVMRecompiler::DCBI(u32 ra, u32 rb) {
+    InterpreterCall("DCBI", &PPUInterpreter::DCBI, ra, rb);
+}
+
 void PPULLVMRecompiler::CRNAND(u32 crbd, u32 crba, u32 crbb) {
     auto cr_i32  = GetCr();
     auto ba_i32  = GetBit(cr_i32, crba);
diff --git a/rpcs3/Emu/Cell/PPULLVMRecompiler.h b/rpcs3/Emu/Cell/PPULLVMRecompiler.h
index 218dad9721..b73aab049c 100644
--- a/rpcs3/Emu/Cell/PPULLVMRecompiler.h
+++ b/rpcs3/Emu/Cell/PPULLVMRecompiler.h
@@ -330,7 +330,7 @@ protected:
     void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override;
     void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override;
     void MTSPR(u32 spr, u32 rs) override;
-    //DCBI
+    void DCBI(u32 ra, u32 rb) override;
     void NAND(u32 ra, u32 rs, u32 rb, bool rc) override;
     void STVXL(u32 vs, u32 ra, u32 rb) override;
     void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) override;
diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h
index 150275ae9c..9fbe5e8d79 100644
--- a/rpcs3/Emu/Cell/PPUOpcodes.h
+++ b/rpcs3/Emu/Cell/PPUOpcodes.h
@@ -276,7 +276,7 @@ namespace PPU_opcodes
 		LVEHX  = 0x027, //Load Vector Element Halfword Indexed
 		SUBF   = 0x028,
 		LDUX   = 0x035, //Load Doubleword with Update Indexed
-		DCBST  = 0x036,
+		DCBST  = 0x036, //Data Cache Block Store
 		LWZUX  = 0x037,
 		CNTLZD = 0x03a,
 		ANDC   = 0x03c,
@@ -285,7 +285,7 @@ namespace PPU_opcodes
 		MULHD  = 0x049,
 		MULHW  = 0x04b,
 		LDARX  = 0x054,
-		DCBF   = 0x056,
+		DCBF   = 0x056, //Data Cache Block Flush
 		LBZX   = 0x057,
 		LVX    = 0x067, //Load Vector Indexed
 		NEG    = 0x068,
@@ -311,11 +311,11 @@ namespace PPU_opcodes
 		MULLD  = 0x0e9,
 		ADDME  = 0x0ea,
 		MULLW  = 0x0eb,
-		DCBTST = 0x0f6,
+		DCBTST = 0x0f6, //Data Cache Block Touch for Store
 		STBUX  = 0x0f7,
 		DOZ    = 0x108,
 		ADD    = 0x10a,
-		DCBT   = 0x116,
+		DCBT   = 0x116, //Data Cache Block Touch
 		LHZX   = 0x117,
 		EQV    = 0x11c,
 		ECIWX  = 0x136,
@@ -338,7 +338,7 @@ namespace PPU_opcodes
 		DIVDU  = 0x1c9,
 		DIVWU  = 0x1cb,
 		MTSPR  = 0x1d3,
-		DCBI   = 0x1d6,
+		DCBI   = 0x1d6, //Data Cache Block Invalidate
 		NAND   = 0x1dc,
 		STVXL  = 0x1e7, //Store Vector Indexed Last
 		DIVD   = 0x1e9,
@@ -382,8 +382,8 @@ namespace PPU_opcodes
 		EXTSB  = 0x3ba,
 		STFIWX = 0x3d7,
 		EXTSW  = 0x3da,
-		ICBI   = 0x3d6,
-		DCBZ   = 0x3f6,
+		ICBI   = 0x3d6, //Instruction Cache Block Invalidate
+		DCBZ   = 0x3f6, //Data Cache Block Set to Zero
 	};
 
 	enum G_3aOpcodes //Field 30 - 31
@@ -738,7 +738,7 @@ public:
 	virtual void DIVDU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
 	virtual void DIVWU(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;
 	virtual void MTSPR(u32 spr, u32 rs) = 0;
-	//DCBI
+	virtual void DCBI(u32 ra, u32 rb) = 0;
 	virtual void NAND(u32 ra, u32 rs, u32 rb, bool rc) = 0;
 	virtual void STVXL(u32 vs, u32 ra, u32 rb) = 0;
 	virtual void DIVD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0;