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redream
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370 Commits 3 Branches 1 Tag 32 MiB
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370 Commits

Author SHA1 Message Date
Anthony Pesch d8087b941e don't assert on invalid instruction when disassembling 2016-02-12 17:28:38 -08:00
Anthony Pesch 35c55a653c warn on invalid memory read or write from a dynamic region 2016-02-12 17:28:38 -08:00
Anthony Pesch 518034455c change default bios path 2016-02-12 17:28:38 -08:00
Anthony Pesch 00bc388e10 enabled 1 and 2 byte access to wave memory 2016-02-12 17:28:38 -08:00
Anthony Pesch 72b5edbeba replaced horribly broken 64-bit float implementation 2016-02-12 17:28:38 -08:00
Anthony Pesch 8d9987843d added IRReader for deserializing IRWriter output 2016-02-12 17:28:38 -08:00
Anthony Pesch 4be33f7ee4 removed core.h, added config.h.in 2016-02-12 17:28:37 -08:00
Anthony Pesch 25eccee9f4 improved IR writing 2016-02-12 17:28:37 -08:00
Anthony Pesch 9ce4318d24 rename sh4_instr.cc 2016-02-12 17:28:37 -08:00
Anthony Pesch f457e8e9d8 added OP_LOAD_HOST and OP_STORE_HOST for directly accessing host memory 
added lookup table for fsca
removed sin, cos ir ops
 2016-02-12 17:28:37 -08:00
Anthony Pesch a039b60d52 get tests back running 2016-02-12 17:28:37 -08:00
Anthony Pesch f729894480 simplified dreamcast structure so it can be reused with stubs by tests 2016-02-12 17:28:37 -08:00
Anthony Pesch 631a23c11f disable unused aica regs 2016-02-12 17:28:37 -08:00
Anthony Pesch 57944b3ceb refactored scheduler to more fairly update timers 2016-02-12 17:28:37 -08:00
Anthony Pesch 3c5d1526b9 group x64 blocks together under the same symbol for profiling 2016-02-12 17:28:36 -08:00
Anthony Pesch 4c8c48086b mark threads for profiler 2016-02-12 17:28:36 -08:00
Anthony Pesch e1db917a4e initial multithreaded rendering 2016-02-12 17:28:36 -08:00
Anthony Pesch 19a188d9c2 graceful shutdown 2016-02-12 17:28:36 -08:00
Anthony Pesch 6c72c2a3ba remove old tty related events 2016-02-12 17:28:36 -08:00
Anthony Pesch 2a17810a25 msvc compilation fixes 2016-02-12 17:28:36 -08:00
Anthony Pesch 9528d9beaa removed beaengine 2016-02-12 17:28:36 -08:00
Anthony Pesch 20a1437f96 replaced ringbuffer usage in register allocation with minmax heap 
removed terrible insert method from ringbuffer
 2016-02-12 17:28:31 -08:00
Anthony Pesch 590ecc3849 added source map support for translating host addresses back to guest addresses 
added guest address ir opcodes for actually emitting the debug address information
added support for recompiling blocks instead of backpatching for when slow memory access is needed
 2016-01-16 13:28:12 -08:00
Anthony Pesch 4542ef4888 renamed dreavm namespace 2016-01-16 13:26:56 -08:00
Anthony Pesch afacb09ac2 don't test ctx_.pc to terminate loop in Run 2016-01-05 01:35:24 -08:00
Anthony Pesch 7f5be10b66 moved Runtime to SH4CodeCache 
added --interpreter command line option
 2016-01-04 23:50:25 -08:00
Anthony Pesch 8c4da71deb add debugbreak on LOG_FATAL's in debug builds 2016-01-04 00:49:03 -08:00
Anthony Pesch c7cf96317a cache register pointers directly in interpreter 2016-01-04 00:49:03 -08:00
Anthony Pesch fe60ecbb83 simplify code cache entries 
generate unique function call per interpreted block to aid in branch prediction
 2016-01-04 00:49:03 -08:00
Anthony Pesch 40733aefcb inline cycle tracking into block epilog and out of main loop 
added IRBuilder::Get/SetInsertPoint
 2016-01-04 00:49:03 -08:00
Anthony Pesch 71f9290ea4 removed remnants of old branch support 2016-01-04 00:49:03 -08:00
Anthony Pesch 3948eb70a9 cross-platform networking shim 2016-01-04 00:49:03 -08:00
Anthony Pesch 6bc0c08d45 removed Runtime::set_compile_handler 2016-01-04 00:49:02 -08:00
Anthony Pesch ca23cbc1b9 split up memory map / memory code 2016-01-04 00:48:56 -08:00
Anthony Pesch a08f110658 simplified sh4 test generation and execution 2015-12-05 19:56:41 -08:00
Anthony Pesch 178c61ec4a don't use unions of bitfields for SR and FPSCR registers 2015-12-02 23:30:04 -08:00
Anthony Pesch 79322e80af remove old_sr and old_fpscr 2015-12-02 20:19:38 -08:00
Anthony Pesch 5454991347 move memory access watch code into sys 2015-12-02 18:22:23 -08:00
Anthony Pesch 90013d6f3c reworked memory.cc to split out address map and core memory code 2015-12-02 18:21:51 -08:00
Anthony Pesch e94e0b6979 removed unused virtual tty 2015-12-02 00:09:59 -08:00
Anthony Pesch 0e803c3f70 map static banks to page table as well 2015-12-02 00:09:50 -08:00
Anthony Pesch 5c52954544 specify SEC_COMMIT to CreateFileMapping, resulting in mapped views automatically having their pages committed 2015-11-23 15:30:28 -08:00
Anthony Pesch c4879c3a16 global interpreter state 2015-11-08 23:49:00 -08:00
Anthony Pesch fc895201a2 slim down number of parameters required by RuntimeBlock::call 2015-11-08 19:31:14 -08:00
Anthony Pesch 21de83cbde remove complicated register preserve functionality now that ir blocks no longer branch 2015-11-05 00:17:57 -08:00
Anthony Pesch d01780286e added ashd and lshd op codes 2015-11-04 23:55:51 -08:00
Anthony Pesch 55170120f0 removed ir level branch from pref translation 2015-11-03 23:50:51 -08:00
Anthony Pesch d5001494a0 sh4 has only 24 general purpose registers, not 32, optimized rbank related opcodes with this realization 2015-11-03 16:50:21 -08:00
Anthony Pesch 8c578f922b readability improvements 2015-10-31 19:42:15 -07:00
Anthony Pesch 82881a4b2f added clang-tidy build step 2015-10-31 19:42:11 -07:00