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sh4 has only 24 general purpose registers, not 32, optimized rbank related opcodes with this realization

This commit is contained in:
Anthony Pesch 2015-11-03 16:50:21 -08:00
parent 8c578f922b
commit d5001494a0
3 changed files with 19 additions and 102 deletions
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12
src/hw/sh4/sh4.cc
View File

@ -322,13 +322,15 @@ void SH4::FPSCRUpdated(SH4Context *ctx) {
void SH4::SetRegisterBank(int bank) {
if (bank == 0) {
for (int s = 0; s < 8; s++) {
ctx_.rbnk[1][s] = ctx_.r[s];
ctx_.r[s] = ctx_.rbnk[0][s];
uint32_t tmp = ctx_.r[s];
ctx_.r[s] = ctx_.ralt[s];
ctx_.ralt[s] = tmp;
}
} else {
} else if (bank == 1) {
for (int s = 0; s < 8; s++) {
ctx_.rbnk[0][s] = ctx_.r[s];
ctx_.r[s] = ctx_.rbnk[1][s];
uint32_t tmp = ctx_.r[s];
ctx_.r[s] = ctx_.ralt[s];
ctx_.ralt[s] = tmp;
}
}
}

107
src/jit/frontend/sh4/sh4_builder.cc
View File

@ -1360,29 +1360,9 @@ EMITTER(LDCDBR) {
// LDC.L Rm,Rn_BANK
EMITTER(LDCRBANK) {
Block *rb1 = b.AppendBlock();
Block *rb0 = b.AppendBlock();
Block *end_block = b.AppendBlock();
int reg = i.Rn & 0x7;
b.BranchCond(b.And(b.LoadSR(), b.AllocConstant(RB)), rb1, rb0);
{
b.SetCurrentBlock(rb1);
Value *rm = b.LoadRegister(i.Rm, VALUE_I32);
b.StoreContext(offsetof(SH4Context, rbnk[0]) + reg * 4, rm);
b.Branch(end_block);
}
{
b.SetCurrentBlock(rb0);
Value *rm = b.LoadRegister(i.Rm, VALUE_I32);
b.StoreContext(offsetof(SH4Context, rbnk[1]) + reg * 4, rm);
b.Branch(end_block);
}
b.SetCurrentBlock(end_block);
Value *rm = b.LoadRegister(i.Rm, VALUE_I32);
b.StoreContext(offsetof(SH4Context, ralt) + reg * 4, rm);
}
// LDC.L @Rm+,SR
@ -1437,33 +1417,11 @@ EMITTER(LDCMDBR) {
// LDC.L @Rm+,Rn_BANK
EMITTER(LDCMRBANK) {
Block *rb1 = b.AppendBlock();
Block *rb0 = b.AppendBlock();
Block *end_block = b.AppendBlock();
int reg = i.Rn & 0x7;
b.BranchCond(b.And(b.LoadSR(), b.AllocConstant(RB)), rb1, rb0);
{
b.SetCurrentBlock(rb0);
Value *addr = b.LoadRegister(i.Rm, VALUE_I32);
b.StoreRegister(i.Rm, b.Add(addr, b.AllocConstant(4)));
Value *v = b.Load(addr, VALUE_I32);
b.StoreContext(offsetof(SH4Context, rbnk[1]) + reg * 4, v);
b.Branch(end_block);
}
{
b.SetCurrentBlock(rb1);
Value *addr = b.LoadRegister(i.Rm, VALUE_I32);
b.StoreRegister(i.Rm, b.Add(addr, b.AllocConstant(4)));
Value *v = b.Load(addr, VALUE_I32);
b.StoreContext(offsetof(SH4Context, rbnk[0]) + reg * 4, v);
b.Branch(end_block);
}
b.SetCurrentBlock(end_block);
Value *addr = b.LoadRegister(i.Rm, VALUE_I32);
b.StoreRegister(i.Rm, b.Add(addr, b.AllocConstant(4)));
Value *v = b.Load(addr, VALUE_I32);
b.StoreContext(offsetof(SH4Context, ralt) + reg * 4, v);
}
// LDS Rm,MACH
@ -1639,29 +1597,9 @@ EMITTER(STCDBR) {
// STC Rm_BANK,Rn
EMITTER(STCRBANK) {
Block *rb1 = b.AppendBlock();
Block *rb0 = b.AppendBlock();
Block *end_block = b.AppendBlock();
int reg = i.Rm & 0x7;
b.BranchCond(b.And(b.LoadSR(), b.AllocConstant(RB)), rb1, rb0);
{
b.SetCurrentBlock(rb1);
b.StoreRegister(i.Rn, b.LoadContext(offsetof(SH4Context, rbnk[0]) + reg * 4,
VALUE_I32));
b.Branch(end_block);
}
{
b.SetCurrentBlock(rb0);
b.StoreRegister(i.Rn, b.LoadContext(offsetof(SH4Context, rbnk[1]) + reg * 4,
VALUE_I32));
b.Branch(end_block);
}
b.SetCurrentBlock(end_block);
b.StoreRegister(
i.Rn, b.LoadContext(offsetof(SH4Context, ralt) + reg * 4, VALUE_I32));
}
// STC.L SR,@-Rn
@ -1722,33 +1660,10 @@ EMITTER(STCMDBR) {
// STC.L Rm_BANK,@-Rn
EMITTER(STCMRBANK) {
Block *rb1 = b.AppendBlock();
Block *rb0 = b.AppendBlock();
Block *end_block = b.AppendBlock();
int reg = i.Rm & 0x7;
b.BranchCond(b.And(b.LoadSR(), b.AllocConstant(RB)), rb1, rb0);
{
b.SetCurrentBlock(rb1);
Value *addr = b.Sub(b.LoadRegister(i.Rn, VALUE_I32), b.AllocConstant(4));
b.StoreRegister(i.Rn, addr);
b.Store(addr,
b.LoadContext(offsetof(SH4Context, rbnk[0]) + reg * 4, VALUE_I32));
b.Branch(end_block);
}
{
b.SetCurrentBlock(rb0);
Value *addr = b.Sub(b.LoadRegister(i.Rn, VALUE_I32), b.AllocConstant(4));
b.StoreRegister(i.Rn, addr);
b.Store(addr,
b.LoadContext(offsetof(SH4Context, rbnk[1]) + reg * 4, VALUE_I32));
b.Branch(end_block);
}
b.SetCurrentBlock(end_block);
Value *addr = b.Sub(b.LoadRegister(i.Rn, VALUE_I32), b.AllocConstant(4));
b.StoreRegister(i.Rn, addr);
b.Store(addr, b.LoadContext(offsetof(SH4Context, ralt) + reg * 4, VALUE_I32));
}
// STS MACH,Rn

2
src/jit/frontend/sh4/sh4_context.h
View File

@ -51,7 +51,7 @@ struct SH4Context {
uint32_t pr;
uint32_t gbr, vbr;
uint32_t mach, macl;
uint32_t r[16], rbnk[2][8], sgr;
uint32_t r[16], ralt[8], sgr;
uint32_t fr[16], xf[16];
uint32_t fpul;
uint32_t dbr;