mirror of https://github.com/inolen/redream.git
separated T and S bits from sh4 status register into their own context members, sr_t and sr_s, reducing codegen by around 15%
This commit is contained in:
Anthony Pesch
parent
d658bb2bfe
commit
b2fd497cda
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@ -63,11 +63,12 @@ void sh4_sr_updated(void *data, uint32_t old_sr) {
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prof_counter_add(COUNTER_sh4_sr_updates, 1);
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if ((ctx->sr & RB) != (old_sr & RB)) {
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if ((ctx->sr & RB_MASK) != (old_sr & RB_MASK)) {
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sh4_swap_gpr_bank(sh4);
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}
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if ((ctx->sr & I) != (old_sr & I) || (ctx->sr & BL) != (old_sr & BL)) {
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if ((ctx->sr & I_MASK) != (old_sr & I_MASK) ||
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(ctx->sr & BL_MASK) != (old_sr & BL_MASK)) {
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sh4_intc_update_pending(sh4);
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}
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}
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@ -205,6 +206,16 @@ static void sh4_translate(void *data, uint32_t addr, struct ir *ir, int fastmem,
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*size = as.size;
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}
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void sh4_implode_sr(struct sh4 *sh4) {
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sh4->ctx.sr &= ~(S_MASK | T_MASK);
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sh4->ctx.sr |= (sh4->ctx.sr_s << S_BIT) | (sh4->ctx.sr_t << T_BIT);
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}
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void sh4_explode_sr(struct sh4 *sh4) {
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sh4->ctx.sr_t = (sh4->ctx.sr & T_MASK) >> T_BIT;
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sh4->ctx.sr_s = (sh4->ctx.sr & S_MASK) >> S_BIT;
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}
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void sh4_clear_interrupt(struct sh4 *sh4, enum sh4_interrupt intr) {
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sh4->requested_interrupts &= ~sh4->sort_id[intr];
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sh4_intc_update_pending(sh4);
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@ -83,6 +83,8 @@ void sh4_destroy(struct sh4 *sh);
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void sh4_reset(struct sh4 *sh4, uint32_t pc);
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void sh4_raise_interrupt(struct sh4 *sh, enum sh4_interrupt intr);
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void sh4_clear_interrupt(struct sh4 *sh, enum sh4_interrupt intr);
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void sh4_explode_sr(struct sh4 *sh4);
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void sh4_implode_sr(struct sh4 *sh4);
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void sh4_sr_updated(void *data, uint32_t old_sr);
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void sh4_fpscr_updated(void *data, uint32_t old_fpscr);
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@ -12,9 +12,9 @@ static struct sh4_interrupt_info sh4_interrupts[NUM_SH_INTERRUPTS] = {
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};
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void sh4_intc_update_pending(struct sh4 *sh4) {
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int min_priority = (sh4->ctx.sr & I) >> 4;
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int min_priority = (sh4->ctx.sr & I_MASK) >> I_BIT;
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uint64_t priority_mask =
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(sh4->ctx.sr & BL) ? 0 : ~sh4->priority_mask[min_priority];
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(sh4->ctx.sr & BL_MASK) ? 0 : ~sh4->priority_mask[min_priority];
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sh4->ctx.pending_interrupts = sh4->requested_interrupts & priority_mask;
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}
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@ -28,11 +28,14 @@ int sh4_intc_check_pending(struct sh4 *sh4) {
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enum sh4_interrupt intr = sh4->sorted_interrupts[n];
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struct sh4_interrupt_info *int_info = &sh4_interrupts[intr];
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/* ensure sr is up to date */
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sh4_implode_sr(sh4);
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*sh4->INTEVT = int_info->intevt;
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sh4->ctx.ssr = sh4->ctx.sr;
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sh4->ctx.spc = sh4->ctx.pc;
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sh4->ctx.sgr = sh4->ctx.r[15];
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sh4->ctx.sr |= (BL | MD | RB);
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sh4->ctx.sr |= (BL_MASK | MD_MASK | RB_MASK);
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sh4->ctx.pc = sh4->ctx.vbr + 0x600;
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sh4_sr_updated(sh4, sh4->ctx.ssr);
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@ -4,29 +4,35 @@
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#include <stdint.h>
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/* SR bits */
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enum {
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/* true / false condition or carry/borrow bit */
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T = 0x00000001,
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/* specifies a saturation operation for a MAC instruction */
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S = 0x00000002,
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/* interrupt mask level */
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I = 0x000000f0,
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/* used by the DIV0S, DIV0U, and DIV1 instructions */
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Q = 0x00000100,
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/* used by the DIV0S, DIV0U, and DIV1 instructions */
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M = 0x00000200,
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/* an FPU instr causes a general FPU disable exception */
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FD = 0x00008000,
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/* interrupt requests are masked */
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BL = 0x10000000,
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/*
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* general register bank specifier in privileged mode (set
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* to 1 by a reset, exception, or interrupt)
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*/
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RB = 0x20000000,
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/* processor mode (0 is user mode, 1 is privileged mode) */
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MD = 0x40000000
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};
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/* true / false condition or carry/borrow bit */
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#define T_BIT 0
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/* specifies a saturation operation for a MAC instruction */
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#define S_BIT 1
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/* interrupt mask level */
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#define I_BIT 4
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/* used by the DIV0S, DIV0U, and DIV1 instructions */
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#define Q_BIT 8
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#define M_BIT 9
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/* an FPU instr causes a general FPU disable exception */
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#define FD_BIT 15
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/* interrupt requests are masked */
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#define BL_BIT 28
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/* general register bank specifier in privileged mode (set
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to 1 by a reset, exception, or interrupt) */
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#define RB_BIT 29
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/* processor mode (0 is user mode, 1 is privileged mode) */
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#define MD_BIT 30
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#define T_MASK (1u << T_BIT)
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#define S_MASK (1u << S_BIT)
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#define I_MASK 0xf0
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#define Q_MASK (1u << Q_BIT)
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#define M_MASK (1u << M_BIT)
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#define FD_MASK (1u << FD_BIT)
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#define BL_MASK (1u << BL_BIT)
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#define RB_MASK (1u << RB_BIT)
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#define MD_MASK (1u << MD_BIT)
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/* FPSCR bits */
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enum {
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@ -38,41 +44,37 @@ enum {
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};
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struct sh4_ctx {
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/*
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* there are 24 32-bit general registers, r0_bank0-r7_bank0, r0_bank1-r7_bank1
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* and r8-r15. r contains the active bank's r0-r7 as well as r8-r15. ralt
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* contains the inactive bank's r0-r7 and is swapped in when the processor
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* mode changes
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*/
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/* there are 24 32-bit general registers, r0_bank0-r7_bank0, r0_bank1-r7_bank1
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and r8-r15. r contains the active bank's r0-r7 as well as r8-r15. ralt
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contains the inactive bank's r0-r7 and is swapped in when the processor
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mode changes */
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uint32_t r[16], ralt[8];
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/*
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* there are 32 32-bit floating point registers, fr0-fr15 and xf0-xf15. these
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* registers are banked, and swapped with eachother when the bank bit of
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* FPSCR changes. in addition, fr0–fr15 can be used as the eight registers
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* dr0/2/4/6/8/10/12/14 (double-precision, or pair registers) or the four
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* registers fv0/4/8/12 (vector registers). while xf0-xf15 can be used as
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* the eight registers xd0/2/4/6/8/10/12/14 (pair registers) or register
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* matrix XMTRX
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*
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* note, the sh4 does not support endian conversion for 64-bit data.
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* therefore, if 64-bit floating point access is performed in little endian
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* mode, the upper and lower 32 bits will be reversed. for example, dr2
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* aliases fr2 and fr3, but fr3 is actually the low-order word
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*
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* in order to avoid swapping the words in every double-precision opcode, the
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* mapping for each pair of single-precision registers is instead swapped by
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* XOR'ing the actual index with 1. for example, fr2 becomes fr[3] and fr3
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* becomes fr[2], enabling dr2 to perfectly alias fr[2]
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/* there are 32 32-bit floating point registers, fr0-fr15 and xf0-xf15. these
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registers are banked, and swapped with eachother when the bank bit of
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FPSCR changes. in addition, fr0–fr15 can be used as the eight registers
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dr0/2/4/6/8/10/12/14 (double-precision, or pair registers) or the four
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registers fv0/4/8/12 (vector registers). while xf0-xf15 can be used as
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the eight registers xd0/2/4/6/8/10/12/14 (pair registers) or register
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matrix XMTRX
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* note note, this incorrectly causes fv registers to be swizzled. fv0 should
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* be loaded as {fr0, fr1, fr2, fr3} but it's actually loaded as
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* {fr1, fr0, fr3, fr2}. however, due to the way the FV registers are
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* used (FIPR and FTRV) this doesn't actually affect the results
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*/
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note, the sh4 does not support endian conversion for 64-bit data.
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therefore, if 64-bit floating point access is performed in little endian
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mode, the upper and lower 32 bits will be reversed. for example, dr2
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aliases fr2 and fr3, but fr3 is actually the low-order word
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in order to avoid swapping the words in every double-precision opcode, the
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mapping for each pair of single-precision registers is instead swapped by
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XOR'ing the actual index with 1. for example, fr2 becomes fr[3] and fr3
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becomes fr[2], enabling dr2 to perfectly alias fr[2]
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note note, this incorrectly causes fv registers to be swizzled. fv0 should
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be loaded as {fr0, fr1, fr2, fr3} but it's actually loaded as
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{fr1, fr0, fr3, fr2}. however, due to the way the FV registers are
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used (FIPR and FTRV) this doesn't actually affect the results */
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uint32_t fr[16], xf[16];
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uint32_t pc, pr, sr, sr_qm, fpscr;
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uint32_t pc, pr, sr, sr_t, sr_s, sr_qm, fpscr;
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uint32_t dbr, gbr, vbr;
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uint32_t fpul, mach, macl;
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uint32_t sgr, spc, ssr;
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@ -53,9 +53,11 @@ static emit_cb emit_callbacks[NUM_SH4_OPS] = {
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#define load_xfr(n, type) ir_load_xfr(ir, n, type)
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#define store_xfr(n, v) ir_store_xfr(ir, n, v)
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#define load_sr() ir_load_sr(ir)
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#define store_sr(v, update) ir_store_sr(frontend, ir, v, update)
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#define store_sr(v) ir_store_sr(frontend, ir, v)
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#define load_t() ir_load_t(ir)
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#define store_t(v) ir_store_t(frontend, ir, v)
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#define load_s() ir_load_s(ir)
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#define store_s(v) ir_store_s(frontend, ir, v)
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#define load_gbr() ir_load_gbr(ir)
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#define store_gbr(v) ir_store_gbr(ir, v)
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#define load_fpscr() ir_load_fpscr(ir)
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@ -120,41 +122,63 @@ static void ir_store_xfr(struct ir *ir, int n, struct ir_value *v) {
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}
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static struct ir_value *ir_load_sr(struct ir *ir) {
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return ir_load_context(ir, offsetof(struct sh4_ctx, sr), VALUE_I32);
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struct ir_value *sr =
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ir_load_context(ir, offsetof(struct sh4_ctx, sr), VALUE_I32);
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/* inlined version of sh4_implode_sr */
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struct ir_value *sr_t =
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ir_load_context(ir, offsetof(struct sh4_ctx, sr_t), VALUE_I32);
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struct ir_value *sr_s =
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ir_load_context(ir, offsetof(struct sh4_ctx, sr_s), VALUE_I32);
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sr = ir_and(ir, sr, ir_alloc_i32(ir, ~(S_MASK | T_MASK)));
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sr = ir_or(ir, sr, sr_t);
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sr = ir_or(ir, sr, ir_shli(ir, sr_s, S_BIT));
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return sr;
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}
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static void ir_store_sr(struct sh4_frontend *frontend, struct ir *ir,
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struct ir_value *v, int update) {
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CHECK_EQ(v->type, VALUE_I32);
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struct ir_value *sr) {
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CHECK_EQ(sr->type, VALUE_I32);
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struct ir_value *sr_updated = NULL;
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struct ir_value *data = NULL;
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struct ir_value *old_sr = NULL;
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struct ir_value *sr_updated = ir_alloc_ptr(ir, frontend->sr_updated);
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struct ir_value *data = ir_alloc_ptr(ir, frontend->data);
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struct ir_value *old_sr = load_sr();
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if (update) {
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sr_updated = ir_alloc_ptr(ir, frontend->sr_updated);
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data = ir_alloc_ptr(ir, frontend->data);
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old_sr = load_sr();
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}
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ir_store_context(ir, offsetof(struct sh4_ctx, sr), sr);
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ir_store_context(ir, offsetof(struct sh4_ctx, sr), v);
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/* inline version of sh4_explode_sr */
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struct ir_value *sr_t = ir_and(ir, sr, ir_alloc_i32(ir, T_MASK));
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struct ir_value *sr_s =
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ir_lshri(ir, ir_and(ir, sr, ir_alloc_i32(ir, S_MASK)), S_BIT);
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ir_store_context(ir, offsetof(struct sh4_ctx, sr_t), sr_t);
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ir_store_context(ir, offsetof(struct sh4_ctx, sr_s), sr_s);
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if (update) {
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ir_call_2(ir, sr_updated, data, old_sr);
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}
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/* TODO inline the check to see if RB, I or BL bits changed */
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ir_call_2(ir, sr_updated, data, old_sr);
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}
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static struct ir_value *ir_load_t(struct ir *ir) {
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return ir_and(ir, load_sr(), ir_alloc_i32(ir, T));
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return ir_load_context(ir, offsetof(struct sh4_ctx, sr_t), VALUE_I32);
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}
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static void ir_store_t(struct sh4_frontend *frontend, struct ir *ir,
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struct ir_value *v) {
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struct ir_value *sr = load_sr();
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struct ir_value *sr_t = ir_or(ir, sr, ir_alloc_i32(ir, T));
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struct ir_value *sr_not = ir_and(ir, sr, ir_alloc_i32(ir, ~T));
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struct ir_value *res = ir_select(ir, v, sr_t, sr_not);
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store_sr(res, 0);
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/* zext the results of ir_cmp_* */
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if (v->type != VALUE_I32) {
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v = ir_zext(ir, v, VALUE_I32);
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}
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ir_store_context(ir, offsetof(struct sh4_ctx, sr_t), v);
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}
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static struct ir_value *ir_load_s(struct ir *ir) {
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return ir_load_context(ir, offsetof(struct sh4_ctx, sr_s), VALUE_I32);
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}
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static void ir_store_s(struct sh4_frontend *frontend, struct ir *ir,
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struct ir_value *v) {
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CHECK_EQ(v->type, VALUE_I32);
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ir_store_context(ir, offsetof(struct sh4_ctx, sr_s), v);
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}
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static struct ir_value *ir_load_gbr(struct ir *ir) {
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@ -609,6 +633,7 @@ EMITTER(ADDC) {
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struct ir_value *not_v = ir_not(ir, v);
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struct ir_value *carry = ir_and(ir, or_rnrm, not_v);
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carry = ir_or(ir, and_rnrm, carry);
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carry = ir_lshri(ir, carry, 31);
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store_t(carry);
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}
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@ -624,7 +649,8 @@ EMITTER(ADDV) {
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/* compute overflow flag, taken from Hacker's Delight */
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struct ir_value *xor_vrn = ir_xor(ir, v, rn);
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struct ir_value *xor_vrm = ir_xor(ir, v, rm);
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struct ir_value *overflow = ir_lshri(ir, ir_and(ir, xor_vrn, xor_vrm), 31);
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struct ir_value *overflow = ir_and(ir, xor_vrn, xor_vrm);
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overflow = ir_lshri(ir, overflow, 31);
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store_t(overflow);
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}
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@ -731,7 +757,8 @@ EMITTER(DIV0S) {
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ir_store_context(ir, offsetof(struct sh4_ctx, sr_qm), ir_not(ir, qm));
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/* msb of Q ^ M -> T */
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store_t(ir_lshri(ir, qm, 31));
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struct ir_value *t = ir_lshri(ir, qm, 31);
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store_t(t);
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}
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// code cycles t-bit
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@ -740,8 +767,7 @@ EMITTER(DIV0S) {
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EMITTER(DIV0U) {
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ir_store_context(ir, offsetof(struct sh4_ctx, sr_qm),
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ir_alloc_i32(ir, 0x80000000));
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store_sr(ir_and(ir, load_sr(), ir_alloc_i32(ir, ~T)), 0);
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store_t(ir_alloc_i32(ir, 0));
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}
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// code cycles t-bit
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@ -780,7 +806,8 @@ EMITTER(DIV1) {
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ir_store_context(ir, offsetof(struct sh4_ctx, sr_qm), qm);
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/* set T to output bit (which happens to be Q == M) */
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store_t(ir_lshri(ir, qm, 31));
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struct ir_value *t = ir_lshri(ir, qm, 31);
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store_t(t);
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}
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// DMULS.L Rm,Rn
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@ -893,6 +920,7 @@ EMITTER(NEGC) {
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struct ir_value *v = ir_sub(ir, ir_neg(ir, rm), t);
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store_gpr(i->Rn, v);
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struct ir_value *carry = ir_or(ir, t, rm);
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carry = ir_lshri(ir, carry, 31);
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store_t(carry);
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}
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@ -916,6 +944,7 @@ EMITTER(SUBC) {
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struct ir_value *l = ir_and(ir, ir_not(ir, rn), rm);
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struct ir_value *r = ir_and(ir, ir_or(ir, ir_not(ir, rn), rm), v);
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struct ir_value *carry = ir_or(ir, l, r);
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carry = ir_lshri(ir, carry, 31);
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store_t(carry);
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}
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@ -929,7 +958,8 @@ EMITTER(SUBV) {
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// compute overflow flag, taken from Hacker's Delight
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struct ir_value *xor_rnrm = ir_xor(ir, rn, rm);
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struct ir_value *xor_vrn = ir_xor(ir, v, rn);
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struct ir_value *overflow = ir_lshri(ir, ir_and(ir, xor_rnrm, xor_vrn), 31);
|
||||
struct ir_value *overflow = ir_and(ir, xor_rnrm, xor_vrn);
|
||||
overflow = ir_lshri(ir, overflow, 31);
|
||||
store_t(overflow);
|
||||
}
|
||||
|
||||
|
|
@ -1319,9 +1349,7 @@ EMITTER(CLRMAC) {
|
|||
}
|
||||
|
||||
EMITTER(CLRS) {
|
||||
struct ir_value *sr = load_sr();
|
||||
sr = ir_and(ir, sr, ir_alloc_i32(ir, ~S));
|
||||
store_sr(sr, 1);
|
||||
store_s(ir_alloc_i32(ir, 0));
|
||||
}
|
||||
|
||||
// code cycles t-bit
|
||||
|
|
@ -1334,7 +1362,7 @@ EMITTER(CLRT) {
|
|||
// LDC Rm,SR
|
||||
EMITTER(LDCSR) {
|
||||
struct ir_value *rm = load_gpr(i->Rm, VALUE_I32);
|
||||
store_sr(rm, 1);
|
||||
store_sr(rm);
|
||||
}
|
||||
|
||||
// LDC Rm,GBR
|
||||
|
|
@ -1378,7 +1406,7 @@ EMITTER(LDCRBANK) {
|
|||
EMITTER(LDCMSR) {
|
||||
struct ir_value *addr = load_gpr(i->Rm, VALUE_I32);
|
||||
struct ir_value *v = load_guest(addr, VALUE_I32);
|
||||
store_sr(v, 1);
|
||||
store_sr(v);
|
||||
/* reload Rm, sr store could have swapped banks */
|
||||
addr = load_gpr(i->Rm, VALUE_I32);
|
||||
addr = ir_add(ir, addr, ir_alloc_i32(ir, 4));
|
||||
|
|
@ -1524,15 +1552,14 @@ EMITTER(RTE) {
|
|||
ir_load_context(ir, offsetof(struct sh4_ctx, spc), VALUE_I32);
|
||||
struct ir_value *ssr =
|
||||
ir_load_context(ir, offsetof(struct sh4_ctx, ssr), VALUE_I32);
|
||||
store_sr(ssr, 1);
|
||||
store_sr(ssr);
|
||||
emit_delay_instr();
|
||||
branch(spc);
|
||||
}
|
||||
|
||||
// SETS
|
||||
EMITTER(SETS) {
|
||||
struct ir_value *sr = ir_or(ir, load_sr(), ir_alloc_i32(ir, S));
|
||||
store_sr(sr, 1);
|
||||
store_s(ir_alloc_i32(ir, 1));
|
||||
}
|
||||
|
||||
// SETT
|
||||
|
|
|
|||
|
|
@ -107,6 +107,9 @@ static void run_sh4_test(struct dreamcast *dc, const struct sh4_test *test) {
|
|||
dc_tick(dc, 1);
|
||||
}
|
||||
|
||||
/* ensure sh4 sr is up to date before testing against it */
|
||||
sh4_implode_sr(dc->sh4);
|
||||
|
||||
/* validate out registers */
|
||||
for (int i = 0; i < sh4_num_test_regs; i++) {
|
||||
struct sh4_test_reg *reg = &sh4_test_regs[i];
|
||||
|
|
@ -138,7 +141,7 @@ TEST(sh4_x64) {
|
|||
{0}, \
|
||||
{fr1, fr0, fr3, fr2, fr5, fr4, fr7, fr6, fr9, fr8, fr11, fr10, fr13, fr12, fr15, fr14}, \
|
||||
{xf1, xf0, xf3, xf2, xf5, xf4, xf7, xf6, xf9, xf8, xf11, xf10, xf13, xf12, xf15, xf14}, \
|
||||
0, 0, 0, 0, fpscr, \
|
||||
0, 0, 0, 0, 0, 0, fpscr, \
|
||||
0, 0, 0, \
|
||||
0, 0, 0, \
|
||||
0, 0, 0, \
|
||||
|
|
|
|||
Loading…
Reference in New Issue