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quickerNES
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Abandoning support for quicknes savestates due to its unability to establish the correct state size from the beginning with games like Castlevania 3. Removing headers also

This commit is contained in:
SergioMartin86 2024-02-24 18:35:47 +00:00
parent c07130414f
commit 3b041974d8
30 changed files with 28 additions and 103 deletions
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2
source/player.cpp
View File

@ -166,7 +166,7 @@ int main(int argc, char *argv[])
showFrameInfo = true; showFrameInfo = true;
// Get command // Get command
auto command = jaffarCommon::getKeyPress(); auto command = jaffarCommon::waitForKeyPress();
// Advance/Rewind commands // Advance/Rewind commands
if (command == 'n') currentStep = currentStep - 1; if (command == 'n') currentStep = currentStep - 1;

2
source/quickNES/core

@ -1 +1 @@
Subproject commit 54eb1b308ed33f252861a6b95c428946ff5a664e Subproject commit e35054dc19c94fcac9b8cfd2fbf5b33f8e1dfbde

75
source/quickerNES/core/core.hpp
View File

@ -96,7 +96,6 @@ class Core : private Cpu
bool NTABBlockEnabled = true; bool NTABBlockEnabled = true;
bool CHRRBlockEnabled = true; bool CHRRBlockEnabled = true;
bool SRAMBlockEnabled = true; bool SRAMBlockEnabled = true;
bool HEADBlockEnabled = true;
Core() : ppu(this) Core() : ppu(this)
{ {
@ -154,28 +153,8 @@ class Core : private Cpu
reset(true, true); reset(true, true);
} }
static inline void serializeBlockHead(
const char* blockTag,
const uint32_t blockSize,
jaffarCommon::serializer::Base& serializer)
{
serializer.pushContiguous(blockTag, 4);
serializer.pushContiguous(&blockSize, 4);
}
static inline void deserializeBlockHead(jaffarCommon::deserializer::Base& deserializer)
{
uint32_t nullValue = 0;
deserializer.popContiguous(&nullValue, 4);
deserializer.popContiguous(&nullValue, 4);
}
inline void serializeState(jaffarCommon::serializer::Base& serializer) const inline void serializeState(jaffarCommon::serializer::Base& serializer) const
{ {
// NESS Block
if (HEADBlockEnabled == true) serializeBlockHead("NESS", 0xFFFFFFFF, serializer);
// TIME Block // TIME Block
if (TIMEBlockEnabled == true) if (TIMEBlockEnabled == true)
{ {
@ -184,8 +163,6 @@ class Core : private Cpu
const auto inputDataSize = sizeof(nes_state_t); const auto inputDataSize = sizeof(nes_state_t);
const auto inputData = (uint8_t *)&state; const auto inputData = (uint8_t *)&state;
if (HEADBlockEnabled == true) serializeBlockHead("TIME", inputDataSize, serializer);
serializer.pushContiguous(inputData, inputDataSize); serializer.pushContiguous(inputData, inputDataSize);
} }
@ -204,7 +181,6 @@ class Core : private Cpu
const auto inputDataSize = sizeof(cpu_state_t); const auto inputDataSize = sizeof(cpu_state_t);
const auto inputData = (uint8_t *)&s; const auto inputData = (uint8_t *)&s;
if (HEADBlockEnabled == true) serializeBlockHead("CPUR", inputDataSize, serializer);
serializer.pushContiguous(inputData, inputDataSize); serializer.pushContiguous(inputData, inputDataSize);
} }
@ -212,8 +188,6 @@ class Core : private Cpu
{ {
const auto inputDataSize = sizeof(ppu_state_t); const auto inputDataSize = sizeof(ppu_state_t);
const auto inputData = (const uint8_t *)&ppu; const auto inputData = (const uint8_t *)&ppu;
if (HEADBlockEnabled == true) serializeBlockHead("PPUR", inputDataSize, serializer);
serializer.pushContiguous(inputData, inputDataSize); serializer.pushContiguous(inputData, inputDataSize);
} }
@ -225,8 +199,6 @@ class Core : private Cpu
const auto inputDataSize = sizeof(Apu::apu_state_t); const auto inputDataSize = sizeof(Apu::apu_state_t);
const auto inputData = (uint8_t *)&apuState; const auto inputData = (uint8_t *)&apuState;
if (HEADBlockEnabled == true) serializeBlockHead("APUR", inputDataSize, serializer);
serializer.pushContiguous(inputData, inputDataSize); serializer.pushContiguous(inputData, inputDataSize);
} }
@ -235,8 +207,6 @@ class Core : private Cpu
{ {
const auto inputDataSize = sizeof(joypad_state_t); const auto inputDataSize = sizeof(joypad_state_t);
const auto inputData = (uint8_t *)&joypad; const auto inputData = (uint8_t *)&joypad;
if (HEADBlockEnabled == true) serializeBlockHead("CTRL", inputDataSize, serializer);
serializer.pushContiguous(inputData, inputDataSize); serializer.pushContiguous(inputData, inputDataSize);
} }
@ -245,8 +215,6 @@ class Core : private Cpu
{ {
const auto inputDataSize = mapper->state_size; const auto inputDataSize = mapper->state_size;
const auto inputData = (uint8_t *)mapper->state; const auto inputData = (uint8_t *)mapper->state;
if (HEADBlockEnabled == true) serializeBlockHead("MAPR", inputDataSize, serializer);
serializer.pushContiguous(inputData, inputDataSize); serializer.pushContiguous(inputData, inputDataSize);
} }
@ -255,8 +223,6 @@ class Core : private Cpu
{ {
const auto inputDataSize = low_ram_size; const auto inputDataSize = low_ram_size;
const auto inputData = (uint8_t *)low_mem; const auto inputData = (uint8_t *)low_mem;
if (HEADBlockEnabled == true) serializeBlockHead("LRAM", inputDataSize, serializer);
serializer.push(inputData, inputDataSize); serializer.push(inputData, inputDataSize);
} }
@ -265,8 +231,6 @@ class Core : private Cpu
{ {
const auto inputDataSize = Ppu::spr_ram_size; const auto inputDataSize = Ppu::spr_ram_size;
const auto inputData = (uint8_t *)ppu.spr_ram; const auto inputData = (uint8_t *)ppu.spr_ram;
if (HEADBlockEnabled == true) serializeBlockHead("SPRT", inputDataSize, serializer);
serializer.push(inputData, inputDataSize); serializer.push(inputData, inputDataSize);
} }
@ -277,8 +241,6 @@ class Core : private Cpu
const auto inputDataSize = nametable_size; const auto inputDataSize = nametable_size;
const auto inputData = (uint8_t *)ppu.impl->nt_ram; const auto inputData = (uint8_t *)ppu.impl->nt_ram;
if (HEADBlockEnabled == true) serializeBlockHead("NTAB", inputDataSize, serializer);
serializer.push(inputData, inputDataSize); serializer.push(inputData, inputDataSize);
} }
@ -289,8 +251,6 @@ class Core : private Cpu
{ {
const auto inputDataSize = ppu.chr_size; const auto inputDataSize = ppu.chr_size;
const auto inputData = (uint8_t *)ppu.impl->chr_ram; const auto inputData = (uint8_t *)ppu.impl->chr_ram;
if (HEADBlockEnabled == true) serializeBlockHead("CHRR", inputDataSize, serializer);
serializer.push(inputData, inputDataSize); serializer.push(inputData, inputDataSize);
} }
} }
@ -302,14 +262,9 @@ class Core : private Cpu
{ {
const auto inputDataSize = impl->sram_size; const auto inputDataSize = impl->sram_size;
const auto inputData = (uint8_t *)impl->sram; const auto inputData = (uint8_t *)impl->sram;
if (HEADBlockEnabled == true) serializeBlockHead("SRAM", inputDataSize, serializer);
serializer.push(inputData, inputDataSize); serializer.push(inputData, inputDataSize);
} }
} }
// gend Block
if (HEADBlockEnabled == true) serializeBlockHead("gend", 0, serializer);
} }
inline void deserializeState(jaffarCommon::deserializer::Base& deserializer) inline void deserializeState(jaffarCommon::deserializer::Base& deserializer)
@ -318,9 +273,6 @@ class Core : private Cpu
error_count = 0; error_count = 0;
ppu.burst_phase = 0; // avoids shimmer when seeking to same time over and over ppu.burst_phase = 0; // avoids shimmer when seeking to same time over and over
// NESS Block
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
// TIME Block // TIME Block
if (TIMEBlockEnabled == true) if (TIMEBlockEnabled == true)
{ {
@ -328,8 +280,6 @@ class Core : private Cpu
const auto outputData = (uint8_t*) &nesState; const auto outputData = (uint8_t*) &nesState;
const auto inputDataSize = sizeof(nes_state_t); const auto inputDataSize = sizeof(nes_state_t);
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.popContiguous(outputData, inputDataSize); deserializer.popContiguous(outputData, inputDataSize);
nes = nesState; nes = nesState;
@ -343,8 +293,6 @@ class Core : private Cpu
const auto outputData = (uint8_t*) &s; const auto outputData = (uint8_t*) &s;
const auto inputDataSize = sizeof(cpu_state_t); const auto inputDataSize = sizeof(cpu_state_t);
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.popContiguous(outputData, inputDataSize); deserializer.popContiguous(outputData, inputDataSize);
r.pc = s.pc; r.pc = s.pc;
@ -360,8 +308,6 @@ class Core : private Cpu
{ {
const auto outputData = (uint8_t*) &ppu; const auto outputData = (uint8_t*) &ppu;
const auto inputDataSize = sizeof(ppu_state_t); const auto inputDataSize = sizeof(ppu_state_t);
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.popContiguous(outputData, inputDataSize); deserializer.popContiguous(outputData, inputDataSize);
} }
@ -372,8 +318,6 @@ class Core : private Cpu
const auto outputData = (uint8_t*) &apuState; const auto outputData = (uint8_t*) &apuState;
const auto inputDataSize = sizeof(Apu::apu_state_t); const auto inputDataSize = sizeof(Apu::apu_state_t);
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.popContiguous(outputData, inputDataSize); deserializer.popContiguous(outputData, inputDataSize);
impl->apu.load_state(apuState); impl->apu.load_state(apuState);
@ -385,8 +329,6 @@ class Core : private Cpu
{ {
const auto outputData = (uint8_t*) &joypad; const auto outputData = (uint8_t*) &joypad;
const auto inputDataSize = sizeof(joypad_state_t); const auto inputDataSize = sizeof(joypad_state_t);
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.popContiguous(outputData, inputDataSize); deserializer.popContiguous(outputData, inputDataSize);
} }
@ -397,8 +339,6 @@ class Core : private Cpu
const auto outputData = (uint8_t*) mapper->state; const auto outputData = (uint8_t*) mapper->state;
const auto inputDataSize = mapper->state_size; const auto inputDataSize = mapper->state_size;
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.popContiguous(outputData, inputDataSize); deserializer.popContiguous(outputData, inputDataSize);
mapper->apply_mapping(); mapper->apply_mapping();
@ -409,8 +349,6 @@ class Core : private Cpu
{ {
const auto outputData = (uint8_t*) low_mem; const auto outputData = (uint8_t*) low_mem;
const auto inputDataSize = low_ram_size; const auto inputDataSize = low_ram_size;
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.pop(outputData, inputDataSize); deserializer.pop(outputData, inputDataSize);
} }
@ -419,8 +357,6 @@ class Core : private Cpu
{ {
const auto outputData = (uint8_t*) ppu.spr_ram; const auto outputData = (uint8_t*) ppu.spr_ram;
const auto inputDataSize = Ppu::spr_ram_size; const auto inputDataSize = Ppu::spr_ram_size;
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.pop(outputData, inputDataSize); deserializer.pop(outputData, inputDataSize);
} }
@ -431,8 +367,6 @@ class Core : private Cpu
const auto outputData = (uint8_t*) ppu.impl->nt_ram; const auto outputData = (uint8_t*) ppu.impl->nt_ram;
const auto inputDataSize = nametable_size; const auto inputDataSize = nametable_size;
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.pop(outputData, inputDataSize); deserializer.pop(outputData, inputDataSize);
} }
@ -443,8 +377,6 @@ class Core : private Cpu
{ {
const auto outputData = (uint8_t*) ppu.impl->chr_ram; const auto outputData = (uint8_t*) ppu.impl->chr_ram;
const auto inputDataSize = ppu.chr_size; const auto inputDataSize = ppu.chr_size;
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.pop(outputData, inputDataSize); deserializer.pop(outputData, inputDataSize);
ppu.all_tiles_modified(); ppu.all_tiles_modified();
@ -458,16 +390,11 @@ class Core : private Cpu
{ {
const auto outputData = (uint8_t*) impl->sram; const auto outputData = (uint8_t*) impl->sram;
const auto inputDataSize = impl->sram_size; const auto inputDataSize = impl->sram_size;
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
deserializer.pop(outputData, inputDataSize); deserializer.pop(outputData, inputDataSize);
} }
} }
if (sram_present) enable_sram(true); if (sram_present) enable_sram(true);
// gend Block
if (HEADBlockEnabled == true) deserializeBlockHead(deserializer);
} }
void enableStateBlock(const std::string& block) void enableStateBlock(const std::string& block)
@ -485,7 +412,6 @@ void enableStateBlock(const std::string& block)
if (block == "NTAB") { NTABBlockEnabled = true; recognizedBlock = true; } if (block == "NTAB") { NTABBlockEnabled = true; recognizedBlock = true; }
if (block == "CHRR") { CHRRBlockEnabled = true; recognizedBlock = true; } if (block == "CHRR") { CHRRBlockEnabled = true; recognizedBlock = true; }
if (block == "SRAM") { SRAMBlockEnabled = true; recognizedBlock = true; } if (block == "SRAM") { SRAMBlockEnabled = true; recognizedBlock = true; }
if (block == "HEAD") { HEADBlockEnabled = true; recognizedBlock = true; }
if (recognizedBlock == false) { fprintf(stderr, "Unrecognized block type: %s\n", block.c_str()); exit(-1);} if (recognizedBlock == false) { fprintf(stderr, "Unrecognized block type: %s\n", block.c_str()); exit(-1);}
}; };
@ -506,7 +432,6 @@ void disableStateBlock(const std::string& block)
if (block == "NTAB") { NTABBlockEnabled = false; recognizedBlock = true; } if (block == "NTAB") { NTABBlockEnabled = false; recognizedBlock = true; }
if (block == "CHRR") { CHRRBlockEnabled = false; recognizedBlock = true; } if (block == "CHRR") { CHRRBlockEnabled = false; recognizedBlock = true; }
if (block == "SRAM") { SRAMBlockEnabled = false; recognizedBlock = true; } if (block == "SRAM") { SRAMBlockEnabled = false; recognizedBlock = true; }
if (block == "HEAD") { HEADBlockEnabled = false; recognizedBlock = true; }
if (recognizedBlock == false) { fprintf(stderr, "Unrecognized block type: %s\n", block.c_str()); exit(-1);} if (recognizedBlock == false) { fprintf(stderr, "Unrecognized block type: %s\n", block.c_str()); exit(-1);}
}; };

2
tests/arkanoid.warpless.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "B2B30C4F30DD853C215C17B0C67CFE63D61A3062", "Expected ROM SHA1": "B2B30C4F30DD853C215C17B0C67CFE63D61A3062",
"Initial State File": "", "Initial State File": "",
"Sequence File": "arkanoid.warpless.sol", "Sequence File": "arkanoid.warpless.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "MAPR", "CTRL", "APUR" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "MAPR", "CTRL", "APUR" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/arkanoid.warps.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "B2B30C4F30DD853C215C17B0C67CFE63D61A3062", "Expected ROM SHA1": "B2B30C4F30DD853C215C17B0C67CFE63D61A3062",
"Initial State File": "", "Initial State File": "",
"Sequence File": "arkanoid.warps.sol", "Sequence File": "arkanoid.warps.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "MAPR", "CTRL", "APUR" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "MAPR", "CTRL", "APUR" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/castlevania1.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "A31B8BD5B370A9103343C866F3C2B2998E889341", "Expected ROM SHA1": "A31B8BD5B370A9103343C866F3C2B2998E889341",
"Initial State File": "", "Initial State File": "",
"Sequence File": "castlevania1.anyPercent.sol", "Sequence File": "castlevania1.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/castlevania1.pacifist.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "A31B8BD5B370A9103343C866F3C2B2998E889341", "Expected ROM SHA1": "A31B8BD5B370A9103343C866F3C2B2998E889341",
"Initial State File": "", "Initial State File": "",
"Sequence File": "castlevania1.pacifist.sol", "Sequence File": "castlevania1.pacifist.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/galaga.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "DA54C223D79FA59EB95437854B677CF69B5CAC8A", "Expected ROM SHA1": "DA54C223D79FA59EB95437854B677CF69B5CAC8A",
"Initial State File": "", "Initial State File": "",
"Sequence File": "galaga.anyPercent.sol", "Sequence File": "galaga.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/ironSword.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "97B79E432F62403FB9F877090850C41112A9A168", "Expected ROM SHA1": "97B79E432F62403FB9F877090850C41112A9A168",
"Initial State File": "", "Initial State File": "",
"Sequence File": "ironSword.anyPercent.sol", "Sequence File": "ironSword.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/metroid.playaround.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "ECF39EC5A33E6A6F832F03E8FFC61C5D53F4F90B", "Expected ROM SHA1": "ECF39EC5A33E6A6F832F03E8FFC61C5D53F4F90B",
"Initial State File": "", "Initial State File": "",
"Sequence File": "metroid.playaround.sol", "Sequence File": "metroid.playaround.sol",
"Disable State Blocks": [ "HEAD", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/microMachines.race20.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "EC7BB4D11AFA5A955010BB9A548C1460EAC08FE0", "Expected ROM SHA1": "EC7BB4D11AFA5A955010BB9A548C1460EAC08FE0",
"Initial State File": "microMachines.race20.state", "Initial State File": "microMachines.race20.state",
"Sequence File": "microMachines.race20.sol", "Sequence File": "microMachines.race20.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/nigelMansell.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "BBE5CF2DFA0B5422776A530D6F1B617238A8569F", "Expected ROM SHA1": "BBE5CF2DFA0B5422776A530D6F1B617238A8569F",
"Initial State File": "", "Initial State File": "",
"Sequence File": "nigelMansell.anyPercent.sol", "Sequence File": "nigelMansell.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/ninjaGaiden.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "CA513F841D75EFEB33BB8099FB02BEEB39F6BB9C", "Expected ROM SHA1": "CA513F841D75EFEB33BB8099FB02BEEB39F6BB9C",
"Initial State File": "", "Initial State File": "",
"Sequence File": "ninjaGaiden.anyPercent.sol", "Sequence File": "ninjaGaiden.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/ninjaGaiden.pacifist.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "CA513F841D75EFEB33BB8099FB02BEEB39F6BB9C", "Expected ROM SHA1": "CA513F841D75EFEB33BB8099FB02BEEB39F6BB9C",
"Initial State File": "", "Initial State File": "",
"Sequence File": "ninjaGaiden.pacifist.sol", "Sequence File": "ninjaGaiden.pacifist.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/ninjaGaiden2.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "B1796660E4A4CEFC72181D4BF4F97999BC048A77", "Expected ROM SHA1": "B1796660E4A4CEFC72181D4BF4F97999BC048A77",
"Initial State File": "", "Initial State File": "",
"Sequence File": "ninjaGaiden2.anyPercent.sol", "Sequence File": "ninjaGaiden2.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/ninjaGaiden2.pacifist.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "B1796660E4A4CEFC72181D4BF4F97999BC048A77", "Expected ROM SHA1": "B1796660E4A4CEFC72181D4BF4F97999BC048A77",
"Initial State File": "", "Initial State File": "",
"Sequence File": "ninjaGaiden2.pacifist.sol", "Sequence File": "ninjaGaiden2.pacifist.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/novaTheSquirrel.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "B6B07EE76492ED475F39167C89B342353F999231", "Expected ROM SHA1": "B6B07EE76492ED475F39167C89B342353F999231",
"Initial State File": "", "Initial State File": "",
"Sequence File": "novaTheSquirrel.anyPercent.sol", "Sequence File": "novaTheSquirrel.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/princeOfPersia.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "6B58F149F34FA829135619C58700CAAA95B9CDE3", "Expected ROM SHA1": "6B58F149F34FA829135619C58700CAAA95B9CDE3",
"Initial State File": "", "Initial State File": "",
"Sequence File": "princeOfPersia.anyPercent.sol", "Sequence File": "princeOfPersia.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/rcProAmII.race1.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "8C68582BDAA32FBC8C7CD858991D4E00D3B1569C", "Expected ROM SHA1": "8C68582BDAA32FBC8C7CD858991D4E00D3B1569C",
"Initial State File": "", "Initial State File": "",
"Sequence File": "rcProAmII.race1.sol", "Sequence File": "rcProAmII.race1.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "NTAB", "SPRT", "CTRL", "APUR" ], "Disable State Blocks": [ "SRAM", "NTAB", "SPRT", "CTRL", "APUR" ],
"Controller 1 Type": "FourScore1", "Controller 1 Type": "FourScore1",
"Controller 2 Type": "FourScore2", "Controller 2 Type": "FourScore2",
"Differential Compression": "Differential Compression":

2
tests/saintSeiyaKanketsuHen.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "F871D9B3DAFDDCDAD5F2ACD71044292E5169064E", "Expected ROM SHA1": "F871D9B3DAFDDCDAD5F2ACD71044292E5169064E",
"Initial State File": "", "Initial State File": "",
"Sequence File": "saintSeiyaKanketsuHen.anyPercent.sol", "Sequence File": "saintSeiyaKanketsuHen.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/saintSeiyaOugonDensetsu.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "3F3B499CF50386084E053BCA096AE8E52330CFAE", "Expected ROM SHA1": "3F3B499CF50386084E053BCA096AE8E52330CFAE",
"Initial State File": "", "Initial State File": "",
"Sequence File": "saintSeiyaKanketsuHen.anyPercent.sol", "Sequence File": "saintSeiyaKanketsuHen.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/saiyuukiWorld.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "C2F12D915A4D0B1FFDF8A64AE1092CE6A2D08770", "Expected ROM SHA1": "C2F12D915A4D0B1FFDF8A64AE1092CE6A2D08770",
"Initial State File": "", "Initial State File": "",
"Sequence File": "saiyuukiWorld.anyPercent.sol", "Sequence File": "saiyuukiWorld.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

BIN
tests/saiyuukiWorld.lastHalf.state
View File

Binary file not shown.

2
tests/solarJetman.anyPercent.test
View File

@ -5,7 +5,7 @@
"Expected ROM SHA1": "872B91A2F7A2F635061EF43F79E7F7E9F59F5C50", "Expected ROM SHA1": "872B91A2F7A2F635061EF43F79E7F7E9F59F5C50",
"Initial State File": "", "Initial State File": "",
"Sequence File": "solarJetman.anyPercent.sol", "Sequence File": "solarJetman.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/sprilo.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "6EC09B9B51320A536A786D3D4719432B714C5779", "Expected ROM SHA1": "6EC09B9B51320A536A786D3D4719432B714C5779",
"Initial State File": "", "Initial State File": "",
"Sequence File": "sprilo.anyPercent.sol", "Sequence File": "sprilo.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/superMarioBros.warpless.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "EA343F4E445A9050D4B4FBAC2C77D0693B1D0922", "Expected ROM SHA1": "EA343F4E445A9050D4B4FBAC2C77D0693B1D0922",
"Initial State File": "", "Initial State File": "",
"Sequence File": "superMarioBros.warpless.sol", "Sequence File": "superMarioBros.warpless.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/superMarioBros.warps.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "EA343F4E445A9050D4B4FBAC2C77D0693B1D0922", "Expected ROM SHA1": "EA343F4E445A9050D4B4FBAC2C77D0693B1D0922",
"Initial State File": "", "Initial State File": "",
"Sequence File": "superMarioBros.warps.sol", "Sequence File": "superMarioBros.warps.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/superMarioBros3.warps.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "A03E7E526E79DF222E048AE22214BCA2BC49C449", "Expected ROM SHA1": "A03E7E526E79DF222E048AE22214BCA2BC49C449",
"Initial State File": "", "Initial State File": "",
"Sequence File": "superMarioBros3.warps.sol", "Sequence File": "superMarioBros3.warps.sol",
"Disable State Blocks": [ "HEAD", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/superOffroad.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "57919B685B55EE3ED3AD98FB1D25626B98BE7D39", "Expected ROM SHA1": "57919B685B55EE3ED3AD98FB1D25626B98BE7D39",
"Initial State File": "", "Initial State File": "",
"Sequence File": "superOffroad.anyPercent.sol", "Sequence File": "superOffroad.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":

2
tests/tennis.anyPercent.test
View File

@ -3,7 +3,7 @@
"Expected ROM SHA1": "80D99C035E6A5AB9718E413EC25CBE094F085962", "Expected ROM SHA1": "80D99C035E6A5AB9718E413EC25CBE094F085962",
"Initial State File": "", "Initial State File": "",
"Sequence File": "tennis.anyPercent.sol", "Sequence File": "tennis.anyPercent.sol",
"Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ],
"Controller 1 Type": "Joypad", "Controller 1 Type": "Joypad",
"Controller 2 Type": "None", "Controller 2 Type": "None",
"Differential Compression": "Differential Compression":