From 3b041974d8cca1031c947627645303e399b4ca63 Mon Sep 17 00:00:00 2001 From: SergioMartin86 Date: Sat, 24 Feb 2024 18:35:47 +0000 Subject: [PATCH] Abandoning support for quicknes savestates due to its unability to establish the correct state size from the beginning with games like Castlevania 3. Removing headers also --- source/player.cpp | 2 +- source/quickNES/core | 2 +- source/quickerNES/core/core.hpp | 75 ------------------ tests/arkanoid.warpless.test | 2 +- tests/arkanoid.warps.test | 2 +- tests/castlevania1.anyPercent.test | 2 +- tests/castlevania1.pacifist.test | 2 +- tests/galaga.anyPercent.test | 2 +- tests/ironSword.anyPercent.test | 2 +- tests/metroid.playaround.test | 2 +- tests/microMachines.race20.test | 2 +- tests/nigelMansell.anyPercent.test | 2 +- tests/ninjaGaiden.anyPercent.test | 2 +- tests/ninjaGaiden.pacifist.test | 2 +- tests/ninjaGaiden2.anyPercent.test | 2 +- tests/ninjaGaiden2.pacifist.test | 2 +- tests/novaTheSquirrel.anyPercent.test | 2 +- tests/princeOfPersia.anyPercent.test | 2 +- tests/rcProAmII.race1.test | 2 +- tests/saintSeiyaKanketsuHen.anyPercent.test | 2 +- tests/saintSeiyaOugonDensetsu.anyPercent.test | 2 +- tests/saiyuukiWorld.anyPercent.test | 2 +- tests/saiyuukiWorld.lastHalf.state | Bin 23041 -> 22937 bytes tests/solarJetman.anyPercent.test | 2 +- tests/sprilo.anyPercent.test | 2 +- tests/superMarioBros.warpless.test | 2 +- tests/superMarioBros.warps.test | 2 +- tests/superMarioBros3.warps.test | 2 +- tests/superOffroad.anyPercent.test | 2 +- tests/tennis.anyPercent.test | 2 +- 30 files changed, 28 insertions(+), 103 deletions(-) diff --git a/source/player.cpp b/source/player.cpp index 6f714df..e1c5828 100644 --- a/source/player.cpp +++ b/source/player.cpp @@ -166,7 +166,7 @@ int main(int argc, char *argv[]) showFrameInfo = true; // Get command - auto command = jaffarCommon::getKeyPress(); + auto command = jaffarCommon::waitForKeyPress(); // Advance/Rewind commands if (command == 'n') currentStep = currentStep - 1; diff --git a/source/quickNES/core b/source/quickNES/core index 54eb1b3..e35054d 160000 --- a/source/quickNES/core +++ b/source/quickNES/core @@ -1 +1 @@ -Subproject commit 54eb1b308ed33f252861a6b95c428946ff5a664e +Subproject commit e35054dc19c94fcac9b8cfd2fbf5b33f8e1dfbde diff --git a/source/quickerNES/core/core.hpp b/source/quickerNES/core/core.hpp index d9b8567..b9b695f 100644 --- a/source/quickerNES/core/core.hpp +++ b/source/quickerNES/core/core.hpp @@ -96,7 +96,6 @@ class Core : private Cpu bool NTABBlockEnabled = true; bool CHRRBlockEnabled = true; bool SRAMBlockEnabled = true; - bool HEADBlockEnabled = true; Core() : ppu(this) { @@ -154,28 +153,8 @@ class Core : private Cpu reset(true, true); } - static inline void serializeBlockHead( - const char* blockTag, - const uint32_t blockSize, - jaffarCommon::serializer::Base& serializer) - { - serializer.pushContiguous(blockTag, 4); - serializer.pushContiguous(&blockSize, 4); - } - - static inline void deserializeBlockHead(jaffarCommon::deserializer::Base& deserializer) - { - uint32_t nullValue = 0; - deserializer.popContiguous(&nullValue, 4); - deserializer.popContiguous(&nullValue, 4); - } - - inline void serializeState(jaffarCommon::serializer::Base& serializer) const { - // NESS Block - if (HEADBlockEnabled == true) serializeBlockHead("NESS", 0xFFFFFFFF, serializer); - // TIME Block if (TIMEBlockEnabled == true) { @@ -184,8 +163,6 @@ class Core : private Cpu const auto inputDataSize = sizeof(nes_state_t); const auto inputData = (uint8_t *)&state; - - if (HEADBlockEnabled == true) serializeBlockHead("TIME", inputDataSize, serializer); serializer.pushContiguous(inputData, inputDataSize); } @@ -204,7 +181,6 @@ class Core : private Cpu const auto inputDataSize = sizeof(cpu_state_t); const auto inputData = (uint8_t *)&s; - if (HEADBlockEnabled == true) serializeBlockHead("CPUR", inputDataSize, serializer); serializer.pushContiguous(inputData, inputDataSize); } @@ -212,8 +188,6 @@ class Core : private Cpu { const auto inputDataSize = sizeof(ppu_state_t); const auto inputData = (const uint8_t *)&ppu; - - if (HEADBlockEnabled == true) serializeBlockHead("PPUR", inputDataSize, serializer); serializer.pushContiguous(inputData, inputDataSize); } @@ -225,8 +199,6 @@ class Core : private Cpu const auto inputDataSize = sizeof(Apu::apu_state_t); const auto inputData = (uint8_t *)&apuState; - - if (HEADBlockEnabled == true) serializeBlockHead("APUR", inputDataSize, serializer); serializer.pushContiguous(inputData, inputDataSize); } @@ -235,8 +207,6 @@ class Core : private Cpu { const auto inputDataSize = sizeof(joypad_state_t); const auto inputData = (uint8_t *)&joypad; - - if (HEADBlockEnabled == true) serializeBlockHead("CTRL", inputDataSize, serializer); serializer.pushContiguous(inputData, inputDataSize); } @@ -245,8 +215,6 @@ class Core : private Cpu { const auto inputDataSize = mapper->state_size; const auto inputData = (uint8_t *)mapper->state; - - if (HEADBlockEnabled == true) serializeBlockHead("MAPR", inputDataSize, serializer); serializer.pushContiguous(inputData, inputDataSize); } @@ -255,8 +223,6 @@ class Core : private Cpu { const auto inputDataSize = low_ram_size; const auto inputData = (uint8_t *)low_mem; - - if (HEADBlockEnabled == true) serializeBlockHead("LRAM", inputDataSize, serializer); serializer.push(inputData, inputDataSize); } @@ -265,8 +231,6 @@ class Core : private Cpu { const auto inputDataSize = Ppu::spr_ram_size; const auto inputData = (uint8_t *)ppu.spr_ram; - - if (HEADBlockEnabled == true) serializeBlockHead("SPRT", inputDataSize, serializer); serializer.push(inputData, inputDataSize); } @@ -277,8 +241,6 @@ class Core : private Cpu const auto inputDataSize = nametable_size; const auto inputData = (uint8_t *)ppu.impl->nt_ram; - - if (HEADBlockEnabled == true) serializeBlockHead("NTAB", inputDataSize, serializer); serializer.push(inputData, inputDataSize); } @@ -289,8 +251,6 @@ class Core : private Cpu { const auto inputDataSize = ppu.chr_size; const auto inputData = (uint8_t *)ppu.impl->chr_ram; - - if (HEADBlockEnabled == true) serializeBlockHead("CHRR", inputDataSize, serializer); serializer.push(inputData, inputDataSize); } } @@ -302,14 +262,9 @@ class Core : private Cpu { const auto inputDataSize = impl->sram_size; const auto inputData = (uint8_t *)impl->sram; - - if (HEADBlockEnabled == true) serializeBlockHead("SRAM", inputDataSize, serializer); serializer.push(inputData, inputDataSize); } } - - // gend Block - if (HEADBlockEnabled == true) serializeBlockHead("gend", 0, serializer); } inline void deserializeState(jaffarCommon::deserializer::Base& deserializer) @@ -318,9 +273,6 @@ class Core : private Cpu error_count = 0; ppu.burst_phase = 0; // avoids shimmer when seeking to same time over and over - // NESS Block - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); - // TIME Block if (TIMEBlockEnabled == true) { @@ -328,8 +280,6 @@ class Core : private Cpu const auto outputData = (uint8_t*) &nesState; const auto inputDataSize = sizeof(nes_state_t); - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.popContiguous(outputData, inputDataSize); nes = nesState; @@ -343,8 +293,6 @@ class Core : private Cpu const auto outputData = (uint8_t*) &s; const auto inputDataSize = sizeof(cpu_state_t); - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.popContiguous(outputData, inputDataSize); r.pc = s.pc; @@ -360,8 +308,6 @@ class Core : private Cpu { const auto outputData = (uint8_t*) &ppu; const auto inputDataSize = sizeof(ppu_state_t); - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.popContiguous(outputData, inputDataSize); } @@ -372,8 +318,6 @@ class Core : private Cpu const auto outputData = (uint8_t*) &apuState; const auto inputDataSize = sizeof(Apu::apu_state_t); - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.popContiguous(outputData, inputDataSize); impl->apu.load_state(apuState); @@ -385,8 +329,6 @@ class Core : private Cpu { const auto outputData = (uint8_t*) &joypad; const auto inputDataSize = sizeof(joypad_state_t); - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.popContiguous(outputData, inputDataSize); } @@ -397,8 +339,6 @@ class Core : private Cpu const auto outputData = (uint8_t*) mapper->state; const auto inputDataSize = mapper->state_size; - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.popContiguous(outputData, inputDataSize); mapper->apply_mapping(); @@ -409,8 +349,6 @@ class Core : private Cpu { const auto outputData = (uint8_t*) low_mem; const auto inputDataSize = low_ram_size; - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.pop(outputData, inputDataSize); } @@ -419,8 +357,6 @@ class Core : private Cpu { const auto outputData = (uint8_t*) ppu.spr_ram; const auto inputDataSize = Ppu::spr_ram_size; - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.pop(outputData, inputDataSize); } @@ -431,8 +367,6 @@ class Core : private Cpu const auto outputData = (uint8_t*) ppu.impl->nt_ram; const auto inputDataSize = nametable_size; - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.pop(outputData, inputDataSize); } @@ -443,8 +377,6 @@ class Core : private Cpu { const auto outputData = (uint8_t*) ppu.impl->chr_ram; const auto inputDataSize = ppu.chr_size; - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.pop(outputData, inputDataSize); ppu.all_tiles_modified(); @@ -458,16 +390,11 @@ class Core : private Cpu { const auto outputData = (uint8_t*) impl->sram; const auto inputDataSize = impl->sram_size; - - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); deserializer.pop(outputData, inputDataSize); } } if (sram_present) enable_sram(true); - - // gend Block - if (HEADBlockEnabled == true) deserializeBlockHead(deserializer); } void enableStateBlock(const std::string& block) @@ -485,7 +412,6 @@ void enableStateBlock(const std::string& block) if (block == "NTAB") { NTABBlockEnabled = true; recognizedBlock = true; } if (block == "CHRR") { CHRRBlockEnabled = true; recognizedBlock = true; } if (block == "SRAM") { SRAMBlockEnabled = true; recognizedBlock = true; } - if (block == "HEAD") { HEADBlockEnabled = true; recognizedBlock = true; } if (recognizedBlock == false) { fprintf(stderr, "Unrecognized block type: %s\n", block.c_str()); exit(-1);} }; @@ -506,7 +432,6 @@ void disableStateBlock(const std::string& block) if (block == "NTAB") { NTABBlockEnabled = false; recognizedBlock = true; } if (block == "CHRR") { CHRRBlockEnabled = false; recognizedBlock = true; } if (block == "SRAM") { SRAMBlockEnabled = false; recognizedBlock = true; } - if (block == "HEAD") { HEADBlockEnabled = false; recognizedBlock = true; } if (recognizedBlock == false) { fprintf(stderr, "Unrecognized block type: %s\n", block.c_str()); exit(-1);} }; diff --git a/tests/arkanoid.warpless.test b/tests/arkanoid.warpless.test index 46ad719..86e3bc1 100644 --- a/tests/arkanoid.warpless.test +++ b/tests/arkanoid.warpless.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "B2B30C4F30DD853C215C17B0C67CFE63D61A3062", "Initial State File": "", "Sequence File": "arkanoid.warpless.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "MAPR", "CTRL", "APUR" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "MAPR", "CTRL", "APUR" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/arkanoid.warps.test b/tests/arkanoid.warps.test index 98f9ab8..3c393f6 100644 --- a/tests/arkanoid.warps.test +++ b/tests/arkanoid.warps.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "B2B30C4F30DD853C215C17B0C67CFE63D61A3062", "Initial State File": "", "Sequence File": "arkanoid.warps.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "MAPR", "CTRL", "APUR" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "MAPR", "CTRL", "APUR" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/castlevania1.anyPercent.test b/tests/castlevania1.anyPercent.test index 2fcc901..6b34450 100644 --- a/tests/castlevania1.anyPercent.test +++ b/tests/castlevania1.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "A31B8BD5B370A9103343C866F3C2B2998E889341", "Initial State File": "", "Sequence File": "castlevania1.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/castlevania1.pacifist.test b/tests/castlevania1.pacifist.test index 568bc3c..e433ade 100644 --- a/tests/castlevania1.pacifist.test +++ b/tests/castlevania1.pacifist.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "A31B8BD5B370A9103343C866F3C2B2998E889341", "Initial State File": "", "Sequence File": "castlevania1.pacifist.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/galaga.anyPercent.test b/tests/galaga.anyPercent.test index 5f0aefb..b7cf63e 100644 --- a/tests/galaga.anyPercent.test +++ b/tests/galaga.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "DA54C223D79FA59EB95437854B677CF69B5CAC8A", "Initial State File": "", "Sequence File": "galaga.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/ironSword.anyPercent.test b/tests/ironSword.anyPercent.test index 9f1645e..61a00f8 100644 --- a/tests/ironSword.anyPercent.test +++ b/tests/ironSword.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "97B79E432F62403FB9F877090850C41112A9A168", "Initial State File": "", "Sequence File": "ironSword.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/metroid.playaround.test b/tests/metroid.playaround.test index b4d53a9..556996d 100644 --- a/tests/metroid.playaround.test +++ b/tests/metroid.playaround.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "ECF39EC5A33E6A6F832F03E8FFC61C5D53F4F90B", "Initial State File": "", "Sequence File": "metroid.playaround.sol", - "Disable State Blocks": [ "HEAD", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/microMachines.race20.test b/tests/microMachines.race20.test index cfa3e2f..ccef1d7 100644 --- a/tests/microMachines.race20.test +++ b/tests/microMachines.race20.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "EC7BB4D11AFA5A955010BB9A548C1460EAC08FE0", "Initial State File": "microMachines.race20.state", "Sequence File": "microMachines.race20.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/nigelMansell.anyPercent.test b/tests/nigelMansell.anyPercent.test index e085cf5..fc193c4 100644 --- a/tests/nigelMansell.anyPercent.test +++ b/tests/nigelMansell.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "BBE5CF2DFA0B5422776A530D6F1B617238A8569F", "Initial State File": "", "Sequence File": "nigelMansell.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/ninjaGaiden.anyPercent.test b/tests/ninjaGaiden.anyPercent.test index 6a10196..c810a8b 100644 --- a/tests/ninjaGaiden.anyPercent.test +++ b/tests/ninjaGaiden.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "CA513F841D75EFEB33BB8099FB02BEEB39F6BB9C", "Initial State File": "", "Sequence File": "ninjaGaiden.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/ninjaGaiden.pacifist.test b/tests/ninjaGaiden.pacifist.test index a5be4ee..4d42573 100644 --- a/tests/ninjaGaiden.pacifist.test +++ b/tests/ninjaGaiden.pacifist.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "CA513F841D75EFEB33BB8099FB02BEEB39F6BB9C", "Initial State File": "", "Sequence File": "ninjaGaiden.pacifist.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/ninjaGaiden2.anyPercent.test b/tests/ninjaGaiden2.anyPercent.test index 722a8a4..84b4b79 100644 --- a/tests/ninjaGaiden2.anyPercent.test +++ b/tests/ninjaGaiden2.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "B1796660E4A4CEFC72181D4BF4F97999BC048A77", "Initial State File": "", "Sequence File": "ninjaGaiden2.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/ninjaGaiden2.pacifist.test b/tests/ninjaGaiden2.pacifist.test index 5d4e5f3..5df7ac7 100644 --- a/tests/ninjaGaiden2.pacifist.test +++ b/tests/ninjaGaiden2.pacifist.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "B1796660E4A4CEFC72181D4BF4F97999BC048A77", "Initial State File": "", "Sequence File": "ninjaGaiden2.pacifist.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/novaTheSquirrel.anyPercent.test b/tests/novaTheSquirrel.anyPercent.test index 6ade17f..4a79f40 100644 --- a/tests/novaTheSquirrel.anyPercent.test +++ b/tests/novaTheSquirrel.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "B6B07EE76492ED475F39167C89B342353F999231", "Initial State File": "", "Sequence File": "novaTheSquirrel.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/princeOfPersia.anyPercent.test b/tests/princeOfPersia.anyPercent.test index a4ad4f2..9177758 100644 --- a/tests/princeOfPersia.anyPercent.test +++ b/tests/princeOfPersia.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "6B58F149F34FA829135619C58700CAAA95B9CDE3", "Initial State File": "", "Sequence File": "princeOfPersia.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/rcProAmII.race1.test b/tests/rcProAmII.race1.test index 5ef8511..cf3f0e1 100644 --- a/tests/rcProAmII.race1.test +++ b/tests/rcProAmII.race1.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "8C68582BDAA32FBC8C7CD858991D4E00D3B1569C", "Initial State File": "", "Sequence File": "rcProAmII.race1.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "NTAB", "SPRT", "CTRL", "APUR" ], + "Disable State Blocks": [ "SRAM", "NTAB", "SPRT", "CTRL", "APUR" ], "Controller 1 Type": "FourScore1", "Controller 2 Type": "FourScore2", "Differential Compression": diff --git a/tests/saintSeiyaKanketsuHen.anyPercent.test b/tests/saintSeiyaKanketsuHen.anyPercent.test index 59c7273..21bd8d1 100644 --- a/tests/saintSeiyaKanketsuHen.anyPercent.test +++ b/tests/saintSeiyaKanketsuHen.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "F871D9B3DAFDDCDAD5F2ACD71044292E5169064E", "Initial State File": "", "Sequence File": "saintSeiyaKanketsuHen.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/saintSeiyaOugonDensetsu.anyPercent.test b/tests/saintSeiyaOugonDensetsu.anyPercent.test index cd456cc..9e69327 100644 --- a/tests/saintSeiyaOugonDensetsu.anyPercent.test +++ b/tests/saintSeiyaOugonDensetsu.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "3F3B499CF50386084E053BCA096AE8E52330CFAE", "Initial State File": "", "Sequence File": "saintSeiyaKanketsuHen.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/saiyuukiWorld.anyPercent.test b/tests/saiyuukiWorld.anyPercent.test index 4a4251a..bfc2d94 100644 --- a/tests/saiyuukiWorld.anyPercent.test +++ b/tests/saiyuukiWorld.anyPercent.test @@ -3,7 +3,7 @@ "Expected ROM SHA1": "C2F12D915A4D0B1FFDF8A64AE1092CE6A2D08770", "Initial State File": "", "Sequence File": "saiyuukiWorld.anyPercent.sol", - "Disable State Blocks": [ "HEAD", "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], + "Disable State Blocks": [ "SRAM", "CHRR", "NTAB", "SPRT", "CTRL" ], "Controller 1 Type": "Joypad", "Controller 2 Type": "None", "Differential Compression": diff --git a/tests/saiyuukiWorld.lastHalf.state b/tests/saiyuukiWorld.lastHalf.state index 0a8255f914941864b53cf6e745d0337e82c5e99a..d1b16d25b813bd57cc7ec8f16719f09e9a4ad0d9 100644 GIT binary patch delta 78 zcmZqN!Z>p?BOez71H=1J28NAa{<3hhPSi7I*6T}{n4`@2f8qoc-v9sq1LYxrap6sl e#Sb|cCl|6hY}VvDz`yvTq{3!Ks~_@{gg5~1P#K~C delta 193 zcmbQanXz#Tqn@8@aPWU12=VlFCqVS-4pl7y^KN6NZU= z#@wL>430pK2T*dNi!vj_#0(Wx=a3*D9-siwARq|=zK#Jwj6f!%PmrT81JJC6GdVbd z1A;;rfTEKbnPnz#WqQKq7vku|ATZgG)oJrh&I9~x&K^NQ3