zilmar
|
8272d18aa6
|
Reorder MoveConstHalfToX86regPointer parameters
|
2022-11-07 10:43:27 +10:30 |
|
zilmar
|
0123100233
|
Core: reorder MoveConstHalfToVariable parameters
|
2022-11-07 10:37:29 +10:30 |
|
zilmar
|
bdb2d040f9
|
Core: reorder MoveConstByteToVariable parameters
|
2022-11-07 10:34:25 +10:30 |
|
zilmar
|
eb8b36603b
|
Core: remove MoveConstByteToN64Mem, MoveConstHalfToN64Mem, MoveConstToN64Mem, MoveConstToN64MemDisp
|
2022-11-07 10:27:22 +10:30 |
|
zilmar
|
09fb90117e
|
Core: reorder CompConstToVariable parameters
|
2022-11-07 10:11:55 +10:30 |
|
zilmar
|
ade6787e6d
|
Core: Reorder AndVariableToX86Reg parameters
|
2022-11-07 10:00:35 +10:30 |
|
zilmar
|
513ca57f46
|
Core: Reorder parameters for AndVariableDispToX86Reg
|
2022-11-07 09:51:41 +10:30 |
|
zilmar
|
897fd39a0e
|
Core: reorder AndConstToVariable parameters
|
2022-11-07 09:40:12 +10:30 |
|
zilmar
|
c13080d7c3
|
Core: Reorder AddX86regToVariable parameters
|
2022-11-07 09:34:34 +10:30 |
|
zilmar
|
dbd20dd993
|
Core: Reorder AddConstToVariable parameters
|
2022-11-07 09:29:06 +10:30 |
|
zilmar
|
94247ce1a6
|
Core: handle better CX86RecompilerOps::ResetMemoryStack
|
2022-10-28 16:41:24 +10:30 |
|
zilmar
|
6c9237f603
|
Core: Get recompiler to handle RESERVED31
|
2022-10-24 16:50:12 +10:30 |
|
zilmar
|
d06d1526d9
|
Core: Change the order of MoveVariableToX86reg parameters
|
2022-10-24 16:05:19 +10:30 |
|
zilmar
|
af3c31b0ff
|
Core: Change the order of MoveConstToX86Pointer
|
2022-10-24 15:09:24 +10:30 |
|
zilmar
|
538933e0a5
|
Core: reoder MoveConstToX86reg parameters
|
2022-10-24 15:05:31 +10:30 |
|
zilmar
|
dd61a4351d
|
Core: Reorder the order of MoveX86regToX86regPointer
|
2022-10-24 12:56:38 +10:30 |
|
zilmar
|
fdbc31961f
|
Core: Change the order of MoveX86RegToX86Reg
|
2022-10-24 12:48:51 +10:30 |
|
zilmar
|
8713878994
|
Core: Change order of MoveX86regToX86Pointer parameters
|
2022-10-24 12:13:48 +10:30 |
|
zilmar
|
ae6157427f
|
Recompiler: Handle stack if it is in IMEM/DMEM
|
2022-10-21 10:03:33 +10:30 |
|
zilmar
|
96244cd6fd
|
Core: Update NonMemory Access to pifram
|
2022-10-17 11:31:54 +10:30 |
|
zilmar
|
c16307ec0f
|
Core: Move Pifram code into PifRamHandler
|
2022-10-17 08:27:52 +10:30 |
|
zilmar
|
315231d439
|
Core: Writing to 0x0410000C was not calling AfterCallDirect()
|
2022-10-11 17:31:28 +10:30 |
|
zilmar
|
2199c9cd1f
|
Core: Inherit STATE_CONST_64 in CX86RecompilerOps::InheritParentInfo
|
2022-10-11 17:24:06 +10:30 |
|
zilmar
|
801a3e29fc
|
Core: Handle more with LW and invalid addresses
|
2022-10-10 20:25:16 +10:30 |
|
zilmar
|
082ec9c22e
|
Core: Handle unaligned LH
|
2022-10-10 17:17:56 +10:30 |
|
zilmar
|
ca037abf2b
|
Core: Update counters when updating wired
|
2022-10-10 15:44:52 +10:30 |
|
zilmar
|
29e1468338
|
Core: Ignore next targeting branch if last op in block
|
2022-10-10 14:30:20 +10:30 |
|
zilmar
|
0848bab003
|
Core: do not predefine temp reg
|
2022-10-10 13:57:10 +10:30 |
|
zilmar
|
6044222be0
|
Core: Remove temp usage of Name
|
2022-10-10 13:38:43 +10:30 |
|
zilmar
|
0ffaf43418
|
Core: fix CX86RecompilerOps::LD when rt==base
|
2022-10-10 12:41:12 +10:30 |
|
zilmar
|
96cece6cd9
|
Core: Update timing around exception in DADD/DSUB
|
2022-10-10 12:34:11 +10:30 |
|
zilmar
|
3a87c3c5ad
|
Core: Update timing around exception in ADD/SUB
|
2022-10-10 12:28:06 +10:30 |
|
zilmar
|
3b57424b86
|
Core: DMTC/MT should not be updating registers
|
2022-10-10 12:16:27 +10:30 |
|
zilmar
|
481f1c50c8
|
Core: Add break op to recompiler
|
2022-10-10 12:07:04 +10:30 |
|
zilmar
|
fc247fd953
|
Core: Get recompiler to handle DADDI/DADDIU
|
2022-10-10 11:53:30 +10:30 |
|
zilmar
|
a8add093d1
|
Core: Add CPO_DMF/CPO_DMT to recompiler
|
2022-10-10 11:38:55 +10:30 |
|
zilmar
|
761a1ee52a
|
Code clean up
|
2022-10-10 10:52:17 +10:30 |
|
zilmar
|
1c77f6f0fd
|
Core: Make Cop0 64bit
|
2022-09-19 16:36:44 +09:30 |
|
zilmar
|
457937f039
|
Core: Map temp pass in flag for 8 bit register
|
2022-09-12 06:01:43 +09:30 |
|
zilmar
|
479e2e518c
|
Core: Syscall should increment cycle count
|
2022-09-05 20:00:28 +09:30 |
|
zilmar
|
c380571d8b
|
Core: Update when branch goes to the opcode after the delay slot
|
2022-09-05 19:42:22 +09:30 |
|
zilmar
|
17b78bc705
|
Core: Clean up CExitInfo::EXIT_REASON enum
|
2022-09-05 17:42:41 +09:30 |
|
zilmar
|
18b9892bc7
|
Core: Add handling of overflow exception
|
2022-09-05 16:35:13 +09:30 |
|
zilmar
|
a5c6f25ee3
|
Core: CX86RecompilerOps::BaseOffsetAddress should not unprotect unless it actually protected
|
2022-09-05 10:41:18 +09:30 |
|
zilmar
|
d82a370e59
|
Core: Create a x86RegIndex enum
|
2022-08-29 11:49:20 +09:30 |
|
zilmar
|
b88a1ccc1e
|
Core: Fix bug in div for recompiler
|
2022-08-29 08:33:13 +09:30 |
|
zilmar
|
6782599687
|
Core: Create a x86 call for calling this functions
|
2022-08-29 08:32:02 +09:30 |
|
zilmar
|
52a30b78fb
|
Core: Handle div/0 better
|
2022-08-22 22:13:53 +09:30 |
|
zilmar
|
f3a392489a
|
Core: Do not fail on checking delay slot, if it is invalid memory
|
2022-08-22 13:02:25 +09:30 |
|
zilmar
|
9b16d29792
|
Core: Add rom write decay and some code clean up
|
2022-08-22 12:47:44 +09:30 |