zilmar
|
46e6e54f24
|
RSP: improve running RSP multithreaded
|
2023-09-28 14:46:36 +09:30 |
|
zilmar
|
15e6e460d2
|
Rsp: Clean up VRCP, VRCPL, VRCPH, VRSQ, VRSQL, VRSQH
|
2023-09-28 13:39:23 +09:30 |
|
zilmar
|
3c52d8e2e3
|
RSP: use vt instead of rt when using RSP_Vect
|
2023-09-28 11:57:29 +09:30 |
|
zilmar
|
0bd6a96118
|
RSP: fix display of VRCP instruction
|
2023-09-28 11:54:50 +09:30 |
|
zilmar
|
b1240072c6
|
RSP: move Enter_RSP_Register_Window & UpdateRSPRegistersScreen function definition out of RSP core
|
2023-09-28 11:53:57 +09:30 |
|
zilmar
|
ac3e0f83d1
|
Rsp: Use RSP Register Handler
|
2023-09-28 11:52:06 +09:30 |
|
zilmar
|
bd1ec4ff0f
|
Core: Create a setting for RDRAM Size that plugins can read
|
2023-09-28 07:29:11 +09:30 |
|
zilmar
|
f817becf9c
|
Core: Create a handler for RSP registers that is accessible to the core and the RSP
|
2023-09-28 07:03:01 +09:30 |
|
zilmar
|
32ff820a03
|
RSP: clean up vector compare ops (VLT, VEQ, VNE, VGE, VCH)
|
2023-09-21 15:51:16 +09:30 |
|
zilmar
|
dc95d2f7a4
|
RSP: Clean up vector ops (VADD, VSUB, VABS, VSUBC, VMRG, VAND, VNAND, VOR, VNOR, VXOR, VNXOR)
|
2023-09-21 15:44:07 +09:30 |
|
zilmar
|
174e751a4a
|
RSP: Fix up load ops (LUV, LHV, LFV, LTV)
|
2023-09-21 15:30:07 +09:30 |
|
zilmar
|
bdaf8cf78c
|
RSP: Clean up store vector ops (SHV, SFV, STV, SWV)
|
2023-09-21 15:25:45 +09:30 |
|
zilmar
|
5dcc7e200f
|
Rsp: Move InitilizeRSPRegisters and InitilizeRSP into rsp-core
|
2023-09-21 15:16:26 +09:30 |
|
zilmar
|
002f2e17c3
|
RSP: Clean up code for vector multiple ops
|
2023-09-07 11:54:36 +09:30 |
|
zilmar
|
4e9a692449
|
RSP: Add RSP_Vector_VRNDP
|
2023-09-07 11:41:17 +09:30 |
|
zilmar
|
0cadbe0f70
|
RSP: Add clamp16
|
2023-09-07 11:31:31 +09:30 |
|
zilmar
|
af1c0c2b55
|
RSP: Add Vmulq
|
2023-09-07 11:30:15 +09:30 |
|
zilmar
|
d468b863c2
|
Rsp: add vnop for vnull
|
2023-09-07 11:29:16 +09:30 |
|
zilmar
|
8b71ef3bc1
|
RSP: Add RSP_Vector_Reserved
|
2023-09-07 11:23:35 +09:30 |
|
zilmar
|
ab67374c8a
|
RSP: Update the display of RSP opcodes in debugger
|
2023-09-07 11:19:44 +09:30 |
|
zilmar
|
625f532d73
|
RSP: use __debugbreak not DebugBreak
|
2023-08-24 10:44:45 +09:30 |
|
zilmar
|
47f14016e6
|
RSP: Set RSP_JumpTo before register in JALR, BLTZAL, BGEZAL
|
2023-08-24 10:35:51 +09:30 |
|
zilmar
|
ae9912b068
|
RSP: Clean up VCR
|
2023-08-24 10:31:26 +09:30 |
|
zilmar
|
7db5876927
|
RSP: Clean up VCL
|
2023-08-24 10:07:05 +09:30 |
|
zilmar
|
9dab3481ae
|
RSP: Add class to wrap around RSP flag
|
2023-08-24 08:00:29 +09:30 |
|
zilmar
|
0cb43e0c33
|
RSP: Remove flag to swap vector register endian
|
2023-08-24 07:04:35 +09:30 |
|
zilmar
|
a80860605d
|
RSP: fix up usage of Indx in recompiler
|
2023-08-17 14:38:51 +09:30 |
|
zilmar
|
3394be733f
|
RSP: Fix up AccurateEmulation for interpreter
|
2023-08-17 14:22:54 +09:30 |
|
zilmar
|
54be4d8135
|
Rsp: Add a rsp AccurateEmulation flag for new rsp work
|
2023-08-17 12:04:06 +09:30 |
|
zilmar
|
09ef426ac6
|
Rsp: Fix memory allocation of recompiler memory
|
2023-08-17 11:37:03 +09:30 |
|
zilmar
|
6b30c1ae6a
|
Rsp: Move Recompiler in to rsp-core
|
2023-08-17 08:59:22 +09:30 |
|
zilmar
|
1f0151e067
|
RSP: fix up clang formatting
|
2023-08-10 21:50:01 +09:30 |
|
zilmar
|
6bdc898248
|
RSP: fix LPV
|
2023-08-10 20:52:50 +09:30 |
|
zilmar
|
c6c0a4a6d2
|
RSP: fix LDV
|
2023-08-10 16:06:38 +09:30 |
|
zilmar
|
1d492262fd
|
RSP: use std::min for length calculation
|
2023-08-10 14:24:33 +09:30 |
|
zilmar
|
60192a7f33
|
RSP: Move more functionality in to rsp-core
|
2023-08-10 14:16:57 +09:30 |
|
zilmar
|
25e48405c5
|
RSP: Start to split out RSP in to core and UI for plugin
|
2023-08-10 10:27:11 +09:30 |