Commit Graph

111 Commits

Author SHA1 Message Date
zilmar 2336fd0fc9 [Project64] Update logging in CArmRegInfo::Map_GPR_32bit 2016-11-23 09:02:55 +11:00
zilmar 5d5b14de47 [Project64] Add CArmRegInfo::operator== 2016-11-23 08:52:05 +11:00
zilmar 94c9cc1848 [Project64] Add CArmRegInfo::UnProtectGPR 2016-11-23 08:48:41 +11:00
zilmar d1a2e29f9b [Project64] Add LogRegisterState when no registers available 2016-11-23 08:47:28 +11:00
zilmar b8985ce815 [Project64] Keep Arm_R11 for temp reg 2016-11-23 08:39:40 +11:00
zilmar 442429b5dc [Project64] Add more variable to map and fix reg for GPR variable 2016-11-23 08:29:11 +11:00
zilmar a8eda0d391 [Project64] Add CArmRegInfo::VariableMapName 2016-11-23 06:28:54 +11:00
zilmar 13a1f9fc25 [Project64] fix CArmRecompilerOps::ADDI 2016-11-22 22:40:55 +11:00
zilmar 13fa7446df [Project64] WriteBack_GPR instead of unmap 2016-11-22 22:39:24 +11:00
zilmar 7cf0fe045f [Project64] Update CArmRecompilerOps::JAL 2016-11-22 21:30:05 +11:00
zilmar e6b483ef85 [Project64] Update CArmRecompilerOps::BLEZ_Compare 2016-11-22 21:28:56 +11:00
zilmar c166c307a2 Update CArmRecompilerOps::BEQ_Compare 2016-11-22 21:22:39 +11:00
zilmar b9d21af5b5 [Project64] Update CArmRecompilerOps::BNE_Compare 2016-11-22 21:21:07 +11:00
zilmar 3846cb4515 Remove CDebugSettings from CArmRecompilerOps 2016-11-22 21:18:09 +11:00
zilmar 5ea6c2c0c5 [Projec64] Fix CArmOps::MoveConstToArmReg to use compress value 2016-11-22 21:09:10 +11:00
zilmar 4053bc2286 [Project64] Fix CArmOps::SetJump20 for negative 2016-11-22 21:07:44 +11:00
zilmar a5a1547131 [Project64] Get CArmOps::MoveConstToArmReg to work in IT block 2016-11-22 20:56:36 +11:00
zilmar 3704300b44 [Project64] Update CArmOps::SubConstFromArmReg to have source and dest reg 2016-11-22 20:41:19 +11:00
zilmar e5b260b078 [Project64] Add ArmBreakPoint 2016-11-22 18:09:37 +11:00
zilmar 28e4ba2e8c [Project64] Add CArmOps::ProgressItBlock 2016-11-22 18:06:50 +11:00
zilmar 88fc1130c8 [Project64] Add comment to StoreArmRegToArmRegPointer 2016-11-22 18:04:17 +11:00
zilmar b046831771 [Project64] Add CArmOps::SubArmRegFromArmReg 2016-11-22 18:02:53 +11:00
zilmar abb764d0c4 [Project64] Add CArmOps::StoreArmRegToArmRegPointer 2016-11-22 18:00:45 +11:00
zilmar 7ea5418168 [Project64] Add CArmOps::OrConstToVariable 2016-11-22 17:59:04 +11:00
zilmar e1e82546bb [Project64] Add CArmOps::OrConstToArmReg 2016-11-22 17:57:54 +11:00
zilmar b672cfa21b [Project64] Add CArmOps::MoveArmRegToVariable 2016-11-22 17:56:23 +11:00
zilmar 86d7fbd4b8 [Project64] Add comment to LoadArmRegPointerToArmReg 2016-11-22 17:54:46 +11:00
zilmar 4686ce7127 [Project64] Add LoadArmRegPointerByteToArmReg 2016-11-22 17:53:10 +11:00
zilmar e42cb0f2c7 [Project64] Fix up usage of AndArmRegToArmReg 2016-11-22 17:52:04 +11:00
zilmar afd92fc562 [Project64] Add second source to AndArmRegToArmReg 2016-11-22 17:48:03 +11:00
zilmar beea1d8c27 [Project64] Add AndConstToArmReg 2016-11-22 17:45:07 +11:00
zilmar 0b53e3e584 [Projec64] Add AndConstToVariable 2016-11-22 17:43:59 +11:00
zilmar ae27b59621 [Project64] Rename ArmBranchCompare to ArmCompareType 2016-11-22 17:41:46 +11:00
zilmar dff480d6dc [Android] Add CArmOps::IfBlock 2016-11-22 17:34:47 +11:00
zilmar cb29d3b98e [Android] Add another case to ThumbCompressConst 2016-11-22 07:51:08 +11:00
zilmar 97f1d8302d [Android] Handle SPECIAL_XOR recompiler case 2016-10-09 20:20:10 +11:00
zilmar 1686e60b26 [Android] Fix CArmRecompilerOps::CompileReadTLBMiss 2016-10-06 22:59:03 +11:00
zilmar 3be044ba71 [Android] Fix up compilation issues 2016-10-02 07:22:10 +11:00
zilmar bd2d5b507a [Android] in CArmRecompilerOps::CompileInterpterCall load the variable after BeforeCallDirect 2016-10-02 07:05:37 +11:00
zilmar 9a6c8419e9 [Android] Optimize CArmRecompilerOps::UpdateCounters 2016-10-02 07:03:12 +11:00
zilmar c2a960771c [Android] make sure the working reg set is not changed in CArmRecompilerOps::CompileSystemCheck 2016-10-02 07:00:23 +11:00
zilmar f3ebb20bb1 [Android] Have CArmRecompilerOps::CompileExit write back as the working reg set 2016-10-02 06:55:59 +11:00
zilmar 41baaa015b [Android] Get CArmRecompilerOps::CompileCop1Test to use temp registers 2016-10-02 06:54:22 +11:00
zilmar d8bab5ac7f [Android] Push the rest of the register on enter/exit code block 2016-10-02 06:53:18 +11:00
zilmar a302c17a76 [Android] get CArmRecompilerOps::COP1_S_MUL to use register caching 2016-10-01 22:01:58 +10:00
zilmar 56cbe56482 [Android] CArmRecompilerOps::SPECIAL_XOR use register caching 2016-10-01 21:59:52 +10:00
zilmar 4a5ede2287 [Android] get CArmRecompilerOps::SPECIAL_JALR to use dynamic registers 2016-10-01 21:40:58 +10:00
zilmar 8f6ca9c15a [Android[ void CArmRecompilerOps::SPECIAL_JR() 2016-10-01 20:52:33 +10:00
zilmar 75fba4be38 [Android] get CArmRecompilerOps::LWC1 to use reg caching 2016-10-01 20:35:02 +10:00
zilmar b2ebefd767 [Android] fix CArmRecompilerOps::CACHE() 2016-10-01 20:33:17 +10:00