keep $zero overwrite prevention to a single location in CPU loop
In both the 32- and the 64-bit interpreters, ADDI, LUI, LB, LW, LWU, LL, SLLV all check if the destination register specifier is 0, when none of the other interpreter ops do. Actually, none of these 7 need to really check it either, since handling $zero overwrite is already managed in a single location in the main interpreter loop.
This commit is contained in:
parent
b6341d0b92
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dc103ec59b
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@ -337,7 +337,7 @@ void CInterpreterCPU::ExecuteOps ( int Cycles )
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//WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %d %d",*_PROGRAM_COUNTER,*g_NextTimer,g_SystemTimer->CurrentType());
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//WriteTraceF((TraceType)(TraceError | TraceNoHeader),"%X: %d %d",*_PROGRAM_COUNTER,*g_NextTimer,g_SystemTimer->CurrentType());
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}*/
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}*/
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m_R4300i_Opcode[ Opcode.op ]();
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m_R4300i_Opcode[ Opcode.op ]();
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_GPR[0].DW = 0;
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_GPR[0].DW = 0; /* MIPS $zero hard-wired to 0 */
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Cycles -= CountPerOp;
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Cycles -= CountPerOp;
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*g_NextTimer -= CountPerOp;
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*g_NextTimer -= CountPerOp;
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@ -709,7 +709,6 @@ void R4300iOp32::ADDI (void) {
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StackValue += (short)m_Opcode.immediate;
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StackValue += (short)m_Opcode.immediate;
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}
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}
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#endif
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#endif
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if (m_Opcode.rt == 0) { return; }
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_GPR[m_Opcode.rt].W[0] = (_GPR[m_Opcode.rs].W[0] + ((short)m_Opcode.immediate));
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_GPR[m_Opcode.rt].W[0] = (_GPR[m_Opcode.rs].W[0] + ((short)m_Opcode.immediate));
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#ifdef Interpreter_StackTest
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#ifdef Interpreter_StackTest
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if (m_Opcode.rt == 29 && m_Opcode.rs != 29) {
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if (m_Opcode.rt == 29 && m_Opcode.rs != 29) {
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@ -761,7 +760,6 @@ void R4300iOp32::XORI (void) {
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}
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}
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void R4300iOp32::LUI (void) {
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void R4300iOp32::LUI (void) {
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if (m_Opcode.rt == 0) { return; }
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_GPR[m_Opcode.rt].W[0] = (long)((short)m_Opcode.offset << 16);
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_GPR[m_Opcode.rt].W[0] = (long)((short)m_Opcode.offset << 16);
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#ifdef Interpreter_StackTest
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#ifdef Interpreter_StackTest
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if (m_Opcode.rt == 29) {
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if (m_Opcode.rt == 29) {
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@ -840,7 +838,6 @@ void R4300iOp32::BGTZL (void) {
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void R4300iOp32::LB (void) {
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void R4300iOp32::LB (void) {
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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if (m_Opcode.rt == 0) { return; }
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if (!g_MMU->LB_VAddr(Address,_GPR[m_Opcode.rt].UB[0])) {
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if (!g_MMU->LB_VAddr(Address,_GPR[m_Opcode.rt].UB[0])) {
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if (bShowTLBMisses()) {
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if (bShowTLBMisses()) {
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g_Notify->DisplayError(L"LB TLB: %X",Address);
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g_Notify->DisplayError(L"LB TLB: %X",Address);
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@ -892,8 +889,6 @@ void R4300iOp32::LW (void) {
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Log_LW((*_PROGRAM_COUNTER),Address);
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Log_LW((*_PROGRAM_COUNTER),Address);
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}
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}
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if (m_Opcode.rt == 0) { return; }
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
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if (bShowTLBMisses()) {
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if (bShowTLBMisses()) {
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g_Notify->DisplayError(L"LW TLB: %X",Address);
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g_Notify->DisplayError(L"LW TLB: %X",Address);
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@ -952,7 +947,6 @@ void R4300iOp32::LWR (void) {
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void R4300iOp32::LWU (void) {
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void R4300iOp32::LWU (void) {
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
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if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
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if (m_Opcode.rt == 0) { return; }
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
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if (bShowTLBMisses()) {
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if (bShowTLBMisses()) {
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@ -969,8 +963,6 @@ void R4300iOp32::LL (void) {
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
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if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
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if (m_Opcode.rt == 0) { return; }
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
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if (bShowTLBMisses()) {
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if (bShowTLBMisses()) {
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g_Notify->DisplayError(L"LL TLB: %X",Address);
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g_Notify->DisplayError(L"LL TLB: %X",Address);
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@ -996,7 +988,6 @@ void R4300iOp32::SPECIAL_SRA (void) {
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}
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}
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void R4300iOp32::SPECIAL_SLLV (void) {
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void R4300iOp32::SPECIAL_SLLV (void) {
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if (m_Opcode.rd == 0) { return; }
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_GPR[m_Opcode.rd].W[0] = (_GPR[m_Opcode.rt].W[0] << (_GPR[m_Opcode.rs].UW[0] & 0x1F));
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_GPR[m_Opcode.rd].W[0] = (_GPR[m_Opcode.rt].W[0] << (_GPR[m_Opcode.rs].UW[0] & 0x1F));
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}
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}
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@ -814,7 +814,6 @@ void R4300iOp::ADDI (void)
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StackValue += (short)m_Opcode.immediate;
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StackValue += (short)m_Opcode.immediate;
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}
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}
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#endif
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#endif
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if (m_Opcode.rt == 0) { return; }
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_GPR[m_Opcode.rt].DW = (_GPR[m_Opcode.rs].W[0] + ((short)m_Opcode.immediate));
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_GPR[m_Opcode.rt].DW = (_GPR[m_Opcode.rs].W[0] + ((short)m_Opcode.immediate));
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#ifdef Interpreter_StackTest
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#ifdef Interpreter_StackTest
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if (m_Opcode.rt == 29 && m_Opcode.rs != 29) {
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if (m_Opcode.rt == 29 && m_Opcode.rs != 29) {
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@ -873,7 +872,6 @@ void R4300iOp::XORI (void)
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void R4300iOp::LUI (void)
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void R4300iOp::LUI (void)
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{
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{
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if (m_Opcode.rt == 0) { return; }
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_GPR[m_Opcode.rt].DW = (long)((short)m_Opcode.offset << 16);
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_GPR[m_Opcode.rt].DW = (long)((short)m_Opcode.offset << 16);
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#ifdef Interpreter_StackTest
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#ifdef Interpreter_StackTest
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if (m_Opcode.rt == 29) {
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if (m_Opcode.rt == 29) {
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@ -1016,7 +1014,6 @@ void R4300iOp::LDR (void)
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void R4300iOp::LB (void)
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void R4300iOp::LB (void)
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{
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{
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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if (m_Opcode.rt == 0) { return; }
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if (!g_MMU->LB_VAddr(Address,_GPR[m_Opcode.rt].UB[0])) {
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if (!g_MMU->LB_VAddr(Address,_GPR[m_Opcode.rt].UB[0])) {
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if (bShowTLBMisses()) {
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if (bShowTLBMisses()) {
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g_Notify->DisplayError(L"LB TLB: %X",Address);
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g_Notify->DisplayError(L"LB TLB: %X",Address);
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@ -1072,8 +1069,6 @@ void R4300iOp::LW (void)
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Log_LW((*_PROGRAM_COUNTER),Address);
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Log_LW((*_PROGRAM_COUNTER),Address);
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}
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}
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if (m_Opcode.rt == 0) { return; }
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
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if (bShowTLBMisses()) {
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if (bShowTLBMisses()) {
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g_Notify->DisplayError(L"LW TLB: %X",Address);
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g_Notify->DisplayError(L"LW TLB: %X",Address);
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@ -1136,7 +1131,6 @@ void R4300iOp::LWU (void)
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{
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{
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
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if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
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if (m_Opcode.rt == 0) { return; }
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0])) {
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if (bShowTLBMisses()) {
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if (bShowTLBMisses()) {
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@ -1381,8 +1375,6 @@ void R4300iOp::LL (void)
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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DWORD Address = _GPR[m_Opcode.base].UW[0] + (short)m_Opcode.offset;
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if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
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if ((Address & 3) != 0) { ADDRESS_ERROR_EXCEPTION(Address,TRUE); }
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if (m_Opcode.rt == 0) { return; }
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0]))
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if (!g_MMU->LW_VAddr(Address,_GPR[m_Opcode.rt].UW[0]))
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{
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{
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if (bShowTLBMisses())
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if (bShowTLBMisses())
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@ -1543,7 +1535,6 @@ void R4300iOp::SPECIAL_SRA (void)
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void R4300iOp::SPECIAL_SLLV (void)
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void R4300iOp::SPECIAL_SLLV (void)
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{
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{
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if (m_Opcode.rd == 0) { return; }
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_GPR[m_Opcode.rd].DW = (_GPR[m_Opcode.rt].W[0] << (_GPR[m_Opcode.rs].UW[0] & 0x1F));
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_GPR[m_Opcode.rd].DW = (_GPR[m_Opcode.rt].W[0] << (_GPR[m_Opcode.rs].UW[0] & 0x1F));
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}
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}
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