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[Android] Add Arm32Opcode handling for CArmOps::AddArmRegToArmReg

This commit is contained in:
zilmar 2016-09-29 21:58:10 +10:00
parent a8f2ce86f4
commit b175442aac
2 changed files with 28 additions and 10 deletions
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20
Source/Project64-core/N64System/Recompiler/Arm/ArmOps.cpp
View File

@ -31,7 +31,9 @@ void CArmOps::WriteArmLabel(const char * Label)
CPU_Message(" %s:", Label);
}
void CArmOps::AddArmRegToArmReg(ArmReg SourceReg1, ArmReg SourceReg2, ArmReg DestReg)
void CArmOps::AddArmRegToArmReg(ArmReg DestReg, ArmReg SourceReg1, ArmReg SourceReg2)
{
if (DestReg <= 7 && SourceReg1 <=7 && SourceReg2 <= 7)
{
CPU_Message(" add\t%s,%s,%s", ArmRegName(DestReg), ArmRegName(SourceReg1), ArmRegName(SourceReg2));
ArmThumbOpcode op = {0};
@ -41,7 +43,23 @@ void CArmOps::AddArmRegToArmReg(ArmReg SourceReg1, ArmReg SourceReg2, ArmReg Des
op.Reg.opcode = 0xC;
AddCode16(op.Hex);
}
else
{
CPU_Message(" add.w\t%s,%s,%s", ArmRegName(DestReg), ArmRegName(SourceReg1), ArmRegName(SourceReg2));
Arm32Opcode op = {0};
op.imm5.rn = SourceReg1;
op.imm5.s = 0;
op.imm5.opcode = 0x758;
op.imm5.rm = SourceReg2;
op.imm5.type = 0;
op.imm5.imm2 = 0;
op.imm5.rd = DestReg;
op.imm5.imm3 = 0;
op.imm5.opcode2 = 0;
AddCode32(op.Hex);
}
}
void CArmOps::AndArmRegToArmReg(ArmReg SourceReg, ArmReg DestReg)
{
CPU_Message(" and\t%s, %s", ArmRegName(DestReg), ArmRegName(SourceReg));

2
Source/Project64-core/N64System/Recompiler/Arm/ArmOps.h
View File

@ -132,7 +132,7 @@ protected:
static void WriteArmComment(const char * Comment);
static void WriteArmLabel(const char * Label);
static void AddArmRegToArmReg(ArmReg SourceReg1, ArmReg SourceReg2, ArmReg DestReg);
static void AddArmRegToArmReg(ArmReg DestReg, ArmReg SourceReg1, ArmReg SourceReg2);
static void AndArmRegToArmReg(ArmReg SourceReg, ArmReg DestReg);
static void BranchLabel8(ArmBranchCompare CompareType, const char * Label);
static void BranchLabel20(ArmBranchCompare CompareType, const char * Label);