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Cote Update PeripheralInterfaceHandler::PI_DMA_WRITE to handle misaligned, end of page test

This commit is contained in:
zilmar 2024-10-03 14:38:04 +09:30
parent 08e1b3b39b
commit 9e53b161a4
1 changed files with 9 additions and 2 deletions
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11
Source/Project64-core/N64System/MemoryHandler/PeripheralInterfaceHandler.cpp
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@ -390,15 +390,21 @@ void PeripheralInterfaceHandler::PI_DMA_WRITE()
uint8_t * Rdram = m_MMU.Rdram(); uint8_t * Rdram = m_MMU.Rdram();
uint32_t RdramSize = m_MMU.RdramSize(); uint32_t RdramSize = m_MMU.RdramSize();
uint32_t TransferLen = 0; uint32_t TransferLen = 0;
int32_t MaxBlockSize = 128;
while (Length > 0) while (Length > 0)
{ {
int32_t BlockAlign = PI_DRAM_ADDR_REG & 6; int32_t BlockAlign = PI_DRAM_ADDR_REG & 7;
int32_t BlockSize = 128 - BlockAlign; int32_t BlockSize = MaxBlockSize - BlockAlign;
int32_t BlockLen = BlockSize; int32_t BlockLen = BlockSize;
if (Length < BlockLen) if (Length < BlockLen)
{ {
BlockLen = Length; BlockLen = Length;
} }
int32_t EndOfRow = 0x800 - (PI_DRAM_ADDR_REG & 0x7ff);
if (EndOfRow < BlockLen)
{
BlockLen = EndOfRow;
}
Length -= BlockLen; Length -= BlockLen;
if (Length < 0) if (Length < 0)
{ {
@ -440,6 +446,7 @@ void PeripheralInterfaceHandler::PI_DMA_WRITE()
} }
PI_DRAM_ADDR_REG = (PI_DRAM_ADDR_REG + BlockLen + 7) & ~7; PI_DRAM_ADDR_REG = (PI_DRAM_ADDR_REG + BlockLen + 7) & ~7;
TransferLen += (BlockLen + 7) & ~7; TransferLen += (BlockLen + 7) & ~7;
MaxBlockSize = EndOfRow < 8 ? 128 - BlockAlign : 128;
FirstBlock = false; FirstBlock = false;
} }