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Core: fix CX86RecompilerOps::CompileLoadMemoryValue Map_GPR_32bit when called from LWC1

This commit is contained in:
zilmar 2024-11-21 11:10:01 +10:30
parent 48b3e5a9a2
commit 5e1a40fffb
3 changed files with 4 additions and 4 deletions
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4
Source/Project64-core/N64System/Mips/R4300iInstruction.cpp
View File

@ -199,7 +199,7 @@ void R4300iInstruction::ReadsGPR(uint32_t & Reg1, uint32_t & Reg2) const
Reg2 = 0;
}
uint32_t R4300iInstruction::WritesGPR(void) const
int32_t R4300iInstruction::WritesGPR(void) const
{
uint32_t op = m_Instruction.op;
if (op == R4300i_SPECIAL)
@ -226,7 +226,7 @@ uint32_t R4300iInstruction::WritesGPR(void) const
{
return 31; // RA
}
return (uint32_t)-1;
return -1;
}
bool R4300iInstruction::ReadsHI() const

2
Source/Project64-core/N64System/Mips/R4300iInstruction.h
View File

@ -18,7 +18,7 @@ public:
bool HasDelaySlot(void) const;
bool DelaySlotEffectsCompare(uint32_t DelayInstruction) const;
void ReadsGPR(uint32_t & Reg1, uint32_t & Reg2) const;
uint32_t WritesGPR(void) const;
int32_t WritesGPR(void) const;
bool ReadsHI() const;
bool ReadsLO() const;
bool WritesHI() const;

2
Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp
View File

@ -9771,7 +9771,7 @@ asmjit::x86::Gp CX86RecompilerOps::BaseOffsetAddress(bool UseBaseRegister)
void CX86RecompilerOps::CompileLoadMemoryValue(asmjit::x86::Gp & AddressReg, const asmjit::x86::Gp & ValueReg, const asmjit::x86::Gp & ValueRegHi, uint8_t ValueSize, bool SignExtend)
{
if (ValueSize == 32 && m_Instruction.WritesGPR() != 0)
if (ValueSize == 32 && m_Instruction.WritesGPR() > 0)
{
m_RegWorkingSet.ProtectGPR(m_Opcode.base);
m_RegWorkingSet.Map_GPR_32bit(m_Opcode.rt, true, m_Opcode.rt != m_Opcode.base ? -1 : m_Opcode.base);