RSP: implement SP_SEMAPHORE_REG
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196b8ee100
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@ -459,8 +459,6 @@ DWORD RunInterpreterCPU(DWORD Cycles) {
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break;
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break;
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}
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}
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}
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}
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*PrgCount -= 4;
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return Cycles;
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return Cycles;
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}
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}
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@ -382,9 +382,9 @@ void RSP_Cop0_MF (void) {
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case 5: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DMA_FULL_REG; break;
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case 5: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DMA_FULL_REG; break;
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case 6: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DMA_BUSY_REG; break;
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case 6: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DMA_BUSY_REG; break;
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case 7:
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case 7:
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RSP_GPR[RSPOpC.rt].W = 0;
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RSP_GPR[RSPOpC.rt].W = *RSPInfo.SP_SEMAPHORE_REG;
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//RSP_GPR[RSPOpC.rt].W = *RSPInfo.SP_SEMAPHORE_REG;
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*RSPInfo.SP_SEMAPHORE_REG = 1;
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//*RSPInfo.SP_SEMAPHORE_REG = 1;
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RSP_Running = FALSE;
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break;
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break;
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case 8: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.DPC_START_REG ; break;
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case 8: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.DPC_START_REG ; break;
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case 9: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.DPC_END_REG ; break;
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case 9: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.DPC_END_REG ; break;
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@ -1492,8 +1492,10 @@ void Compile_Cop0_MF ( void ) {
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MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
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MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
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break;
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break;
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case 7:
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case 7:
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MoveConstToVariable(0, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
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Cheat_r4300iOpcode(RSP_Cop0_MF,"RSP_Cop0_MF");
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//Cheat_r4300iOpcode(RSP_Cop0_MF,"RSP_Cop0_MF");
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MoveConstToVariable(CompilePC + 4,PrgCount,"RSP PC");
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Ret();
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NextInstruction = FINISH_BLOCK;
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break;
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break;
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case 8:
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case 8:
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MoveVariableToX86reg(RSPInfo.DPC_START_REG, "DPC_START_REG", x86_EAX);
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MoveVariableToX86reg(RSPInfo.DPC_START_REG, "DPC_START_REG", x86_EAX);
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