diff --git a/Source/RSP/Interpreter CPU.c b/Source/RSP/Interpreter CPU.c
index b4308c29f..ee264b6a0 100644
--- a/Source/RSP/Interpreter CPU.c	
+++ b/Source/RSP/Interpreter CPU.c	
@@ -459,8 +459,6 @@ DWORD RunInterpreterCPU(DWORD Cycles) {
 			break;
 		}
 	}
-	*PrgCount -= 4;
-
 	return Cycles;
 }
 
diff --git a/Source/RSP/Interpreter Ops.c b/Source/RSP/Interpreter Ops.c
index aae6b816c..e9a8d81d8 100644
--- a/Source/RSP/Interpreter Ops.c	
+++ b/Source/RSP/Interpreter Ops.c	
@@ -382,9 +382,9 @@ void RSP_Cop0_MF (void) {
 	case 5: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DMA_FULL_REG; break;
 	case 6: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.SP_DMA_BUSY_REG; break;
 	case 7: 
-		RSP_GPR[RSPOpC.rt].W = 0;
-		//RSP_GPR[RSPOpC.rt].W = *RSPInfo.SP_SEMAPHORE_REG;
-		//*RSPInfo.SP_SEMAPHORE_REG = 1;
+		RSP_GPR[RSPOpC.rt].W = *RSPInfo.SP_SEMAPHORE_REG;
+		*RSPInfo.SP_SEMAPHORE_REG = 1;
+		RSP_Running = FALSE;
 		break;
 	case 8: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.DPC_START_REG ; break;
 	case 9: RSP_GPR[RSPOpC.rt].UW = *RSPInfo.DPC_END_REG ; break;
diff --git a/Source/RSP/Recompiler Ops.c b/Source/RSP/Recompiler Ops.c
index bb7006721..77d727f57 100644
--- a/Source/RSP/Recompiler Ops.c	
+++ b/Source/RSP/Recompiler Ops.c	
@@ -1492,8 +1492,10 @@ void Compile_Cop0_MF ( void ) {
 		MoveX86regToVariable(x86_EAX, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
 		break;
 	case 7: 
-		MoveConstToVariable(0, &RSP_GPR[RSPOpC.rt].UW, GPR_Name(RSPOpC.rt));
-		//Cheat_r4300iOpcode(RSP_Cop0_MF,"RSP_Cop0_MF");
+		Cheat_r4300iOpcode(RSP_Cop0_MF,"RSP_Cop0_MF");
+		MoveConstToVariable(CompilePC + 4,PrgCount,"RSP PC");
+		Ret();
+		NextInstruction = FINISH_BLOCK;
 		break;
 	case 8:
 		MoveVariableToX86reg(RSPInfo.DPC_START_REG, "DPC_START_REG", x86_EAX);