Core: Make the FPU double ops to be modularized so it is a simple function call for an opcode
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5133d47502
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@ -8299,26 +8299,7 @@ void CX86RecompilerOps::COP1_D_ADD()
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if (FpuExceptionInRecompiler())
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{
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CompileInitFpuOperation(CRegInfo::RoundDefault);
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if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Any) ||
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m_RegWorkingSet.RegInStack(m_Opcode.ft, CRegInfo::FPU_Any) ||
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m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Any))
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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return;
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}
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asmjit::x86::Gp TempReg = m_RegWorkingSet.FPRValuePointer(Reg1, CRegInfo::FPU_Double);
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CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
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m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
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TempReg = m_RegWorkingSet.FPRValuePointer(Reg2, CRegInfo::FPU_Double);
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CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
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m_RegWorkingSet.PrepareFPTopToBe(m_Opcode.fd, Reg1, CRegInfo::FPU_Double);
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m_Assembler.fadd(asmjit::x86::qword_ptr(TempReg));
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m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
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m_Assembler.mov(TempReg, (uint64_t)&m_TempValue64);
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m_Assembler.fpuStoreQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), TempReg, false);
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CompileCheckFPUResult64(TempReg);
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m_RegWorkingSet.SetFPTopAs(m_Opcode.fd);
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COP1_D_Opcode(&CX86Ops::Fadd);
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}
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else
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{
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@ -8347,26 +8328,7 @@ void CX86RecompilerOps::COP1_D_SUB()
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if (FpuExceptionInRecompiler())
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{
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CompileInitFpuOperation(CRegInfo::RoundDefault);
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if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Any) ||
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m_RegWorkingSet.RegInStack(m_Opcode.ft, CRegInfo::FPU_Any) ||
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m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Any))
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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return;
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}
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asmjit::x86::Gp TempReg = m_RegWorkingSet.FPRValuePointer(Reg1, CRegInfo::FPU_Double);
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CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
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m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
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TempReg = m_RegWorkingSet.FPRValuePointer(Reg2, CRegInfo::FPU_Double);
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CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
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m_RegWorkingSet.PrepareFPTopToBe(m_Opcode.fd, Reg1, CRegInfo::FPU_Double);
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m_Assembler.fsub(asmjit::x86::qword_ptr(TempReg));
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m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
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m_Assembler.mov(TempReg, (uint64_t)&m_TempValue64);
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m_Assembler.fpuStoreQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), TempReg, false);
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CompileCheckFPUResult64(TempReg);
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m_RegWorkingSet.SetFPTopAs(m_Opcode.fd);
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COP1_D_Opcode(&CX86Ops::Fsub);
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}
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else
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{
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@ -8407,26 +8369,7 @@ void CX86RecompilerOps::COP1_D_MUL()
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if (FpuExceptionInRecompiler())
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{
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CompileInitFpuOperation(CRegInfo::RoundDefault);
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if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Any) ||
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m_RegWorkingSet.RegInStack(m_Opcode.ft, CRegInfo::FPU_Any) ||
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m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Any))
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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return;
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}
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asmjit::x86::Gp TempReg = m_RegWorkingSet.FPRValuePointer(Reg1, CRegInfo::FPU_Double);
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CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
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m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
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TempReg = m_RegWorkingSet.FPRValuePointer(Reg2, CRegInfo::FPU_Double);
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CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
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m_RegWorkingSet.PrepareFPTopToBe(m_Opcode.fd, Reg1, CRegInfo::FPU_Double);
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m_Assembler.fmul(asmjit::x86::qword_ptr(TempReg));
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m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
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m_Assembler.mov(TempReg, (uint64_t)&m_TempValue64);
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m_Assembler.fpuStoreQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), TempReg, false);
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CompileCheckFPUResult64(TempReg);
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m_RegWorkingSet.SetFPTopAs(m_Opcode.fd);
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COP1_D_Opcode(&CX86Ops::Fmul);
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}
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else
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{
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@ -8456,26 +8399,7 @@ void CX86RecompilerOps::COP1_D_DIV()
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if (FpuExceptionInRecompiler())
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{
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CompileInitFpuOperation(CRegInfo::RoundDefault);
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if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Any) ||
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m_RegWorkingSet.RegInStack(m_Opcode.ft, CRegInfo::FPU_Any) ||
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m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Any))
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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return;
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}
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asmjit::x86::Gp TempReg = m_RegWorkingSet.FPRValuePointer(Reg1, CRegInfo::FPU_Double);
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CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
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m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
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TempReg = m_RegWorkingSet.FPRValuePointer(Reg2, CRegInfo::FPU_Double);
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CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
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m_RegWorkingSet.PrepareFPTopToBe(m_Opcode.fd, Reg1, CRegInfo::FPU_Double);
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m_Assembler.fdiv(asmjit::x86::qword_ptr(TempReg));
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m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
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m_Assembler.mov(TempReg, (uint64_t)&m_TempValue64);
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m_Assembler.fpuStoreQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), TempReg, false);
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CompileCheckFPUResult64(TempReg);
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m_RegWorkingSet.SetFPTopAs(m_Opcode.fd);
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COP1_D_Opcode(&CX86Ops::Fdiv);
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}
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else
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{
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@ -10948,6 +10872,30 @@ void CX86RecompilerOps::CompileStoreMemoryValue(asmjit::x86::Gp AddressReg, asmj
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}
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}
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void CX86RecompilerOps::COP1_D_Opcode(void (CX86Ops::*Instruction)(const asmjit::x86::Mem &))
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{
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CompileInitFpuOperation(CRegInfo::RoundDefault);
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if (m_RegWorkingSet.RegInStack(m_Opcode.fs, CRegInfo::FPU_Any) ||
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m_RegWorkingSet.RegInStack(m_Opcode.ft, CRegInfo::FPU_Any) ||
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m_RegWorkingSet.RegInStack(m_Opcode.fd, CRegInfo::FPU_Any))
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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return;
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}
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asmjit::x86::Gp TempReg = m_RegWorkingSet.FPRValuePointer(m_Opcode.fs, CRegInfo::FPU_Double);
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CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
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m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
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TempReg = m_RegWorkingSet.FPRValuePointer(m_Opcode.ft, CRegInfo::FPU_Double);
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CompileCheckFPUInput(TempReg, FpuOpSize_64bit);
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m_RegWorkingSet.PrepareFPTopToBe(m_Opcode.fd, m_Opcode.fs, CRegInfo::FPU_Double);
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(m_Assembler.*Instruction)(asmjit::x86::qword_ptr(TempReg));
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m_RegWorkingSet.SetX86Protected(GetIndexFromX86Reg(TempReg), false);
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m_Assembler.mov(TempReg, (uint64_t)&m_TempValue64);
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m_Assembler.fpuStoreQwordFromX86Reg(m_RegWorkingSet.StackTopPos(), TempReg, false);
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CompileCheckFPUResult64(TempReg);
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m_RegWorkingSet.SetFPTopAs(m_Opcode.fd);
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}
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void CX86RecompilerOps::SB_Const(uint32_t Value, uint32_t VAddr)
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{
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if (VAddr < 0x80000000 || VAddr >= 0xC0000000)
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@ -270,6 +270,7 @@ private:
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asmjit::x86::Gp BaseOffsetAddress(bool UseBaseRegister);
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void CompileLoadMemoryValue(asmjit::x86::Gp & AddressReg, asmjit::x86::Gp ValueReg, const asmjit::x86::Gp & ValueRegHi, uint8_t ValueSize, bool SignExtend);
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void CompileStoreMemoryValue(asmjit::x86::Gp AddressReg, asmjit::x86::Gp ValueReg, const asmjit::x86::Gp & ValueRegHi, uint64_t Value, uint8_t ValueSize);
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void COP1_D_Opcode(void (CX86Ops::*Instruction)(const asmjit::x86::Mem &));
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void SB_Const(uint32_t Value, uint32_t Addr);
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void SB_Register(const asmjit::x86::Gp & Reg, uint32_t Addr);
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@ -233,6 +233,26 @@ void CX86Ops::CompX86regToVariable(const asmjit::x86::Gp & Reg, void * Variable,
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}
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}
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void CX86Ops::Fadd(const asmjit::x86::Mem & Mem)
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{
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fadd(Mem);
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}
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void CX86Ops::Fdiv(const asmjit::x86::Mem & Mem)
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{
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fdiv(Mem);
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}
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void CX86Ops::Fmul(const asmjit::x86::Mem & Mem)
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{
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fmul(Mem);
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}
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void CX86Ops::Fsub(const asmjit::x86::Mem & Mem)
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{
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fsub(Mem);
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}
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void CX86Ops::JaeLabel(const char * LabelName, asmjit::Label & JumpLabel)
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{
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AddSymbol(stdstr_f("L%d", JumpLabel.id()).c_str(), LabelName);
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@ -44,6 +44,10 @@ public:
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void CompConstToVariable(void * Variable, const char * VariableName, uint32_t Const);
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void CompConstToX86reg(const asmjit::x86::Gp & Reg, uint32_t Const);
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void CompX86regToVariable(const asmjit::x86::Gp & Reg, void * Variable, const char * VariableName);
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void Fadd(const asmjit::x86::Mem & Mem);
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void Fdiv(const asmjit::x86::Mem & Mem);
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void Fmul(const asmjit::x86::Mem & Mem);
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void Fsub(const asmjit::x86::Mem & Mem);
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void JaeLabel(const char * LabelName, asmjit::Label & JumpLabel);
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void JaLabel(const char * LabelName, asmjit::Label & JumpLabel);
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void JbLabel(const char * LabelName, asmjit::Label & JumpLabel);
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