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Change some of the Reg Info functions to be get and setters

This commit is contained in:
zilmar 2012-11-03 12:18:08 +11:00
parent e761561074
commit 464c280fa6
7 changed files with 674 additions and 680 deletions
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172
Source/Project64/N64 System/Mips/Memory Virtual Mem.cpp
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@ -1320,9 +1320,9 @@ void CMipsMemoryVM::ResetMemoryStack ( void)
if (IsUnknown(MipsReg)) { if (IsUnknown(MipsReg)) {
MoveVariableToX86reg(&_GPR[MipsReg].UW[0],CRegName::GPR_Lo[MipsReg],Reg); MoveVariableToX86reg(&_GPR[MipsReg].UW[0],CRegName::GPR_Lo[MipsReg],Reg);
} else if (IsMapped(MipsReg)) { } else if (IsMapped(MipsReg)) {
MoveX86RegToX86Reg(MipsRegMapLo(MipsReg),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(MipsReg),Reg);
} else { } else {
MoveConstToX86reg(MipsRegLo(MipsReg),Reg); MoveConstToX86reg(GetMipsRegLo(MipsReg),Reg);
} }
} }
@ -2432,7 +2432,7 @@ void CMipsMemoryVM::Compile_LB (void)
if (IsConst(Opcode.base)) { if (IsConst(Opcode.base)) {
DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 3; DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 3;
Map_GPR_32bit(Opcode.rt,TRUE,0); Map_GPR_32bit(Opcode.rt,TRUE,0);
Compile_LB(MipsRegMapLo(Opcode.rt),Address,TRUE); Compile_LB(GetMipsRegMapLo(Opcode.rt),Address,TRUE);
return; return;
} }
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); } if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
@ -2440,7 +2440,7 @@ void CMipsMemoryVM::Compile_LB (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2456,12 +2456,12 @@ void CMipsMemoryVM::Compile_LB (void)
CompileReadTLBMiss(TempReg1,TempReg2); CompileReadTLBMiss(TempReg1,TempReg2);
XorConstToX86Reg(TempReg1,3); XorConstToX86Reg(TempReg1,3);
Map_GPR_32bit(Opcode.rt,TRUE,-1); Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveSxByteX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt)); MoveSxByteX86regPointerToX86reg(TempReg1, TempReg2,GetMipsRegMapLo(Opcode.rt));
} else { } else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF); AndConstToX86Reg(TempReg1,0x1FFFFFFF);
XorConstToX86Reg(TempReg1,3); XorConstToX86Reg(TempReg1,3);
Map_GPR_32bit(Opcode.rt,TRUE,-1); Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveSxN64MemToX86regByte(MipsRegMapLo(Opcode.rt), TempReg1); MoveSxN64MemToX86regByte(GetMipsRegMapLo(Opcode.rt), TempReg1);
} }
} }
@ -2477,7 +2477,7 @@ void CMipsMemoryVM::Compile_LBU (void)
if (IsConst(Opcode.base)) { if (IsConst(Opcode.base)) {
DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 3; DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 3;
Map_GPR_32bit(Opcode.rt,FALSE,0); Map_GPR_32bit(Opcode.rt,FALSE,0);
Compile_LB(MipsRegMapLo(Opcode.rt),Address,FALSE); Compile_LB(GetMipsRegMapLo(Opcode.rt),Address,FALSE);
return; return;
} }
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); } if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
@ -2485,7 +2485,7 @@ void CMipsMemoryVM::Compile_LBU (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2501,12 +2501,12 @@ void CMipsMemoryVM::Compile_LBU (void)
CompileReadTLBMiss(TempReg1,TempReg2); CompileReadTLBMiss(TempReg1,TempReg2);
XorConstToX86Reg(TempReg1,3); XorConstToX86Reg(TempReg1,3);
Map_GPR_32bit(Opcode.rt,FALSE,-1); Map_GPR_32bit(Opcode.rt,FALSE,-1);
MoveZxByteX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt)); MoveZxByteX86regPointerToX86reg(TempReg1, TempReg2,GetMipsRegMapLo(Opcode.rt));
} else { } else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF); AndConstToX86Reg(TempReg1,0x1FFFFFFF);
XorConstToX86Reg(TempReg1,3); XorConstToX86Reg(TempReg1,3);
Map_GPR_32bit(Opcode.rt,FALSE,-1); Map_GPR_32bit(Opcode.rt,FALSE,-1);
MoveZxN64MemToX86regByte(MipsRegMapLo(Opcode.rt), TempReg1); MoveZxN64MemToX86regByte(GetMipsRegMapLo(Opcode.rt), TempReg1);
} }
} }
@ -2522,7 +2522,7 @@ void CMipsMemoryVM::Compile_LH (void)
if (IsConst(Opcode.base)) { if (IsConst(Opcode.base)) {
DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 2; DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 2;
Map_GPR_32bit(Opcode.rt,TRUE,0); Map_GPR_32bit(Opcode.rt,TRUE,0);
Compile_LH(MipsRegMapLo(Opcode.rt),Address,TRUE); Compile_LH(GetMipsRegMapLo(Opcode.rt),Address,TRUE);
return; return;
} }
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); } if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
@ -2530,7 +2530,7 @@ void CMipsMemoryVM::Compile_LH (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2546,12 +2546,12 @@ void CMipsMemoryVM::Compile_LH (void)
CompileReadTLBMiss(TempReg1,TempReg2); CompileReadTLBMiss(TempReg1,TempReg2);
XorConstToX86Reg(TempReg1,2); XorConstToX86Reg(TempReg1,2);
Map_GPR_32bit(Opcode.rt,TRUE,-1); Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveSxHalfX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt)); MoveSxHalfX86regPointerToX86reg(TempReg1, TempReg2,GetMipsRegMapLo(Opcode.rt));
} else { } else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF); AndConstToX86Reg(TempReg1,0x1FFFFFFF);
XorConstToX86Reg(TempReg1,2); XorConstToX86Reg(TempReg1,2);
Map_GPR_32bit(Opcode.rt,TRUE,-1); Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveSxN64MemToX86regHalf(MipsRegMapLo(Opcode.rt), TempReg1); MoveSxN64MemToX86regHalf(GetMipsRegMapLo(Opcode.rt), TempReg1);
} }
} }
@ -2567,7 +2567,7 @@ void CMipsMemoryVM::Compile_LHU (void)
if (IsConst(Opcode.base)) { if (IsConst(Opcode.base)) {
DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 2; DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset) ^ 2;
Map_GPR_32bit(Opcode.rt,FALSE,0); Map_GPR_32bit(Opcode.rt,FALSE,0);
Compile_LH(MipsRegMapLo(Opcode.rt),Address,FALSE); Compile_LH(GetMipsRegMapLo(Opcode.rt),Address,FALSE);
return; return;
} }
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); } if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
@ -2575,7 +2575,7 @@ void CMipsMemoryVM::Compile_LHU (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2591,12 +2591,12 @@ void CMipsMemoryVM::Compile_LHU (void)
CompileReadTLBMiss(TempReg1,TempReg2); CompileReadTLBMiss(TempReg1,TempReg2);
XorConstToX86Reg(TempReg1,2); XorConstToX86Reg(TempReg1,2);
Map_GPR_32bit(Opcode.rt,FALSE,-1); Map_GPR_32bit(Opcode.rt,FALSE,-1);
MoveZxHalfX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt)); MoveZxHalfX86regPointerToX86reg(TempReg1, TempReg2,GetMipsRegMapLo(Opcode.rt));
} else { } else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF); AndConstToX86Reg(TempReg1,0x1FFFFFFF);
XorConstToX86Reg(TempReg1,2); XorConstToX86Reg(TempReg1,2);
Map_GPR_32bit(Opcode.rt,TRUE,-1); Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveZxN64MemToX86regHalf(MipsRegMapLo(Opcode.rt), TempReg1); MoveZxN64MemToX86regHalf(GetMipsRegMapLo(Opcode.rt), TempReg1);
} }
} }
@ -2614,24 +2614,24 @@ void CMipsMemoryVM::Compile_LW (void)
Map_GPR_32bit(Opcode.rt,TRUE,-1); Map_GPR_32bit(Opcode.rt,TRUE,-1);
TempReg1 = Map_MemoryStack(x86_Any,true); TempReg1 = Map_MemoryStack(x86_Any,true);
sprintf(String,"%Xh",(short)Opcode.offset); sprintf(String,"%Xh",(short)Opcode.offset);
MoveVariableDispToX86Reg((void *)((DWORD)(short)Opcode.offset),String,MipsRegMapLo(Opcode.rt),TempReg1,1); MoveVariableDispToX86Reg((void *)((DWORD)(short)Opcode.offset),String,GetMipsRegMapLo(Opcode.rt),TempReg1,1);
} else { } else {
if (IsConst(Opcode.base)) { if (IsConst(Opcode.base)) {
DWORD Address = cMipsRegLo(Opcode.base) + (short)Opcode.offset; DWORD Address = cMipsRegLo(Opcode.base) + (short)Opcode.offset;
Map_GPR_32bit(Opcode.rt,TRUE,-1); Map_GPR_32bit(Opcode.rt,TRUE,-1);
Compile_LW(MipsRegMapLo(Opcode.rt),Address); Compile_LW(GetMipsRegMapLo(Opcode.rt),Address);
} else { } else {
if (bUseTlb()) { if (bUseTlb()) {
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); } if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
if (IsMapped(Opcode.base) && Opcode.offset == 0) { if (IsMapped(Opcode.base) && Opcode.offset == 0) {
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
TempReg1 = MipsRegMapLo(Opcode.base); TempReg1 = GetMipsRegMapLo(Opcode.base);
} else { } else {
if (IsMapped(Opcode.base)) { if (IsMapped(Opcode.base)) {
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2646,22 +2646,22 @@ void CMipsMemoryVM::Compile_LW (void)
MoveVariableDispToX86Reg(m_TLB_ReadMap,"m_TLB_ReadMap",TempReg2,TempReg2,4); MoveVariableDispToX86Reg(m_TLB_ReadMap,"m_TLB_ReadMap",TempReg2,TempReg2,4);
CompileReadTLBMiss(TempReg1,TempReg2); CompileReadTLBMiss(TempReg1,TempReg2);
Map_GPR_32bit(Opcode.rt,TRUE,-1); Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt)); MoveX86regPointerToX86reg(TempReg1, TempReg2,GetMipsRegMapLo(Opcode.rt));
} else { } else {
if (IsMapped(Opcode.base)) { if (IsMapped(Opcode.base)) {
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
Map_GPR_32bit(Opcode.rt,TRUE,-1); Map_GPR_32bit(Opcode.rt,TRUE,-1);
LeaSourceAndOffset(MipsRegMapLo(Opcode.rt),MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(GetMipsRegMapLo(Opcode.rt),GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.base); Map_GPR_32bit(Opcode.rt,TRUE,Opcode.base);
} }
} else { } else {
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.base); Map_GPR_32bit(Opcode.rt,TRUE,Opcode.base);
AddConstToX86Reg(MipsRegMapLo(Opcode.rt),(short)Opcode.immediate); AddConstToX86Reg(GetMipsRegMapLo(Opcode.rt),(short)Opcode.immediate);
} }
AndConstToX86Reg(MipsRegMapLo(Opcode.rt),0x1FFFFFFF); AndConstToX86Reg(GetMipsRegMapLo(Opcode.rt),0x1FFFFFFF);
MoveN64MemToX86reg(MipsRegMapLo(Opcode.rt),MipsRegMapLo(Opcode.rt)); MoveN64MemToX86reg(GetMipsRegMapLo(Opcode.rt),GetMipsRegMapLo(Opcode.rt));
} }
} }
} }
@ -2706,7 +2706,7 @@ void CMipsMemoryVM::Compile_LWC1 (void)
if (IsMapped(Opcode.base) && Opcode.offset == 0) { if (IsMapped(Opcode.base) && Opcode.offset == 0) {
if (bUseTlb()) { if (bUseTlb()) {
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
TempReg1 = MipsRegMapLo(Opcode.base); TempReg1 = GetMipsRegMapLo(Opcode.base);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2715,7 +2715,7 @@ void CMipsMemoryVM::Compile_LWC1 (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2767,9 +2767,9 @@ void CMipsMemoryVM::Compile_LWL (void)
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt); Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt);
x86Reg Value = Map_TempReg(x86_Any,-1,FALSE); x86Reg Value = Map_TempReg(x86_Any,-1,FALSE);
Compile_LW(Value,(Address & ~3)); Compile_LW(Value,(Address & ~3));
AndConstToX86Reg(MipsRegMapLo(Opcode.rt),LWL_MASK[Offset]); AndConstToX86Reg(GetMipsRegMapLo(Opcode.rt),LWL_MASK[Offset]);
ShiftLeftSignImmed(Value,(BYTE)LWL_SHIFT[Offset]); ShiftLeftSignImmed(Value,(BYTE)LWL_SHIFT[Offset]);
AddX86RegToX86Reg(MipsRegMapLo(Opcode.rt),Value); AddX86RegToX86Reg(GetMipsRegMapLo(Opcode.rt),Value);
return; return;
} }
@ -2779,7 +2779,7 @@ void CMipsMemoryVM::Compile_LWL (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2802,7 +2802,7 @@ void CMipsMemoryVM::Compile_LWL (void)
AndConstToX86Reg(TempReg1,(DWORD)~3); AndConstToX86Reg(TempReg1,(DWORD)~3);
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt); Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt);
AndVariableDispToX86Reg((void *)LWL_MASK,"LWL_MASK",MipsRegMapLo(Opcode.rt),OffsetReg,Multip_x4); AndVariableDispToX86Reg((void *)LWL_MASK,"LWL_MASK",GetMipsRegMapLo(Opcode.rt),OffsetReg,Multip_x4);
MoveVariableDispToX86Reg((void *)LWL_SHIFT,"LWL_SHIFT",shift,OffsetReg,4); MoveVariableDispToX86Reg((void *)LWL_SHIFT,"LWL_SHIFT",shift,OffsetReg,4);
if (bUseTlb()) { if (bUseTlb()) {
MoveX86regPointerToX86reg(TempReg1, TempReg2,TempReg1); MoveX86regPointerToX86reg(TempReg1, TempReg2,TempReg1);
@ -2811,7 +2811,7 @@ void CMipsMemoryVM::Compile_LWL (void)
MoveN64MemToX86reg(TempReg1,TempReg1); MoveN64MemToX86reg(TempReg1,TempReg1);
} }
ShiftLeftSign(TempReg1); ShiftLeftSign(TempReg1);
AddX86RegToX86Reg(MipsRegMapLo(Opcode.rt),TempReg1); AddX86RegToX86Reg(GetMipsRegMapLo(Opcode.rt),TempReg1);
} }
void CMipsMemoryVM::Compile_LWR (void) void CMipsMemoryVM::Compile_LWR (void)
@ -2830,9 +2830,9 @@ void CMipsMemoryVM::Compile_LWR (void)
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt); Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt);
x86Reg Value = Map_TempReg(x86_Any,-1,FALSE); x86Reg Value = Map_TempReg(x86_Any,-1,FALSE);
Compile_LW(Value,(Address & ~3)); Compile_LW(Value,(Address & ~3));
AndConstToX86Reg(MipsRegMapLo(Opcode.rt),LWR_MASK[Offset]); AndConstToX86Reg(GetMipsRegMapLo(Opcode.rt),LWR_MASK[Offset]);
ShiftRightUnsignImmed(Value,(BYTE)LWR_SHIFT[Offset]); ShiftRightUnsignImmed(Value,(BYTE)LWR_SHIFT[Offset]);
AddX86RegToX86Reg(MipsRegMapLo(Opcode.rt),Value); AddX86RegToX86Reg(GetMipsRegMapLo(Opcode.rt),Value);
return; return;
} }
@ -2842,7 +2842,7 @@ void CMipsMemoryVM::Compile_LWR (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2866,7 +2866,7 @@ void CMipsMemoryVM::Compile_LWR (void)
AndConstToX86Reg(TempReg1,(DWORD)~3); AndConstToX86Reg(TempReg1,(DWORD)~3);
Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt); Map_GPR_32bit(Opcode.rt,TRUE,Opcode.rt);
AndVariableDispToX86Reg((void *)LWR_MASK,"LWR_MASK",MipsRegMapLo(Opcode.rt),OffsetReg,Multip_x4); AndVariableDispToX86Reg((void *)LWR_MASK,"LWR_MASK",GetMipsRegMapLo(Opcode.rt),OffsetReg,Multip_x4);
MoveVariableDispToX86Reg((void *)LWR_SHIFT,"LWR_SHIFT",shift,OffsetReg,4); MoveVariableDispToX86Reg((void *)LWR_SHIFT,"LWR_SHIFT",shift,OffsetReg,4);
if (bUseTlb()) { if (bUseTlb()) {
MoveX86regPointerToX86reg(TempReg1, TempReg2,TempReg1); MoveX86regPointerToX86reg(TempReg1, TempReg2,TempReg1);
@ -2875,7 +2875,7 @@ void CMipsMemoryVM::Compile_LWR (void)
MoveN64MemToX86reg(TempReg1,TempReg1); MoveN64MemToX86reg(TempReg1,TempReg1);
} }
ShiftRightUnsign(TempReg1); ShiftRightUnsign(TempReg1);
AddX86RegToX86Reg(MipsRegMapLo(Opcode.rt),TempReg1); AddX86RegToX86Reg(GetMipsRegMapLo(Opcode.rt),TempReg1);
} }
void CMipsMemoryVM::Compile_LWU (void) void CMipsMemoryVM::Compile_LWU (void)
@ -2890,7 +2890,7 @@ void CMipsMemoryVM::Compile_LWU (void)
if (IsConst(Opcode.base)) { if (IsConst(Opcode.base)) {
DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset); DWORD Address = (cMipsRegLo(Opcode.base) + (short)Opcode.offset);
Map_GPR_32bit(Opcode.rt,FALSE,0); Map_GPR_32bit(Opcode.rt,FALSE,0);
Compile_LW(MipsRegMapLo(Opcode.rt),Address); Compile_LW(GetMipsRegMapLo(Opcode.rt),Address);
return; return;
} }
if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); } if (IsMapped(Opcode.rt)) { ProtectGPR(Opcode.rt); }
@ -2898,7 +2898,7 @@ void CMipsMemoryVM::Compile_LWU (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2913,11 +2913,11 @@ void CMipsMemoryVM::Compile_LWU (void)
MoveVariableDispToX86Reg(m_TLB_ReadMap,"m_TLB_ReadMap",TempReg2,TempReg2,4); MoveVariableDispToX86Reg(m_TLB_ReadMap,"m_TLB_ReadMap",TempReg2,TempReg2,4);
CompileReadTLBMiss(TempReg1,TempReg2); CompileReadTLBMiss(TempReg1,TempReg2);
Map_GPR_32bit(Opcode.rt,FALSE,-1); Map_GPR_32bit(Opcode.rt,FALSE,-1);
MoveZxHalfX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt)); MoveZxHalfX86regPointerToX86reg(TempReg1, TempReg2,GetMipsRegMapLo(Opcode.rt));
} else { } else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF); AndConstToX86Reg(TempReg1,0x1FFFFFFF);
Map_GPR_32bit(Opcode.rt,TRUE,-1); Map_GPR_32bit(Opcode.rt,TRUE,-1);
MoveZxN64MemToX86regHalf(MipsRegMapLo(Opcode.rt), TempReg1); MoveZxN64MemToX86regHalf(GetMipsRegMapLo(Opcode.rt), TempReg1);
} }
} }
@ -2933,8 +2933,8 @@ void CMipsMemoryVM::Compile_LD (void)
if (IsConst(Opcode.base)) { if (IsConst(Opcode.base)) {
DWORD Address = cMipsRegLo(Opcode.base) + (short)Opcode.offset; DWORD Address = cMipsRegLo(Opcode.base) + (short)Opcode.offset;
Map_GPR_64bit(Opcode.rt,-1); Map_GPR_64bit(Opcode.rt,-1);
Compile_LW(MipsRegMapHi(Opcode.rt),Address); Compile_LW(GetMipsRegMapHi(Opcode.rt),Address);
Compile_LW(MipsRegMapLo(Opcode.rt),Address + 4); Compile_LW(GetMipsRegMapLo(Opcode.rt),Address + 4);
if (bFastSP() && Opcode.rt == 29) if (bFastSP() && Opcode.rt == 29)
{ {
ResetMemoryStack(); ResetMemoryStack();
@ -2945,7 +2945,7 @@ void CMipsMemoryVM::Compile_LD (void)
if (IsMapped(Opcode.base) && Opcode.offset == 0) { if (IsMapped(Opcode.base) && Opcode.offset == 0) {
if (bUseTlb()) { if (bUseTlb()) {
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
TempReg1 = MipsRegMapLo(Opcode.base); TempReg1 = GetMipsRegMapLo(Opcode.base);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2954,7 +2954,7 @@ void CMipsMemoryVM::Compile_LD (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -2972,13 +2972,13 @@ void CMipsMemoryVM::Compile_LD (void)
//0041C522 85 C0 test eax,eax //0041C522 85 C0 test eax,eax
//0041C524 75 01 jne 0041C527 //0041C524 75 01 jne 0041C527
Map_GPR_64bit(Opcode.rt,-1); Map_GPR_64bit(Opcode.rt,-1);
MoveX86regPointerToX86reg(TempReg1, TempReg2,MipsRegMapHi(Opcode.rt)); MoveX86regPointerToX86reg(TempReg1, TempReg2,GetMipsRegMapHi(Opcode.rt));
MoveX86regPointerToX86regDisp8(TempReg1, TempReg2,MipsRegMapLo(Opcode.rt),4); MoveX86regPointerToX86regDisp8(TempReg1, TempReg2,GetMipsRegMapLo(Opcode.rt),4);
} else { } else {
AndConstToX86Reg(TempReg1,0x1FFFFFFF); AndConstToX86Reg(TempReg1,0x1FFFFFFF);
Map_GPR_64bit(Opcode.rt,-1); Map_GPR_64bit(Opcode.rt,-1);
MoveN64MemToX86reg(MipsRegMapHi(Opcode.rt),TempReg1); MoveN64MemToX86reg(GetMipsRegMapHi(Opcode.rt),TempReg1);
MoveN64MemDispToX86reg(MipsRegMapLo(Opcode.rt),TempReg1,4); MoveN64MemDispToX86reg(GetMipsRegMapLo(Opcode.rt),TempReg1,4);
} }
if (bFastSP() && Opcode.rt == 29) if (bFastSP() && Opcode.rt == 29)
{ {
@ -3018,7 +3018,7 @@ void CMipsMemoryVM::Compile_LDC1 (void)
if (IsMapped(Opcode.base) && Opcode.offset == 0) { if (IsMapped(Opcode.base) && Opcode.offset == 0) {
if (bUseTlb()) { if (bUseTlb()) {
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
TempReg1 = MipsRegMapLo(Opcode.base); TempReg1 = GetMipsRegMapLo(Opcode.base);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -3027,7 +3027,7 @@ void CMipsMemoryVM::Compile_LDC1 (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -3117,8 +3117,8 @@ void CMipsMemoryVM::Compile_SB (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
Compile_SB_Const((BYTE)cMipsRegLo(Opcode.rt), Address); Compile_SB_Const((BYTE)cMipsRegLo(Opcode.rt), Address);
} else if (IsMapped(Opcode.rt) && Is8BitReg(MipsRegMapLo(Opcode.rt))) { } else if (IsMapped(Opcode.rt) && Is8BitReg(GetMipsRegMapLo(Opcode.rt))) {
Compile_SB_Register(MipsRegMapLo(Opcode.rt), Address); Compile_SB_Register(GetMipsRegMapLo(Opcode.rt), Address);
} else { } else {
Compile_SB_Register(Map_TempReg(x86_Any8Bit,Opcode.rt,FALSE), Address); Compile_SB_Register(Map_TempReg(x86_Any8Bit,Opcode.rt,FALSE), Address);
} }
@ -3129,7 +3129,7 @@ void CMipsMemoryVM::Compile_SB (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -3151,8 +3151,8 @@ void CMipsMemoryVM::Compile_SB (void)
XorConstToX86Reg(TempReg1,3); XorConstToX86Reg(TempReg1,3);
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
MoveConstByteToX86regPointer((BYTE)cMipsRegLo(Opcode.rt),TempReg1, TempReg2); MoveConstByteToX86regPointer((BYTE)cMipsRegLo(Opcode.rt),TempReg1, TempReg2);
} else if (IsMapped(Opcode.rt) && Is8BitReg(MipsRegMapLo(Opcode.rt))) { } else if (IsMapped(Opcode.rt) && Is8BitReg(GetMipsRegMapLo(Opcode.rt))) {
MoveX86regByteToX86regPointer(MipsRegMapLo(Opcode.rt),TempReg1, TempReg2); MoveX86regByteToX86regPointer(GetMipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
} else { } else {
UnProtectGPR(Opcode.rt); UnProtectGPR(Opcode.rt);
MoveX86regByteToX86regPointer(Map_TempReg(x86_Any8Bit,Opcode.rt,FALSE),TempReg1, TempReg2); MoveX86regByteToX86regPointer(Map_TempReg(x86_Any8Bit,Opcode.rt,FALSE),TempReg1, TempReg2);
@ -3162,8 +3162,8 @@ void CMipsMemoryVM::Compile_SB (void)
XorConstToX86Reg(TempReg1,3); XorConstToX86Reg(TempReg1,3);
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
MoveConstByteToN64Mem((BYTE)cMipsRegLo(Opcode.rt),TempReg1); MoveConstByteToN64Mem((BYTE)cMipsRegLo(Opcode.rt),TempReg1);
} else if (IsMapped(Opcode.rt) && Is8BitReg(MipsRegMapLo(Opcode.rt))) { } else if (IsMapped(Opcode.rt) && Is8BitReg(GetMipsRegMapLo(Opcode.rt))) {
MoveX86regByteToN64Mem(MipsRegMapLo(Opcode.rt),TempReg1); MoveX86regByteToN64Mem(GetMipsRegMapLo(Opcode.rt),TempReg1);
} else { } else {
UnProtectGPR(Opcode.rt); UnProtectGPR(Opcode.rt);
MoveX86regByteToN64Mem(Map_TempReg(x86_Any8Bit,Opcode.rt,FALSE),TempReg1); MoveX86regByteToN64Mem(Map_TempReg(x86_Any8Bit,Opcode.rt,FALSE),TempReg1);
@ -3184,7 +3184,7 @@ void CMipsMemoryVM::Compile_SH (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
Compile_SH_Const((WORD)cMipsRegLo(Opcode.rt), Address); Compile_SH_Const((WORD)cMipsRegLo(Opcode.rt), Address);
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
Compile_SH_Register(MipsRegMapLo(Opcode.rt), Address); Compile_SH_Register(GetMipsRegMapLo(Opcode.rt), Address);
} else { } else {
Compile_SH_Register(Map_TempReg(x86_Any,Opcode.rt,FALSE), Address); Compile_SH_Register(Map_TempReg(x86_Any,Opcode.rt,FALSE), Address);
} }
@ -3195,7 +3195,7 @@ void CMipsMemoryVM::Compile_SH (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -3217,7 +3217,7 @@ void CMipsMemoryVM::Compile_SH (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
MoveConstHalfToX86regPointer((WORD)cMipsRegLo(Opcode.rt),TempReg1, TempReg2); MoveConstHalfToX86regPointer((WORD)cMipsRegLo(Opcode.rt),TempReg1, TempReg2);
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
MoveX86regHalfToX86regPointer(MipsRegMapLo(Opcode.rt),TempReg1, TempReg2); MoveX86regHalfToX86regPointer(GetMipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
} else { } else {
MoveX86regHalfToX86regPointer(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1, TempReg2); MoveX86regHalfToX86regPointer(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1, TempReg2);
} }
@ -3227,7 +3227,7 @@ void CMipsMemoryVM::Compile_SH (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
MoveConstHalfToN64Mem((WORD)cMipsRegLo(Opcode.rt),TempReg1); MoveConstHalfToN64Mem((WORD)cMipsRegLo(Opcode.rt),TempReg1);
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
MoveX86regHalfToN64Mem(MipsRegMapLo(Opcode.rt),TempReg1); MoveX86regHalfToN64Mem(GetMipsRegMapLo(Opcode.rt),TempReg1);
} else { } else {
MoveX86regHalfToN64Mem(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1); MoveX86regHalfToN64Mem(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1);
} }
@ -3247,7 +3247,7 @@ void CMipsMemoryVM::Compile_SW (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
MoveConstToMemoryDisp (cMipsRegLo(Opcode.rt),TempReg1, (DWORD)((short)Opcode.offset)); MoveConstToMemoryDisp (cMipsRegLo(Opcode.rt),TempReg1, (DWORD)((short)Opcode.offset));
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
MoveX86regToMemory(MipsRegMapLo(Opcode.rt),TempReg1,(DWORD)((short)Opcode.offset)); MoveX86regToMemory(GetMipsRegMapLo(Opcode.rt),TempReg1,(DWORD)((short)Opcode.offset));
} else { } else {
TempReg2 = Map_TempReg(x86_Any,Opcode.rt,FALSE); TempReg2 = Map_TempReg(x86_Any,Opcode.rt,FALSE);
MoveX86regToMemory(TempReg2,TempReg1,(DWORD)((short)Opcode.offset)); MoveX86regToMemory(TempReg2,TempReg1,(DWORD)((short)Opcode.offset));
@ -3259,7 +3259,7 @@ void CMipsMemoryVM::Compile_SW (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
Compile_SW_Const(cMipsRegLo(Opcode.rt), Address); Compile_SW_Const(cMipsRegLo(Opcode.rt), Address);
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
Compile_SW_Register(MipsRegMapLo(Opcode.rt), Address); Compile_SW_Register(GetMipsRegMapLo(Opcode.rt), Address);
} else { } else {
Compile_SW_Register(Map_TempReg(x86_Any,Opcode.rt,FALSE), Address); Compile_SW_Register(Map_TempReg(x86_Any,Opcode.rt,FALSE), Address);
} }
@ -3276,7 +3276,7 @@ void CMipsMemoryVM::Compile_SW (void)
} }
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -3298,7 +3298,7 @@ void CMipsMemoryVM::Compile_SW (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
MoveConstToX86regPointer(cMipsRegLo(Opcode.rt),TempReg1, TempReg2); MoveConstToX86regPointer(cMipsRegLo(Opcode.rt),TempReg1, TempReg2);
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
MoveX86regToX86regPointer(MipsRegMapLo(Opcode.rt),TempReg1, TempReg2); MoveX86regToX86regPointer(GetMipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
} else { } else {
MoveX86regToX86regPointer(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1, TempReg2); MoveX86regToX86regPointer(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1, TempReg2);
} }
@ -3307,7 +3307,7 @@ void CMipsMemoryVM::Compile_SW (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
MoveConstToN64Mem(cMipsRegLo(Opcode.rt),TempReg1); MoveConstToN64Mem(cMipsRegLo(Opcode.rt),TempReg1);
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
MoveX86regToN64Mem(MipsRegMapLo(Opcode.rt),TempReg1); MoveX86regToN64Mem(GetMipsRegMapLo(Opcode.rt),TempReg1);
} else { } else {
MoveX86regToN64Mem(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1); MoveX86regToN64Mem(Map_TempReg(x86_Any,Opcode.rt,FALSE),TempReg1);
} }
@ -3341,7 +3341,7 @@ void CMipsMemoryVM::Compile_SWC1 (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -3410,7 +3410,7 @@ void CMipsMemoryVM::Compile_SWL (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -3449,7 +3449,7 @@ void CMipsMemoryVM::Compile_SWL (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
MoveConstToX86reg(cMipsRegLo(Opcode.rt),OffsetReg); MoveConstToX86reg(cMipsRegLo(Opcode.rt),OffsetReg);
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
MoveX86RegToX86Reg(MipsRegMapLo(Opcode.rt),OffsetReg); MoveX86RegToX86Reg(GetMipsRegMapLo(Opcode.rt),OffsetReg);
} else { } else {
MoveVariableToX86reg(&_GPR[Opcode.rt].UW[0],CRegName::GPR_Lo[Opcode.rt],OffsetReg); MoveVariableToX86reg(&_GPR[Opcode.rt].UW[0],CRegName::GPR_Lo[Opcode.rt],OffsetReg);
} }
@ -3494,7 +3494,7 @@ void CMipsMemoryVM::Compile_SWR (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -3533,7 +3533,7 @@ void CMipsMemoryVM::Compile_SWR (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
MoveConstToX86reg(cMipsRegLo(Opcode.rt),OffsetReg); MoveConstToX86reg(cMipsRegLo(Opcode.rt),OffsetReg);
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
MoveX86RegToX86Reg(MipsRegMapLo(Opcode.rt),OffsetReg); MoveX86RegToX86Reg(GetMipsRegMapLo(Opcode.rt),OffsetReg);
} else { } else {
MoveVariableToX86reg(&_GPR[Opcode.rt].UW[0],CRegName::GPR_Lo[Opcode.rt],OffsetReg); MoveVariableToX86reg(&_GPR[Opcode.rt].UW[0],CRegName::GPR_Lo[Opcode.rt],OffsetReg);
} }
@ -3615,11 +3615,11 @@ void CMipsMemoryVM::Compile_SD (void)
DWORD Address = cMipsRegLo(Opcode.base) + (short)Opcode.offset; DWORD Address = cMipsRegLo(Opcode.base) + (short)Opcode.offset;
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
Compile_SW_Const(Is64Bit(Opcode.rt) ? MipsRegHi(Opcode.rt) : (MipsRegLo_S(Opcode.rt) >> 31), Address); Compile_SW_Const(Is64Bit(Opcode.rt) ? GetMipsRegHi(Opcode.rt) : (GetMipsRegLo_S(Opcode.rt) >> 31), Address);
Compile_SW_Const(cMipsRegLo(Opcode.rt), Address + 4); Compile_SW_Const(cMipsRegLo(Opcode.rt), Address + 4);
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
Compile_SW_Register(Is64Bit(Opcode.rt) ? MipsRegMapHi(Opcode.rt) : Map_TempReg(x86_Any,Opcode.rt,TRUE), Address); Compile_SW_Register(Is64Bit(Opcode.rt) ? GetMipsRegMapHi(Opcode.rt) : Map_TempReg(x86_Any,Opcode.rt,TRUE), Address);
Compile_SW_Register(MipsRegMapLo(Opcode.rt), Address + 4); Compile_SW_Register(GetMipsRegMapLo(Opcode.rt), Address + 4);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.rt,TRUE); TempReg1 = Map_TempReg(x86_Any,Opcode.rt,TRUE);
Compile_SW_Register(TempReg1, Address); Compile_SW_Register(TempReg1, Address);
@ -3631,7 +3631,7 @@ void CMipsMemoryVM::Compile_SD (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }
@ -3654,20 +3654,20 @@ void CMipsMemoryVM::Compile_SD (void)
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
if (Is64Bit(Opcode.rt)) { if (Is64Bit(Opcode.rt)) {
MoveConstToX86regPointer(MipsRegHi(Opcode.rt),TempReg1, TempReg2); MoveConstToX86regPointer(GetMipsRegHi(Opcode.rt),TempReg1, TempReg2);
} else { } else {
MoveConstToX86regPointer((MipsRegLo_S(Opcode.rt) >> 31),TempReg1, TempReg2); MoveConstToX86regPointer((GetMipsRegLo_S(Opcode.rt) >> 31),TempReg1, TempReg2);
} }
AddConstToX86Reg(TempReg1,4); AddConstToX86Reg(TempReg1,4);
MoveConstToX86regPointer(cMipsRegLo(Opcode.rt),TempReg1, TempReg2); MoveConstToX86regPointer(cMipsRegLo(Opcode.rt),TempReg1, TempReg2);
} else if (IsMapped(Opcode.rt)) { } else if (IsMapped(Opcode.rt)) {
if (Is64Bit(Opcode.rt)) { if (Is64Bit(Opcode.rt)) {
MoveX86regToX86regPointer(MipsRegMapHi(Opcode.rt),TempReg1, TempReg2); MoveX86regToX86regPointer(GetMipsRegMapHi(Opcode.rt),TempReg1, TempReg2);
} else { } else {
MoveX86regToX86regPointer(Map_TempReg(x86_Any,Opcode.rt,TRUE),TempReg1, TempReg2); MoveX86regToX86regPointer(Map_TempReg(x86_Any,Opcode.rt,TRUE),TempReg1, TempReg2);
} }
AddConstToX86Reg(TempReg1,4); AddConstToX86Reg(TempReg1,4);
MoveX86regToX86regPointer(MipsRegMapLo(Opcode.rt),TempReg1, TempReg2); MoveX86regToX86regPointer(GetMipsRegMapLo(Opcode.rt),TempReg1, TempReg2);
} else { } else {
x86Reg Reg = Map_TempReg(x86_Any,Opcode.rt,TRUE); x86Reg Reg = Map_TempReg(x86_Any,Opcode.rt,TRUE);
MoveX86regToX86regPointer(Reg,TempReg1, TempReg2); MoveX86regToX86regPointer(Reg,TempReg1, TempReg2);
@ -3678,7 +3678,7 @@ void CMipsMemoryVM::Compile_SD (void)
AndConstToX86Reg(TempReg1,0x1FFFFFFF); AndConstToX86Reg(TempReg1,0x1FFFFFFF);
if (IsConst(Opcode.rt)) { if (IsConst(Opcode.rt)) {
if (Is64Bit(Opcode.rt)) { if (Is64Bit(Opcode.rt)) {
MoveConstToN64Mem(MipsRegHi(Opcode.rt),TempReg1); MoveConstToN64Mem(GetMipsRegHi(Opcode.rt),TempReg1);
} else if (IsSigned(Opcode.rt)) { } else if (IsSigned(Opcode.rt)) {
MoveConstToN64Mem((cMipsRegLo_S(Opcode.rt) >> 31),TempReg1); MoveConstToN64Mem((cMipsRegLo_S(Opcode.rt) >> 31),TempReg1);
} else { } else {
@ -3687,13 +3687,13 @@ void CMipsMemoryVM::Compile_SD (void)
MoveConstToN64MemDisp(cMipsRegLo(Opcode.rt),TempReg1,4); MoveConstToN64MemDisp(cMipsRegLo(Opcode.rt),TempReg1,4);
} else if (IsKnown(Opcode.rt) && IsMapped(Opcode.rt)) { } else if (IsKnown(Opcode.rt) && IsMapped(Opcode.rt)) {
if (Is64Bit(Opcode.rt)) { if (Is64Bit(Opcode.rt)) {
MoveX86regToN64Mem(MipsRegMapHi(Opcode.rt),TempReg1); MoveX86regToN64Mem(GetMipsRegMapHi(Opcode.rt),TempReg1);
} else if (IsSigned(Opcode.rt)) { } else if (IsSigned(Opcode.rt)) {
MoveX86regToN64Mem(Map_TempReg(x86_Any,Opcode.rt,TRUE), TempReg1); MoveX86regToN64Mem(Map_TempReg(x86_Any,Opcode.rt,TRUE), TempReg1);
} else { } else {
MoveConstToN64Mem(0,TempReg1); MoveConstToN64Mem(0,TempReg1);
} }
MoveX86regToN64MemDisp(MipsRegMapLo(Opcode.rt),TempReg1, 4); MoveX86regToN64MemDisp(GetMipsRegMapLo(Opcode.rt),TempReg1, 4);
} else { } else {
x86Reg Reg; x86Reg Reg;
MoveX86regToN64Mem(Reg = Map_TempReg(x86_Any,Opcode.rt,TRUE), TempReg1); MoveX86regToN64Mem(Reg = Map_TempReg(x86_Any,Opcode.rt,TRUE), TempReg1);
@ -3733,7 +3733,7 @@ void CMipsMemoryVM::Compile_SDC1 (void)
ProtectGPR(Opcode.base); ProtectGPR(Opcode.base);
if (Opcode.offset != 0) { if (Opcode.offset != 0) {
TempReg1 = Map_TempReg(x86_Any,-1,FALSE); TempReg1 = Map_TempReg(x86_Any,-1,FALSE);
LeaSourceAndOffset(TempReg1,MipsRegMapLo(Opcode.base),(short)Opcode.offset); LeaSourceAndOffset(TempReg1,GetMipsRegMapLo(Opcode.base),(short)Opcode.offset);
} else { } else {
TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE); TempReg1 = Map_TempReg(x86_Any,Opcode.base,FALSE);
} }

92
Source/Project64/N64 System/Recompiler/Code Section.cpp
View File

@ -654,15 +654,15 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
switch (MipsRegState(i)) { switch (MipsRegState(i)) {
case CRegInfo::STATE_UNKNOWN: continue; case CRegInfo::STATE_UNKNOWN: continue;
case CRegInfo::STATE_MAPPED_64: case CRegInfo::STATE_MAPPED_64:
if (MipsRegMapHi(i) == SyncTo.MipsRegMapHi(i) && if (GetMipsRegMapHi(i) == SyncTo.GetMipsRegMapHi(i) &&
MipsRegMapLo(i) == SyncTo.MipsRegMapLo(i)) GetMipsRegMapLo(i) == SyncTo.GetMipsRegMapLo(i))
{ {
continue; continue;
} }
break; break;
case CRegInfo::STATE_MAPPED_32_ZERO: case CRegInfo::STATE_MAPPED_32_ZERO:
case CRegInfo::STATE_MAPPED_32_SIGN: case CRegInfo::STATE_MAPPED_32_SIGN:
if (MipsRegMapLo(i) == SyncTo.MipsRegMapLo(i)) { if (GetMipsRegMapLo(i) == SyncTo.GetMipsRegMapLo(i)) {
continue; continue;
} }
break; break;
@ -673,9 +673,9 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
} }
continue; continue;
case CRegInfo::STATE_CONST_32: case CRegInfo::STATE_CONST_32:
if (MipsRegLo(i) != SyncTo.cMipsRegLo(i)) if (GetMipsRegLo(i) != SyncTo.cMipsRegLo(i))
{ {
CPU_Message("Value of const is different Reg %d (%s) Value: 0x%08X to 0x%08X",i,CRegName::GPR[i],MipsRegLo(i),SyncTo.cMipsRegLo(i)); CPU_Message("Value of const is different Reg %d (%s) Value: 0x%08X to 0x%08X",i,CRegName::GPR[i],GetMipsRegLo(i),SyncTo.cMipsRegLo(i));
_Notify->BreakPoint(__FILE__,__LINE__); _Notify->BreakPoint(__FILE__,__LINE__);
} }
continue; continue;
@ -690,8 +690,8 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
case CRegInfo::STATE_UNKNOWN: UnMap_GPR(i,true); break; case CRegInfo::STATE_UNKNOWN: UnMap_GPR(i,true); break;
case CRegInfo::STATE_MAPPED_64: case CRegInfo::STATE_MAPPED_64:
{ {
x86Reg Reg = SyncTo.MipsRegMapLo(i); x86Reg Reg = SyncTo.GetMipsRegMapLo(i);
x86Reg x86RegHi = SyncTo.MipsRegMapHi(i); x86Reg x86RegHi = SyncTo.GetMipsRegMapHi(i);
UnMap_X86reg(Reg); UnMap_X86reg(Reg);
UnMap_X86reg(x86RegHi); UnMap_X86reg(x86RegHi);
switch (MipsRegState(i)) { switch (MipsRegState(i)) {
@ -700,29 +700,29 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
MoveVariableToX86reg(&_GPR[i].UW[1],CRegName::GPR_Hi[i],x86RegHi); MoveVariableToX86reg(&_GPR[i].UW[1],CRegName::GPR_Hi[i],x86RegHi);
break; break;
case CRegInfo::STATE_MAPPED_64: case CRegInfo::STATE_MAPPED_64:
MoveX86RegToX86Reg(MipsRegMapLo(i),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(i),Reg);
m_RegWorkingSet.SetX86Mapped(MipsRegMapLo(i),CRegInfo::NotMapped); m_RegWorkingSet.SetX86Mapped(GetMipsRegMapLo(i),CRegInfo::NotMapped);
MoveX86RegToX86Reg(MipsRegMapHi(i),x86RegHi); MoveX86RegToX86Reg(GetMipsRegMapHi(i),x86RegHi);
m_RegWorkingSet.SetX86Mapped(MipsRegMapHi(i),CRegInfo::NotMapped); m_RegWorkingSet.SetX86Mapped(GetMipsRegMapHi(i),CRegInfo::NotMapped);
break; break;
case CRegInfo::STATE_MAPPED_32_SIGN: case CRegInfo::STATE_MAPPED_32_SIGN:
MoveX86RegToX86Reg(MipsRegMapLo(i),x86RegHi); MoveX86RegToX86Reg(GetMipsRegMapLo(i),x86RegHi);
ShiftRightSignImmed(x86RegHi,31); ShiftRightSignImmed(x86RegHi,31);
MoveX86RegToX86Reg(MipsRegMapLo(i),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(i),Reg);
m_RegWorkingSet.SetX86Mapped(MipsRegMapLo(i),CRegInfo::NotMapped); m_RegWorkingSet.SetX86Mapped(GetMipsRegMapLo(i),CRegInfo::NotMapped);
break; break;
case CRegInfo::STATE_MAPPED_32_ZERO: case CRegInfo::STATE_MAPPED_32_ZERO:
XorX86RegToX86Reg(x86RegHi,x86RegHi); XorX86RegToX86Reg(x86RegHi,x86RegHi);
MoveX86RegToX86Reg(MipsRegMapLo(i),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(i),Reg);
m_RegWorkingSet.SetX86Mapped(MipsRegMapLo(i), CRegInfo::NotMapped); m_RegWorkingSet.SetX86Mapped(GetMipsRegMapLo(i), CRegInfo::NotMapped);
break; break;
case CRegInfo::STATE_CONST_64: case CRegInfo::STATE_CONST_64:
MoveConstToX86reg(MipsRegHi(i),x86RegHi); MoveConstToX86reg(GetMipsRegHi(i),x86RegHi);
MoveConstToX86reg(MipsRegLo(i),Reg); MoveConstToX86reg(GetMipsRegLo(i),Reg);
break; break;
case CRegInfo::STATE_CONST_32: case CRegInfo::STATE_CONST_32:
MoveConstToX86reg(MipsRegLo_S(i) >> 31,x86RegHi); MoveConstToX86reg(GetMipsRegLo_S(i) >> 31,x86RegHi);
MoveConstToX86reg(MipsRegLo(i),Reg); MoveConstToX86reg(GetMipsRegLo(i),Reg);
break; break;
default: default:
CPU_Message("Do something with states in SyncRegState\nSTATE_MAPPED_64\n%d",MipsRegState(i)); CPU_Message("Do something with states in SyncRegState\nSTATE_MAPPED_64\n%d",MipsRegState(i));
@ -740,28 +740,28 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
break; break;
case CRegInfo::STATE_MAPPED_32_SIGN: case CRegInfo::STATE_MAPPED_32_SIGN:
{ {
x86Reg Reg = SyncTo.MipsRegMapLo(i); x86Reg Reg = SyncTo.GetMipsRegMapLo(i);
UnMap_X86reg(Reg); UnMap_X86reg(Reg);
switch (MipsRegState(i)) { switch (MipsRegState(i)) {
case CRegInfo::STATE_UNKNOWN: MoveVariableToX86reg(&_GPR[i].UW[0],CRegName::GPR_Lo[i],Reg); break; case CRegInfo::STATE_UNKNOWN: MoveVariableToX86reg(&_GPR[i].UW[0],CRegName::GPR_Lo[i],Reg); break;
case CRegInfo::STATE_CONST_32: MoveConstToX86reg(MipsRegLo(i),Reg); break; case CRegInfo::STATE_CONST_32: MoveConstToX86reg(GetMipsRegLo(i),Reg); break;
case CRegInfo::STATE_MAPPED_32_SIGN: case CRegInfo::STATE_MAPPED_32_SIGN:
MoveX86RegToX86Reg(MipsRegMapLo(i),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(i),Reg);
m_RegWorkingSet.SetX86Mapped(MipsRegMapLo(i),CRegInfo::NotMapped); m_RegWorkingSet.SetX86Mapped(GetMipsRegMapLo(i),CRegInfo::NotMapped);
break; break;
case CRegInfo::STATE_MAPPED_32_ZERO: case CRegInfo::STATE_MAPPED_32_ZERO:
if (MipsRegMapLo(i) != Reg) { if (GetMipsRegMapLo(i) != Reg) {
MoveX86RegToX86Reg(MipsRegMapLo(i),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(i),Reg);
m_RegWorkingSet.SetX86Mapped(MipsRegMapLo(i),CRegInfo::NotMapped); m_RegWorkingSet.SetX86Mapped(GetMipsRegMapLo(i),CRegInfo::NotMapped);
} }
break; break;
case CRegInfo::STATE_MAPPED_64: case CRegInfo::STATE_MAPPED_64:
MoveX86RegToX86Reg(MipsRegMapLo(i),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(i),Reg);
m_RegWorkingSet.SetX86Mapped(MipsRegMapLo(i),CRegInfo::NotMapped) ; m_RegWorkingSet.SetX86Mapped(GetMipsRegMapLo(i),CRegInfo::NotMapped) ;
m_RegWorkingSet.SetX86Mapped(MipsRegMapHi(i),CRegInfo::NotMapped); m_RegWorkingSet.SetX86Mapped(GetMipsRegMapHi(i),CRegInfo::NotMapped);
break; break;
case CRegInfo::STATE_CONST_64: case CRegInfo::STATE_CONST_64:
CPU_Message("hi %X\nLo %X",MipsRegHi(i),MipsRegLo(i)); CPU_Message("hi %X\nLo %X",GetMipsRegHi(i),GetMipsRegLo(i));
default: default:
CPU_Message("Do something with states in SyncRegState\nSTATE_MAPPED_32_SIGN\n%d",MipsRegState(i)); CPU_Message("Do something with states in SyncRegState\nSTATE_MAPPED_32_SIGN\n%d",MipsRegState(i));
_Notify->BreakPoint(__FILE__,__LINE__); _Notify->BreakPoint(__FILE__,__LINE__);
@ -774,7 +774,7 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
break; break;
case CRegInfo::STATE_MAPPED_32_ZERO: case CRegInfo::STATE_MAPPED_32_ZERO:
{ {
x86Reg Reg = SyncTo.MipsRegMapLo(i); x86Reg Reg = SyncTo.GetMipsRegMapLo(i);
UnMap_X86reg(Reg); UnMap_X86reg(Reg);
switch (MipsRegState(i)) { switch (MipsRegState(i)) {
case CRegInfo::STATE_MAPPED_64: case CRegInfo::STATE_MAPPED_64:
@ -782,27 +782,27 @@ void CCodeSection::SyncRegState ( const CRegInfo & SyncTo )
MoveVariableToX86reg(&_GPR[i].UW[0],CRegName::GPR_Lo[i],Reg); MoveVariableToX86reg(&_GPR[i].UW[0],CRegName::GPR_Lo[i],Reg);
break; break;
case CRegInfo::STATE_MAPPED_32_ZERO: case CRegInfo::STATE_MAPPED_32_ZERO:
MoveX86RegToX86Reg(MipsRegMapLo(i),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(i),Reg);
m_RegWorkingSet.SetX86Mapped(MipsRegMapLo(i),CRegInfo::NotMapped); m_RegWorkingSet.SetX86Mapped(GetMipsRegMapLo(i),CRegInfo::NotMapped);
break; break;
case CRegInfo::STATE_MAPPED_32_SIGN: case CRegInfo::STATE_MAPPED_32_SIGN:
if (b32BitCore()) if (b32BitCore())
{ {
MoveX86RegToX86Reg(MipsRegMapLo(i),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(i),Reg);
m_RegWorkingSet.SetX86Mapped(MipsRegMapLo(i),CRegInfo::NotMapped); m_RegWorkingSet.SetX86Mapped(GetMipsRegMapLo(i),CRegInfo::NotMapped);
} else { } else {
CPU_Message("Do something with states in SyncRegState\nSTATE_MAPPED_32_ZERO\n%d",MipsRegState(i)); CPU_Message("Do something with states in SyncRegState\nSTATE_MAPPED_32_ZERO\n%d",MipsRegState(i));
_Notify->BreakPoint(__FILE__,__LINE__); _Notify->BreakPoint(__FILE__,__LINE__);
} }
break; break;
case CRegInfo::STATE_CONST_32: case CRegInfo::STATE_CONST_32:
if (!b32BitCore() && MipsRegLo_S(i) < 0) if (!b32BitCore() && GetMipsRegLo_S(i) < 0)
{ {
CPU_Message("Sign Problems in SyncRegState\nSTATE_MAPPED_32_ZERO"); CPU_Message("Sign Problems in SyncRegState\nSTATE_MAPPED_32_ZERO");
CPU_Message("%s: %X",CRegName::GPR[i],MipsRegLo_S(i)); CPU_Message("%s: %X",CRegName::GPR[i],GetMipsRegLo_S(i));
_Notify->BreakPoint(__FILE__,__LINE__); _Notify->BreakPoint(__FILE__,__LINE__);
} }
MoveConstToX86reg(MipsRegLo(i),Reg); MoveConstToX86reg(GetMipsRegLo(i),Reg);
break; break;
default: default:
CPU_Message("Do something with states in SyncRegState\nSTATE_MAPPED_32_ZERO\n%d",MipsRegState(i)); CPU_Message("Do something with states in SyncRegState\nSTATE_MAPPED_32_ZERO\n%d",MipsRegState(i));
@ -1406,7 +1406,7 @@ void CCodeSection::TestRegConstantStates( CRegInfo & Base, CRegInfo & Reg )
{ {
if (Reg.Is32Bit(i)) if (Reg.Is32Bit(i))
{ {
if (Reg.MipsRegLo(i) != Base.MipsRegLo(i)) if (Reg.GetMipsRegLo(i) != Base.GetMipsRegLo(i))
{ {
Reg.SetMipsRegState(i, CRegInfo::STATE_UNKNOWN); Reg.SetMipsRegState(i, CRegInfo::STATE_UNKNOWN);
} }
@ -1801,7 +1801,7 @@ bool CCodeSection::InheritParentInfo ( void )
break; break;
case CRegInfo::STATE_CONST_64: Map_GPR_64bit(i2,i2); break; case CRegInfo::STATE_CONST_64: Map_GPR_64bit(i2,i2); break;
case CRegInfo::STATE_CONST_32: case CRegInfo::STATE_CONST_32:
if ((RegSet->MipsRegLo_S(i2) < 0) && IsUnsigned(i2)) { if ((RegSet->GetMipsRegLo_S(i2) < 0) && IsUnsigned(i2)) {
m_RegWorkingSet.SetMipsRegState(i2,CRegInfo::STATE_MAPPED_32_SIGN); m_RegWorkingSet.SetMipsRegState(i2,CRegInfo::STATE_MAPPED_32_SIGN);
} }
break; break;
@ -1826,7 +1826,7 @@ bool CCodeSection::InheritParentInfo ( void )
} else { } else {
Map_GPR_32bit(i2,true,i2); Map_GPR_32bit(i2,true,i2);
} }
} else if (Is32Bit(i2) && MipsRegLo(i2) != RegSet->MipsRegLo(i2)) { } else if (Is32Bit(i2) && GetMipsRegLo(i2) != RegSet->GetMipsRegLo(i2)) {
Map_GPR_32bit(i2,true,i2); Map_GPR_32bit(i2,true,i2);
} else if (Is64Bit(i2) && MipsReg(i2) != RegSet->MipsReg(i2)) { } else if (Is64Bit(i2) && MipsReg(i2) != RegSet->MipsReg(i2)) {
Map_GPR_32bit(i2,true,i2); Map_GPR_32bit(i2,true,i2);
@ -1882,21 +1882,21 @@ bool CCodeSection::InheritParentInfo ( void )
switch (m_RegWorkingSet.MipsRegState(i2)) { switch (m_RegWorkingSet.MipsRegState(i2)) {
case CRegInfo::STATE_UNKNOWN: break; case CRegInfo::STATE_UNKNOWN: break;
case CRegInfo::STATE_MAPPED_64: case CRegInfo::STATE_MAPPED_64:
if (MipsRegMapHi(i2) != RegSet->MipsRegMapHi(i2) || if (GetMipsRegMapHi(i2) != RegSet->GetMipsRegMapHi(i2) ||
MipsRegMapLo(i2) != RegSet->MipsRegMapLo(i2)) GetMipsRegMapLo(i2) != RegSet->GetMipsRegMapLo(i2))
{ {
NeedSync = true; NeedSync = true;
} }
break; break;
case CRegInfo::STATE_MAPPED_32_ZERO: case CRegInfo::STATE_MAPPED_32_ZERO:
case CRegInfo::STATE_MAPPED_32_SIGN: case CRegInfo::STATE_MAPPED_32_SIGN:
if (MipsRegMapLo(i2) != RegSet->MipsRegMapLo(i2)) { if (GetMipsRegMapLo(i2) != RegSet->GetMipsRegMapLo(i2)) {
//DisplayError("Parent: %d",Parent->SectionID); //DisplayError("Parent: %d",Parent->SectionID);
NeedSync = true; NeedSync = true;
} }
break; break;
case CRegInfo::STATE_CONST_32: case CRegInfo::STATE_CONST_32:
if (MipsRegLo(i2) != RegSet->MipsRegLo(i2)) if (GetMipsRegLo(i2) != RegSet->GetMipsRegLo(i2))
{ {
_Notify->BreakPoint(__FILE__,__LINE__); _Notify->BreakPoint(__FILE__,__LINE__);
NeedSync = true; NeedSync = true;

92
Source/Project64/N64 System/Recompiler/Loop Analysis.cpp
View File

@ -161,7 +161,7 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
return false; return false;
} }
CPU_Message(" %08X: %s",m_PC,R4300iOpcodeName(m_Command.Hex,m_PC)); CPU_Message(" %08X: %s",m_PC,R4300iOpcodeName(m_Command.Hex,m_PC));
CPU_Message(" %s state: %X value: %X",CRegName::GPR[3],m_Reg.MipsRegState(3),m_Reg.MipsRegLo(3)); CPU_Message(" %s state: %X value: %X",CRegName::GPR[3],m_Reg.MipsRegState(3),m_Reg.GetMipsRegLo(3));
switch (m_Command.op) { switch (m_Command.op) {
case R4300i_SPECIAL: case R4300i_SPECIAL:
switch (m_Command.funct) { switch (m_Command.funct) {
@ -280,7 +280,7 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
case R4300i_REGIMM_BLTZAL: case R4300i_REGIMM_BLTZAL:
_Notify->BreakPoint(__FILE__,__LINE__); _Notify->BreakPoint(__FILE__,__LINE__);
#ifdef tofix #ifdef tofix
m_Reg.MipsRegLo(31) = m_PC + 8; m_Reg.GetMipsRegLo(31) = m_PC + 8;
m_Reg.SetMipsRegState(31,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(31,CRegInfo::STATE_CONST_32);
Section->m_Cont.TargetPC = m_PC + 8; Section->m_Cont.TargetPC = m_PC + 8;
Section->m_Jump.TargetPC = m_PC + ((short)m_Command.offset << 2) + 4; Section->m_Jump.TargetPC = m_PC + ((short)m_Command.offset << 2) + 4;
@ -300,12 +300,12 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
__int64 Value; __int64 Value;
if (m_Reg.Is32Bit(m_Command.rs)) if (m_Reg.Is32Bit(m_Command.rs))
{ {
Value = m_Reg.MipsRegLo_S(m_Command.rs); Value = m_Reg.GetMipsRegLo_S(m_Command.rs);
} else { } else {
Value = m_Reg.cMipsReg_S(m_Command.rs); Value = m_Reg.cMipsReg_S(m_Command.rs);
} }
if (Value >= 0) { if (Value >= 0) {
m_Reg.MipsRegLo(31) = m_PC + 8; m_Reg.GetMipsRegLo(31) = m_PC + 8;
m_Reg.SetMipsRegState(31,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(31,CRegInfo::STATE_CONST_32);
Section->m_Jump.TargetPC = m_PC + ((short)m_Command.offset << 2) + 4; Section->m_Jump.TargetPC = m_PC + ((short)m_Command.offset << 2) + 4;
if (m_PC == Section->m_Jump.TargetPC) { if (m_PC == Section->m_Jump.TargetPC) {
@ -318,7 +318,7 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
} }
m_Reg.MipsRegLo(31) = m_PC + 8; m_Reg.GetMipsRegLo(31) = m_PC + 8;
m_Reg.SetMipsRegState(31,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(31,CRegInfo::STATE_CONST_32);
Section->m_Cont.TargetPC = m_PC + 8; Section->m_Cont.TargetPC = m_PC + 8;
Section->m_Jump.TargetPC = m_PC + ((short)m_Command.offset << 2) + 4; Section->m_Jump.TargetPC = m_PC + ((short)m_Command.offset << 2) + 4;
@ -344,7 +344,7 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
_Notify->BreakPoint(__FILE__,__LINE__); _Notify->BreakPoint(__FILE__,__LINE__);
#ifdef tofix #ifdef tofix
m_NextInstruction = DELAY_SLOT; m_NextInstruction = DELAY_SLOT;
m_Reg.MipsRegLo(31) = m_PC + 8; m_Reg.GetMipsRegLo(31) = m_PC + 8;
m_Reg.SetMipsRegState(31,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(31,CRegInfo::STATE_CONST_32);
Section->m_Jump.TargetPC = (m_PC & 0xF0000000) + (m_Command.target << 2); Section->m_Jump.TargetPC = (m_PC & 0xF0000000) + (m_Command.target << 2);
if (m_PC == Section->m_Jump.TargetPC) { if (m_PC == Section->m_Jump.TargetPC) {
@ -433,7 +433,7 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
case R4300i_ADDIU: case R4300i_ADDIU:
if (m_Command.rt == 0) { break; } if (m_Command.rt == 0) { break; }
/*if (m_Command.rs == 0) { /*if (m_Command.rs == 0) {
m_Reg.MipsRegLo(m_Command.rt) = (short)m_Command.immediate; m_Reg.GetMipsRegLo(m_Command.rt) = (short)m_Command.immediate;
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32);
} else {*/ } else {*/
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_MODIFIED);
@ -443,9 +443,9 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
if (m_Command.rt == 0) { break; } if (m_Command.rt == 0) { break; }
if (m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rs)) {
if (m_Reg.Is64Bit(m_Command.rs)) { if (m_Reg.Is64Bit(m_Command.rs)) {
m_Reg.MipsRegLo(m_Command.rt) = (m_Reg.cMipsReg_S(m_Command.rs) < (_int64)((short)m_Command.immediate))?1:0; m_Reg.SetMipsRegLo(m_Command.rt, (m_Reg.cMipsReg_S(m_Command.rs) < (_int64)((short)m_Command.immediate))?1:0);
} else { } else {
m_Reg.MipsRegLo(m_Command.rt) = (m_Reg.MipsRegLo_S(m_Command.rs) < (int)((short)m_Command.immediate))?1:0; m_Reg.SetMipsRegLo(m_Command.rt, (m_Reg.GetMipsRegLo_S(m_Command.rs) < (int)((short)m_Command.immediate))?1:0);
} }
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32);
} else { } else {
@ -456,9 +456,9 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
if (m_Command.rt == 0) { break; } if (m_Command.rt == 0) { break; }
if (m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rs)) {
if (m_Reg.Is64Bit(m_Command.rs)) { if (m_Reg.Is64Bit(m_Command.rs)) {
m_Reg.MipsRegLo(m_Command.rt) = (m_Reg.MipsReg(m_Command.rs) < (unsigned _int64)((short)m_Command.immediate))?1:0; m_Reg.SetMipsRegLo(m_Command.rt,(m_Reg.MipsReg(m_Command.rs) < (unsigned _int64)((short)m_Command.immediate))?1:0);
} else { } else {
m_Reg.MipsRegLo(m_Command.rt) = (m_Reg.MipsRegLo(m_Command.rs) < (DWORD)((short)m_Command.immediate))?1:0; m_Reg.SetMipsRegLo(m_Command.rt,(m_Reg.GetMipsRegLo(m_Command.rs) < (DWORD)((short)m_Command.immediate))?1:0);
} }
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32);
} else { } else {
@ -469,7 +469,7 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
if (m_Command.rt == 0) { break; } if (m_Command.rt == 0) { break; }
if (!m_Reg.IsModified(m_Command.rt)) if (!m_Reg.IsModified(m_Command.rt))
{ {
m_Reg.MipsRegLo(m_Command.rt) = ((short)m_Command.offset << 16); m_Reg.SetMipsRegLo(m_Command.rt,((short)m_Command.offset << 16));
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32);
} }
break; break;
@ -485,7 +485,7 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
} }
if (m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32);
m_Reg.MipsRegLo(m_Command.rt) = m_Reg.MipsRegLo(m_Command.rs) | m_Command.immediate; m_Reg.SetMipsRegLo(m_Command.rt,m_Reg.GetMipsRegLo(m_Command.rs) | m_Command.immediate);
} else { } else {
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_MODIFIED);
} }
@ -498,7 +498,7 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
} }
if (m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_32);
m_Reg.MipsRegLo(m_Command.rt) = m_Reg.MipsRegLo(m_Command.rs) ^ m_Command.immediate; m_Reg.SetMipsRegLo(m_Command.rt, m_Reg.GetMipsRegLo(m_Command.rs) ^ m_Command.immediate);
} else { } else {
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_MODIFIED);
} }
@ -648,9 +648,9 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
if (m_Reg.Is64Bit(m_Command.rs)) { if (m_Reg.Is64Bit(m_Command.rs)) {
int imm32 = (short)m_Command.immediate; int imm32 = (short)m_Command.immediate;
__int64 imm64 = imm32; __int64 imm64 = imm32;
m_Reg.MipsReg_S(m_Command.rt) = m_Reg.MipsRegLo_S(m_Command.rs) + imm64; m_Reg.MipsReg_S(m_Command.rt) = m_Reg.GetMipsRegLo_S(m_Command.rs) + imm64;
} else { } else {
m_Reg.MipsReg_S(m_Command.rt) = m_Reg.MipsRegLo_S(m_Command.rs) + (short)m_Command.immediate; m_Reg.MipsReg_S(m_Command.rt) = m_Reg.GetMipsRegLo_S(m_Command.rs) + (short)m_Command.immediate;
} }
m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rt,CRegInfo::STATE_CONST_64);
} else { } else {
@ -701,7 +701,7 @@ bool LoopAnalysis::CheckLoopRegisterUsage( CCodeSection * Section)
R4300iOpcodeName(m_Command.Hex,m_PC),m_Command.Hex); R4300iOpcodeName(m_Command.Hex,m_PC),m_Command.Hex);
} }
CPU_Message(" %s state: %X value: %X",CRegName::GPR[5],m_Reg.MipsRegState(5),m_Reg.MipsRegLo(5)); CPU_Message(" %s state: %X value: %X",CRegName::GPR[5],m_Reg.MipsRegState(5),m_Reg.GetMipsRegLo(5));
if (Section->m_DelaySlot) if (Section->m_DelaySlot)
{ {
@ -839,7 +839,7 @@ void LoopAnalysis::SPECIAL_SLLV ( void )
} }
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32);
m_Reg.MipsRegLo(m_Command.rd) = m_Reg.MipsRegLo(m_Command.rt) << (m_Reg.MipsRegLo(m_Command.rs) & 0x1F); m_Reg.SetMipsRegLo(m_Command.rd, m_Reg.GetMipsRegLo(m_Command.rt) << (m_Reg.GetMipsRegLo(m_Command.rs) & 0x1F));
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -854,7 +854,7 @@ void LoopAnalysis::SPECIAL_SRLV ( void )
} }
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32);
m_Reg.MipsRegLo(m_Command.rd) = m_Reg.MipsRegLo(m_Command.rt) >> (m_Reg.MipsRegLo(m_Command.rs) & 0x1F); m_Reg.SetMipsRegLo(m_Command.rd, m_Reg.GetMipsRegLo(m_Command.rt) >> (m_Reg.GetMipsRegLo(m_Command.rs) & 0x1F));
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -869,7 +869,7 @@ void LoopAnalysis::SPECIAL_SRAV ( void )
} }
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32);
m_Reg.MipsRegLo(m_Command.rd) = m_Reg.MipsRegLo_S(m_Command.rt) >> (m_Reg.MipsRegLo(m_Command.rs) & 0x1F); m_Reg.SetMipsRegLo(m_Command.rd, m_Reg.GetMipsRegLo_S(m_Command.rt) >> (m_Reg.GetMipsRegLo(m_Command.rs) & 0x1F));
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -880,7 +880,7 @@ void LoopAnalysis::SPECIAL_JR ( void )
_Notify->BreakPoint(__FILE__,__LINE__); _Notify->BreakPoint(__FILE__,__LINE__);
#ifdef tofix #ifdef tofix
if (m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rs)) {
Section->m_Jump.TargetPC = m_Reg.MipsRegLo(m_Command.rs); Section->m_Jump.TargetPC = m_Reg.GetMipsRegLo(m_Command.rs);
} else { } else {
Section->m_Jump.TargetPC = (DWORD)-1; Section->m_Jump.TargetPC = (DWORD)-1;
} }
@ -892,10 +892,10 @@ void LoopAnalysis::SPECIAL_JALR ( void )
{ {
_Notify->BreakPoint(__FILE__,__LINE__); _Notify->BreakPoint(__FILE__,__LINE__);
#ifdef tofix #ifdef tofix
m_Reg.MipsRegLo(m_Command.rd) = m_PC + 8; m_Reg.GetMipsRegLo(m_Command.rd) = m_PC + 8;
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32);
if (m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rs)) {
Section->m_Jump.TargetPC = m_Reg.MipsRegLo(m_Command.rs); Section->m_Jump.TargetPC = m_Reg.GetMipsRegLo(m_Command.rs);
} else { } else {
Section->m_Jump.TargetPC = (DWORD)-1; Section->m_Jump.TargetPC = (DWORD)-1;
} }
@ -944,7 +944,7 @@ void LoopAnalysis::SPECIAL_DSLLV ( void )
} }
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
m_Reg.SetMipsReg(m_Command.rd, m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(QWORD)m_Reg.MipsRegLo_S(m_Command.rt) << (m_Reg.MipsRegLo(m_Command.rs) & 0x3F)); m_Reg.SetMipsReg(m_Command.rd, m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(QWORD)m_Reg.GetMipsRegLo_S(m_Command.rt) << (m_Reg.GetMipsRegLo(m_Command.rs) & 0x3F));
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -959,7 +959,7 @@ void LoopAnalysis::SPECIAL_DSRLV ( void )
} }
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
m_Reg.SetMipsReg(m_Command.rd,m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(QWORD)m_Reg.MipsRegLo_S(m_Command.rt) >> (m_Reg.MipsRegLo(m_Command.rs) & 0x3F)); m_Reg.SetMipsReg(m_Command.rd,m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(QWORD)m_Reg.GetMipsRegLo_S(m_Command.rt) >> (m_Reg.GetMipsRegLo(m_Command.rs) & 0x3F));
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -975,7 +975,7 @@ void LoopAnalysis::SPECIAL_DSRAV ( void )
} }
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
m_Reg.SetMipsReg(m_Command.rd,m_Reg.Is64Bit(m_Command.rt)?m_Reg.cMipsReg_S(m_Command.rt):(_int64)m_Reg.MipsRegLo_S(m_Command.rt) >> (m_Reg.MipsRegLo(m_Command.rs) & 0x3F)); m_Reg.SetMipsReg(m_Command.rd,m_Reg.Is64Bit(m_Command.rt)?m_Reg.cMipsReg_S(m_Command.rt):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rt) >> (m_Reg.GetMipsRegLo(m_Command.rs) & 0x3F));
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -1035,12 +1035,12 @@ void LoopAnalysis::SPECIAL_SLT ( void )
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
if (m_Reg.Is64Bit(m_Command.rt) || m_Reg.Is64Bit(m_Command.rs)) { if (m_Reg.Is64Bit(m_Command.rt) || m_Reg.Is64Bit(m_Command.rs)) {
if (m_Reg.Is64Bit(m_Command.rt)) { if (m_Reg.Is64Bit(m_Command.rt)) {
m_Reg.MipsRegLo(m_Command.rd) = (m_Reg.MipsRegLo_S(m_Command.rs) < m_Reg.cMipsReg_S(m_Command.rt))?1:0; m_Reg.SetMipsRegLo(m_Command.rd, (m_Reg.GetMipsRegLo_S(m_Command.rs) < m_Reg.cMipsReg_S(m_Command.rt))?1:0);
} else { } else {
m_Reg.MipsRegLo(m_Command.rd) = (m_Reg.cMipsReg_S(m_Command.rs) < m_Reg.MipsRegLo_S(m_Command.rt))?1:0; m_Reg.SetMipsRegLo(m_Command.rd, (m_Reg.cMipsReg_S(m_Command.rs) < m_Reg.GetMipsRegLo_S(m_Command.rt))?1:0);
} }
} else { } else {
m_Reg.MipsRegLo(m_Command.rd) = (m_Reg.MipsRegLo_S(m_Command.rs) < m_Reg.MipsRegLo_S(m_Command.rt))?1:0; m_Reg.SetMipsRegLo(m_Command.rd, (m_Reg.GetMipsRegLo_S(m_Command.rs) < m_Reg.GetMipsRegLo_S(m_Command.rt))?1:0);
} }
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32);
} else { } else {
@ -1054,12 +1054,12 @@ void LoopAnalysis::SPECIAL_SLTU ( void )
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
if (m_Reg.Is64Bit(m_Command.rt) || m_Reg.Is64Bit(m_Command.rs)) { if (m_Reg.Is64Bit(m_Command.rt) || m_Reg.Is64Bit(m_Command.rs)) {
if (m_Reg.Is64Bit(m_Command.rt)) { if (m_Reg.Is64Bit(m_Command.rt)) {
m_Reg.MipsRegLo(m_Command.rd) = (m_Reg.MipsRegLo(m_Command.rs) < m_Reg.MipsReg(m_Command.rt))?1:0; m_Reg.SetMipsRegLo(m_Command.rd,(m_Reg.GetMipsRegLo(m_Command.rs) < m_Reg.MipsReg(m_Command.rt))?1:0);
} else { } else {
m_Reg.MipsRegLo(m_Command.rd) = (m_Reg.MipsReg(m_Command.rs) < m_Reg.MipsRegLo(m_Command.rt))?1:0; m_Reg.SetMipsRegLo(m_Command.rd,(m_Reg.MipsReg(m_Command.rs) < m_Reg.GetMipsRegLo(m_Command.rt))?1:0);
} }
} else { } else {
m_Reg.MipsRegLo(m_Command.rd) = (m_Reg.MipsRegLo(m_Command.rs) < m_Reg.MipsRegLo(m_Command.rt))?1:0; m_Reg.SetMipsRegLo(m_Command.rd,(m_Reg.GetMipsRegLo(m_Command.rs) < m_Reg.GetMipsRegLo(m_Command.rt))?1:0);
} }
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32);
} else { } else {
@ -1076,8 +1076,8 @@ void LoopAnalysis::SPECIAL_DADD ( void )
} }
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsReg(m_Command.rd, m_Reg.SetMipsReg(m_Command.rd,
m_Reg.Is64Bit(m_Command.rs)?m_Reg.MipsReg(m_Command.rs):(_int64)m_Reg.MipsRegLo_S(m_Command.rs) + m_Reg.Is64Bit(m_Command.rs)?m_Reg.MipsReg(m_Command.rs):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rs) +
m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(_int64)m_Reg.MipsRegLo_S(m_Command.rt) m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rt)
); );
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
} else { } else {
@ -1094,8 +1094,8 @@ void LoopAnalysis::SPECIAL_DADDU ( void )
} }
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsReg(m_Command.rd, m_Reg.SetMipsReg(m_Command.rd,
m_Reg.Is64Bit(m_Command.rs)?m_Reg.MipsReg(m_Command.rs):(_int64)m_Reg.MipsRegLo_S(m_Command.rs) + m_Reg.Is64Bit(m_Command.rs)?m_Reg.MipsReg(m_Command.rs):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rs) +
m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(_int64)m_Reg.MipsRegLo_S(m_Command.rt) m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rt)
); );
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
} else { } else {
@ -1112,8 +1112,8 @@ void LoopAnalysis::SPECIAL_DSUB ( void )
} }
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsReg(m_Command.rd, m_Reg.SetMipsReg(m_Command.rd,
m_Reg.Is64Bit(m_Command.rs)?m_Reg.MipsReg(m_Command.rs):(_int64)m_Reg.MipsRegLo_S(m_Command.rs) - m_Reg.Is64Bit(m_Command.rs)?m_Reg.MipsReg(m_Command.rs):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rs) -
m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(_int64)m_Reg.MipsRegLo_S(m_Command.rt) m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rt)
); );
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
} else { } else {
@ -1130,8 +1130,8 @@ void LoopAnalysis::SPECIAL_DSUBU ( void )
} }
if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) { if (m_Reg.IsConst(m_Command.rt) && m_Reg.IsConst(m_Command.rs)) {
m_Reg.SetMipsReg(m_Command.rd, m_Reg.SetMipsReg(m_Command.rd,
m_Reg.Is64Bit(m_Command.rs)?m_Reg.MipsReg(m_Command.rs):(_int64)m_Reg.MipsRegLo_S(m_Command.rs) - m_Reg.Is64Bit(m_Command.rs)?m_Reg.MipsReg(m_Command.rs):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rs) -
m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(_int64)m_Reg.MipsRegLo_S(m_Command.rt) m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rt)
); );
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
} else { } else {
@ -1148,7 +1148,7 @@ void LoopAnalysis::SPECIAL_DSLL ( void )
} }
if (m_Reg.IsConst(m_Command.rt)) { if (m_Reg.IsConst(m_Command.rt)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
m_Reg.SetMipsReg(m_Command.rd,m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(_int64)m_Reg.MipsRegLo_S(m_Command.rt) << m_Command.sa); m_Reg.SetMipsReg(m_Command.rd,m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rt) << m_Command.sa);
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -1163,7 +1163,7 @@ void LoopAnalysis::SPECIAL_DSRL ( void )
} }
if (m_Reg.IsConst(m_Command.rt)) { if (m_Reg.IsConst(m_Command.rt)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
m_Reg.SetMipsReg(m_Command.rd, m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(QWORD)m_Reg.MipsRegLo_S(m_Command.rt) >> m_Command.sa); m_Reg.SetMipsReg(m_Command.rd, m_Reg.Is64Bit(m_Command.rt)?m_Reg.MipsReg(m_Command.rt):(QWORD)m_Reg.GetMipsRegLo_S(m_Command.rt) >> m_Command.sa);
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -1178,7 +1178,7 @@ void LoopAnalysis::SPECIAL_DSRA ( void )
} }
if (m_Reg.IsConst(m_Command.rt)) { if (m_Reg.IsConst(m_Command.rt)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
m_Reg.MipsReg_S(m_Command.rd) = m_Reg.Is64Bit(m_Command.rt)?m_Reg.cMipsReg_S(m_Command.rt):(_int64)m_Reg.MipsRegLo_S(m_Command.rt) >> m_Command.sa; m_Reg.MipsReg_S(m_Command.rd) = m_Reg.Is64Bit(m_Command.rt)?m_Reg.cMipsReg_S(m_Command.rt):(_int64)m_Reg.GetMipsRegLo_S(m_Command.rt) >> m_Command.sa;
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -1193,7 +1193,7 @@ void LoopAnalysis::SPECIAL_DSLL32 ( void )
} }
if (m_Reg.IsConst(m_Command.rt)) { if (m_Reg.IsConst(m_Command.rt)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_64);
m_Reg.SetMipsReg(m_Command.rd, m_Reg.MipsRegLo(m_Command.rt) << (m_Command.sa + 32)); m_Reg.SetMipsReg(m_Command.rd, m_Reg.GetMipsRegLo(m_Command.rt) << (m_Command.sa + 32));
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -1208,7 +1208,7 @@ void LoopAnalysis::SPECIAL_DSRL32 ( void )
} }
if (m_Reg.IsConst(m_Command.rt)) { if (m_Reg.IsConst(m_Command.rt)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32);
m_Reg.MipsRegLo(m_Command.rd) = (DWORD)(m_Reg.MipsReg(m_Command.rt) >> (m_Command.sa + 32)); m_Reg.SetMipsRegLo(m_Command.rd,(DWORD)(m_Reg.MipsReg(m_Command.rt) >> (m_Command.sa + 32)));
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }
@ -1223,7 +1223,7 @@ void LoopAnalysis::SPECIAL_DSRA32 ( void )
} }
if (m_Reg.IsConst(m_Command.rt)) { if (m_Reg.IsConst(m_Command.rt)) {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_CONST_32);
m_Reg.MipsRegLo(m_Command.rd) = (DWORD)(m_Reg.cMipsReg_S(m_Command.rt) >> (m_Command.sa + 32)); m_Reg.SetMipsRegLo(m_Command.rd,(DWORD)(m_Reg.cMipsReg_S(m_Command.rt) >> (m_Command.sa + 32)));
} else { } else {
m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED); m_Reg.SetMipsRegState(m_Command.rd,CRegInfo::STATE_MODIFIED);
} }

832
Source/Project64/N64 System/Recompiler/Recompiler Ops.cpp
View File

File diff suppressed because it is too large Load Diff

13
Source/Project64/N64 System/Recompiler/Recompiler Ops.h
View File

@ -219,13 +219,12 @@ protected:
static inline REG_STATE MipsRegState ( int Reg ) { return m_RegWorkingSet.MipsRegState(Reg); } static inline REG_STATE MipsRegState ( int Reg ) { return m_RegWorkingSet.MipsRegState(Reg); }
static inline unsigned __int64 MipsReg ( int Reg ) { return m_RegWorkingSet.MipsReg(Reg); } static inline unsigned __int64 MipsReg ( int Reg ) { return m_RegWorkingSet.MipsReg(Reg); }
static inline _int64 & MipsReg_S ( int Reg ) { return m_RegWorkingSet.MipsReg_S(Reg); } static inline _int64 & MipsReg_S ( int Reg ) { return m_RegWorkingSet.MipsReg_S(Reg); }
static inline DWORD & MipsRegLo ( int Reg ) { return m_RegWorkingSet.MipsRegLo(Reg); } static inline DWORD GetMipsRegLo ( int Reg ) { return m_RegWorkingSet.GetMipsRegLo(Reg); }
static inline long & MipsRegLo_S ( int Reg ) { return m_RegWorkingSet.MipsRegLo_S(Reg); } static inline long GetMipsRegLo_S ( int Reg ) { return m_RegWorkingSet.GetMipsRegLo_S(Reg); }
static inline DWORD & MipsRegHi ( int Reg ) { return m_RegWorkingSet.MipsRegHi(Reg); } static inline DWORD GetMipsRegHi ( int Reg ) { return m_RegWorkingSet.GetMipsRegHi(Reg); }
static inline long & MipsRegHi_S ( int Reg ) { return m_RegWorkingSet.MipsRegHi_S(Reg); } static inline long GetMipsRegHi_S ( int Reg ) { return m_RegWorkingSet.GetMipsRegHi_S(Reg); }
static inline CX86Ops::x86Reg MipsRegMapLo ( int Reg ) { return m_RegWorkingSet.MipsRegMapLo(Reg); } static inline CX86Ops::x86Reg GetMipsRegMapLo ( int Reg ) { return m_RegWorkingSet.GetMipsRegMapLo(Reg); }
static inline CX86Ops::x86Reg MipsRegMapHi ( int Reg ) { return m_RegWorkingSet.MipsRegMapHi(Reg); } static inline CX86Ops::x86Reg GetMipsRegMapHi ( int Reg ) { return m_RegWorkingSet.GetMipsRegMapHi(Reg); }
static inline bool X86Protected ( x86Reg Reg ) { return m_RegWorkingSet.X86Protected(Reg); }
static inline bool IsKnown ( int Reg ) { return m_RegWorkingSet.IsKnown(Reg); } static inline bool IsKnown ( int Reg ) { return m_RegWorkingSet.IsKnown(Reg); }
static inline bool IsUnknown ( int Reg ) { return m_RegWorkingSet.IsUnknown(Reg); } static inline bool IsUnknown ( int Reg ) { return m_RegWorkingSet.IsUnknown(Reg); }

118
Source/Project64/N64 System/Recompiler/Reg Info.cpp
View File

@ -563,13 +563,13 @@ void CRegInfo::Map_GPR_32bit (int MipsReg, bool SignValue, int MipsRegToLoad)
} else { } else {
if (Is64Bit(MipsReg)) if (Is64Bit(MipsReg))
{ {
CPU_Message(" regcache: unallocate %s from high 32bit of %s",x86_Name(MipsRegMapHi(MipsReg)),CRegName::GPR_Hi[MipsReg]); CPU_Message(" regcache: unallocate %s from high 32bit of %s",x86_Name(GetMipsRegMapHi(MipsReg)),CRegName::GPR_Hi[MipsReg]);
SetX86MapOrder(MipsRegMapHi(MipsReg),0); SetX86MapOrder(GetMipsRegMapHi(MipsReg),0);
SetX86Mapped(MipsRegMapHi(MipsReg),NotMapped); SetX86Mapped(GetMipsRegMapHi(MipsReg),NotMapped);
SetX86Protected(MipsRegMapHi(MipsReg),FALSE); SetX86Protected(GetMipsRegMapHi(MipsReg),FALSE);
MipsRegHi(MipsReg) = 0; SetMipsRegHi(MipsReg,0);
} }
Reg = MipsRegMapLo(MipsReg); Reg = GetMipsRegMapLo(MipsReg);
} }
for (count = 0; count < 10; count ++) for (count = 0; count < 10; count ++)
{ {
@ -589,10 +589,10 @@ void CRegInfo::Map_GPR_32bit (int MipsReg, bool SignValue, int MipsRegToLoad)
} else if (IsMapped(MipsRegToLoad)) { } else if (IsMapped(MipsRegToLoad)) {
if (MipsReg != MipsRegToLoad) if (MipsReg != MipsRegToLoad)
{ {
MoveX86RegToX86Reg(MipsRegMapLo(MipsRegToLoad),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(MipsRegToLoad),Reg);
} }
} else { } else {
MoveConstToX86reg(MipsRegLo(MipsRegToLoad),Reg); MoveConstToX86reg(GetMipsRegLo(MipsRegToLoad),Reg);
} }
} else if (MipsRegToLoad == 0) { } else if (MipsRegToLoad == 0) {
XorX86RegToX86Reg(Reg,Reg); XorX86RegToX86Reg(Reg,Reg);
@ -628,7 +628,7 @@ void CRegInfo::Map_GPR_64bit ( int MipsReg, int MipsRegToLoad)
CPU_Message(" regcache: allocate %s to hi word of %s",x86_Name(x86Hi),CRegName::GPR[MipsReg]); CPU_Message(" regcache: allocate %s to hi word of %s",x86_Name(x86Hi),CRegName::GPR[MipsReg]);
CPU_Message(" regcache: allocate %s to low word of %s",x86_Name(x86lo),CRegName::GPR[MipsReg]); CPU_Message(" regcache: allocate %s to low word of %s",x86_Name(x86lo),CRegName::GPR[MipsReg]);
} else { } else {
x86lo = MipsRegMapLo(MipsReg); x86lo = GetMipsRegMapLo(MipsReg);
if (Is32Bit(MipsReg)) { if (Is32Bit(MipsReg)) {
SetX86Protected(x86lo,TRUE); SetX86Protected(x86lo,TRUE);
x86Hi = FreeX86Reg(); x86Hi = FreeX86Reg();
@ -641,7 +641,7 @@ void CRegInfo::Map_GPR_64bit ( int MipsReg, int MipsRegToLoad)
CPU_Message(" regcache: allocate %s to hi word of %s",x86_Name(x86Hi),CRegName::GPR[MipsReg]); CPU_Message(" regcache: allocate %s to hi word of %s",x86_Name(x86Hi),CRegName::GPR[MipsReg]);
} else { } else {
x86Hi = MipsRegMapHi(MipsReg); x86Hi = GetMipsRegMapHi(MipsReg);
} }
} }
@ -663,32 +663,32 @@ void CRegInfo::Map_GPR_64bit ( int MipsReg, int MipsRegToLoad)
} else if (IsMapped(MipsRegToLoad)) { } else if (IsMapped(MipsRegToLoad)) {
if (Is32Bit(MipsRegToLoad)) { if (Is32Bit(MipsRegToLoad)) {
if (IsSigned(MipsRegToLoad)) { if (IsSigned(MipsRegToLoad)) {
MoveX86RegToX86Reg(MipsRegMapLo(MipsRegToLoad),x86Hi); MoveX86RegToX86Reg(GetMipsRegMapLo(MipsRegToLoad),x86Hi);
ShiftRightSignImmed(x86Hi,31); ShiftRightSignImmed(x86Hi,31);
} else { } else {
XorX86RegToX86Reg(x86Hi,x86Hi); XorX86RegToX86Reg(x86Hi,x86Hi);
} }
if (MipsReg != MipsRegToLoad) { if (MipsReg != MipsRegToLoad) {
MoveX86RegToX86Reg(MipsRegMapLo(MipsRegToLoad),x86lo); MoveX86RegToX86Reg(GetMipsRegMapLo(MipsRegToLoad),x86lo);
} }
} else { } else {
if (MipsReg != MipsRegToLoad) { if (MipsReg != MipsRegToLoad) {
MoveX86RegToX86Reg(MipsRegMapHi(MipsRegToLoad),x86Hi); MoveX86RegToX86Reg(GetMipsRegMapHi(MipsRegToLoad),x86Hi);
MoveX86RegToX86Reg(MipsRegMapLo(MipsRegToLoad),x86lo); MoveX86RegToX86Reg(GetMipsRegMapLo(MipsRegToLoad),x86lo);
} }
} }
} else { } else {
CPU_Message("Map_GPR_64bit 11"); CPU_Message("Map_GPR_64bit 11");
if (Is32Bit(MipsRegToLoad)) { if (Is32Bit(MipsRegToLoad)) {
if (IsSigned(MipsRegToLoad)) { if (IsSigned(MipsRegToLoad)) {
MoveConstToX86reg(MipsRegLo_S(MipsRegToLoad) >> 31,x86Hi); MoveConstToX86reg(GetMipsRegLo_S(MipsRegToLoad) >> 31,x86Hi);
} else { } else {
MoveConstToX86reg(0,x86Hi); MoveConstToX86reg(0,x86Hi);
} }
} else { } else {
MoveConstToX86reg(MipsRegHi(MipsRegToLoad),x86Hi); MoveConstToX86reg(GetMipsRegHi(MipsRegToLoad),x86Hi);
} }
MoveConstToX86reg(MipsRegLo(MipsRegToLoad),x86lo); MoveConstToX86reg(GetMipsRegLo(MipsRegToLoad),x86lo);
} }
} else if (MipsRegToLoad == 0) { } else if (MipsRegToLoad == 0) {
XorX86RegToX86Reg(x86Hi,x86Hi); XorX86RegToX86Reg(x86Hi,x86Hi);
@ -758,7 +758,7 @@ CX86Ops::x86Reg CRegInfo::Map_TempReg (CX86Ops::x86Reg Reg, int MipsReg, BOOL Lo
{ {
continue; continue;
} }
if (MipsRegMapLo(count) == Reg) if (GetMipsRegMapLo(count) == Reg)
{ {
if (NewReg == x86_Unknown) if (NewReg == x86_Unknown)
{ {
@ -773,7 +773,7 @@ CX86Ops::x86Reg CRegInfo::Map_TempReg (CX86Ops::x86Reg Reg, int MipsReg, BOOL Lo
if (MipsReg == count && LoadHiWord == FALSE) { MipsReg = -1; } if (MipsReg == count && LoadHiWord == FALSE) { MipsReg = -1; }
break; break;
} }
if (Is64Bit(count) && MipsRegMapHi(count) == Reg) if (Is64Bit(count) && GetMipsRegMapHi(count) == Reg)
{ {
if (NewReg == x86_Unknown) if (NewReg == x86_Unknown)
{ {
@ -805,9 +805,9 @@ CX86Ops::x86Reg CRegInfo::Map_TempReg (CX86Ops::x86Reg Reg, int MipsReg, BOOL Lo
else if (IsMapped(MipsReg)) else if (IsMapped(MipsReg))
{ {
if (Is64Bit(MipsReg)) { if (Is64Bit(MipsReg)) {
MoveX86RegToX86Reg(MipsRegMapHi(MipsReg),Reg); MoveX86RegToX86Reg(GetMipsRegMapHi(MipsReg),Reg);
} else if (IsSigned(MipsReg)){ } else if (IsSigned(MipsReg)){
MoveX86RegToX86Reg(MipsRegMapLo(MipsReg),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(MipsReg),Reg);
ShiftRightSignImmed(Reg,31); ShiftRightSignImmed(Reg,31);
} else { } else {
MoveConstToX86reg(0,Reg); MoveConstToX86reg(0,Reg);
@ -815,18 +815,18 @@ CX86Ops::x86Reg CRegInfo::Map_TempReg (CX86Ops::x86Reg Reg, int MipsReg, BOOL Lo
} else { } else {
if (Is64Bit(MipsReg)) if (Is64Bit(MipsReg))
{ {
MoveConstToX86reg(MipsRegHi(MipsReg),Reg); MoveConstToX86reg(GetMipsRegHi(MipsReg),Reg);
} else { } else {
MoveConstToX86reg(MipsRegLo_S(MipsReg) >> 31,Reg); MoveConstToX86reg(GetMipsRegLo_S(MipsReg) >> 31,Reg);
} }
} }
} else { } else {
if (IsUnknown(MipsReg)) { if (IsUnknown(MipsReg)) {
MoveVariableToX86reg(&_GPR[MipsReg].UW[0],CRegName::GPR_Lo[MipsReg],Reg); MoveVariableToX86reg(&_GPR[MipsReg].UW[0],CRegName::GPR_Lo[MipsReg],Reg);
} else if (IsMapped(MipsReg)) { } else if (IsMapped(MipsReg)) {
MoveX86RegToX86Reg(MipsRegMapLo(MipsReg),Reg); MoveX86RegToX86Reg(GetMipsRegMapLo(MipsReg),Reg);
} else { } else {
MoveConstToX86reg(MipsRegLo(MipsReg),Reg); MoveConstToX86reg(GetMipsRegLo(MipsReg),Reg);
} }
} }
} }
@ -846,17 +846,17 @@ CX86Ops::x86Reg CRegInfo::Map_TempReg (CX86Ops::x86Reg Reg, int MipsReg, BOOL Lo
void CRegInfo::ProtectGPR(DWORD Reg) { void CRegInfo::ProtectGPR(DWORD Reg) {
if (IsUnknown(Reg) || IsConst(Reg)) { return; } if (IsUnknown(Reg) || IsConst(Reg)) { return; }
if (Is64Bit(Reg)) { if (Is64Bit(Reg)) {
SetX86Protected(MipsRegMapHi(Reg),TRUE); SetX86Protected(GetMipsRegMapHi(Reg),TRUE);
} }
SetX86Protected(MipsRegMapLo(Reg),TRUE); SetX86Protected(GetMipsRegMapLo(Reg),TRUE);
} }
void CRegInfo::UnProtectGPR(DWORD Reg) { void CRegInfo::UnProtectGPR(DWORD Reg) {
if (IsUnknown(Reg) || IsConst(Reg)) { return; } if (IsUnknown(Reg) || IsConst(Reg)) { return; }
if (Is64Bit(Reg)) { if (Is64Bit(Reg)) {
SetX86Protected(MipsRegMapHi(Reg),false); SetX86Protected(GetMipsRegMapHi(Reg),false);
} }
SetX86Protected(MipsRegMapLo(Reg),false); SetX86Protected(GetMipsRegMapLo(Reg),false);
} }
void CRegInfo::ResetX86Protection (void) void CRegInfo::ResetX86Protection (void)
@ -999,43 +999,43 @@ void CRegInfo::UnMap_GPR (DWORD Reg, bool WriteBackValue)
return; return;
} }
if (Is64Bit(Reg)) { if (Is64Bit(Reg)) {
MoveConstToVariable(MipsRegHi(Reg),&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]); MoveConstToVariable(GetMipsRegHi(Reg),&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]);
MoveConstToVariable(MipsRegLo(Reg),&_GPR[Reg].UW[0],CRegName::GPR_Lo[Reg]); MoveConstToVariable(GetMipsRegLo(Reg),&_GPR[Reg].UW[0],CRegName::GPR_Lo[Reg]);
SetMipsRegState(Reg,STATE_UNKNOWN); SetMipsRegState(Reg,STATE_UNKNOWN);
return; return;
} }
if ((MipsRegLo(Reg) & 0x80000000) != 0) { if ((GetMipsRegLo(Reg) & 0x80000000) != 0) {
MoveConstToVariable(0xFFFFFFFF,&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]); MoveConstToVariable(0xFFFFFFFF,&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]);
} else { } else {
MoveConstToVariable(0,&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]); MoveConstToVariable(0,&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]);
} }
MoveConstToVariable(MipsRegLo(Reg),&_GPR[Reg].UW[0],CRegName::GPR_Lo[Reg]); MoveConstToVariable(GetMipsRegLo(Reg),&_GPR[Reg].UW[0],CRegName::GPR_Lo[Reg]);
SetMipsRegState(Reg,STATE_UNKNOWN); SetMipsRegState(Reg,STATE_UNKNOWN);
return; return;
} }
if (Is64Bit(Reg)) { if (Is64Bit(Reg)) {
CPU_Message(" regcache: unallocate %s from %s",x86_Name(MipsRegMapHi(Reg)),CRegName::GPR_Hi[Reg]); CPU_Message(" regcache: unallocate %s from %s",x86_Name(GetMipsRegMapHi(Reg)),CRegName::GPR_Hi[Reg]);
SetX86Mapped(MipsRegMapHi(Reg),NotMapped); SetX86Mapped(GetMipsRegMapHi(Reg),NotMapped);
SetX86Protected(MipsRegMapHi(Reg),FALSE); SetX86Protected(GetMipsRegMapHi(Reg),FALSE);
} }
CPU_Message(" regcache: unallocate %s from %s",x86_Name(MipsRegMapLo(Reg)),CRegName::GPR_Lo[Reg]); CPU_Message(" regcache: unallocate %s from %s",x86_Name(GetMipsRegMapLo(Reg)),CRegName::GPR_Lo[Reg]);
SetX86Mapped(MipsRegMapLo(Reg),NotMapped); SetX86Mapped(GetMipsRegMapLo(Reg),NotMapped);
SetX86Protected(MipsRegMapLo(Reg),FALSE); SetX86Protected(GetMipsRegMapLo(Reg),FALSE);
if (!WriteBackValue) if (!WriteBackValue)
{ {
SetMipsRegState(Reg,STATE_UNKNOWN); SetMipsRegState(Reg,STATE_UNKNOWN);
return; return;
} }
MoveX86regToVariable(MipsRegMapLo(Reg),&_GPR[Reg].UW[0],CRegName::GPR_Lo[Reg]); MoveX86regToVariable(GetMipsRegMapLo(Reg),&_GPR[Reg].UW[0],CRegName::GPR_Lo[Reg]);
if (Is64Bit(Reg)) { if (Is64Bit(Reg)) {
SetMipsRegMapLo(Reg, x86_Unknown); SetMipsRegMapLo(Reg, x86_Unknown);
MoveX86regToVariable(MipsRegMapHi(Reg),&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]); MoveX86regToVariable(GetMipsRegMapHi(Reg),&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]);
SetMipsRegMapHi(Reg,x86_Unknown); SetMipsRegMapHi(Reg,x86_Unknown);
} else { } else {
if (!b32BitCore()) { if (!b32BitCore()) {
if (IsSigned(Reg)) { if (IsSigned(Reg)) {
ShiftRightSignImmed(MipsRegMapLo(Reg),31); ShiftRightSignImmed(GetMipsRegMapLo(Reg),31);
MoveX86regToVariable(MipsRegMapLo(Reg),&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]); MoveX86regToVariable(GetMipsRegMapLo(Reg),&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]);
} else { } else {
MoveConstToVariable(0,&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]); MoveConstToVariable(0,&_GPR[Reg].UW[1],CRegName::GPR_Hi[Reg]);
} }
@ -1086,7 +1086,7 @@ bool CRegInfo::UnMap_X86reg ( CX86Ops::x86Reg Reg )
{ {
continue; continue;
} }
if (Is64Bit(count) && MipsRegMapHi(count) == Reg) if (Is64Bit(count) && GetMipsRegMapHi(count) == Reg)
{ {
if (GetX86Protected(Reg) == FALSE) if (GetX86Protected(Reg) == FALSE)
{ {
@ -1095,7 +1095,7 @@ bool CRegInfo::UnMap_X86reg ( CX86Ops::x86Reg Reg )
} }
break; break;
} }
if (MipsRegMapLo(count) == Reg) if (GetMipsRegMapLo(count) == Reg)
{ {
if (GetX86Protected(Reg) == FALSE) if (GetX86Protected(Reg) == FALSE)
{ {
@ -1140,22 +1140,22 @@ void CRegInfo::WriteBackRegisters ()
case CRegInfo::STATE_CONST_32: case CRegInfo::STATE_CONST_32:
if (!b32BitCore()) if (!b32BitCore())
{ {
if (!bEdiZero && (!MipsRegLo(count) || !(MipsRegLo(count) & 0x80000000))) { if (!bEdiZero && (!GetMipsRegLo(count) || !(GetMipsRegLo(count) & 0x80000000))) {
XorX86RegToX86Reg(x86_EDI, x86_EDI); XorX86RegToX86Reg(x86_EDI, x86_EDI);
bEdiZero = TRUE; bEdiZero = TRUE;
} }
if (!bEsiSign && (MipsRegLo(count) & 0x80000000)) { if (!bEsiSign && (GetMipsRegLo(count) & 0x80000000)) {
MoveConstToX86reg(0xFFFFFFFF, x86_ESI); MoveConstToX86reg(0xFFFFFFFF, x86_ESI);
bEsiSign = TRUE; bEsiSign = TRUE;
} }
if ((MipsRegLo(count) & 0x80000000) != 0) { if ((GetMipsRegLo(count) & 0x80000000) != 0) {
MoveX86regToVariable(x86_ESI,&_GPR[count].UW[1],CRegName::GPR_Hi[count]); MoveX86regToVariable(x86_ESI,&_GPR[count].UW[1],CRegName::GPR_Hi[count]);
} else { } else {
MoveX86regToVariable(x86_EDI,&_GPR[count].UW[1],CRegName::GPR_Hi[count]); MoveX86regToVariable(x86_EDI,&_GPR[count].UW[1],CRegName::GPR_Hi[count]);
} }
} }
if (MipsRegLo(count) == 0) { if (GetMipsRegLo(count) == 0) {
if (b32BitCore()) if (b32BitCore())
{ {
if (!bEdiZero) if (!bEdiZero)
@ -1165,7 +1165,7 @@ void CRegInfo::WriteBackRegisters ()
} }
} }
MoveX86regToVariable(x86_EDI,&_GPR[count].UW[0],CRegName::GPR_Lo[count]); MoveX86regToVariable(x86_EDI,&_GPR[count].UW[0],CRegName::GPR_Lo[count]);
} else if (MipsRegLo(count) == 0xFFFFFFFF) { } else if (GetMipsRegLo(count) == 0xFFFFFFFF) {
if (b32BitCore()) if (b32BitCore())
{ {
if (!bEsiSign) if (!bEsiSign)
@ -1176,34 +1176,34 @@ void CRegInfo::WriteBackRegisters ()
} }
MoveX86regToVariable(x86_ESI,&_GPR[count].UW[0],CRegName::GPR_Lo[count]); MoveX86regToVariable(x86_ESI,&_GPR[count].UW[0],CRegName::GPR_Lo[count]);
} else } else
MoveConstToVariable(MipsRegLo(count),&_GPR[count].UW[0],CRegName::GPR_Lo[count]); MoveConstToVariable(GetMipsRegLo(count),&_GPR[count].UW[0],CRegName::GPR_Lo[count]);
SetMipsRegState(count, CRegInfo::STATE_UNKNOWN); SetMipsRegState(count, CRegInfo::STATE_UNKNOWN);
break; break;
case CRegInfo::STATE_CONST_64: case CRegInfo::STATE_CONST_64:
if (MipsRegLo(count) == 0 || MipsRegHi(count) == 0) { if (GetMipsRegLo(count) == 0 || GetMipsRegHi(count) == 0) {
XorX86RegToX86Reg(x86_EDI, x86_EDI); XorX86RegToX86Reg(x86_EDI, x86_EDI);
bEdiZero = TRUE; bEdiZero = TRUE;
} }
if (MipsRegLo(count) == 0xFFFFFFFF || MipsRegHi(count) == 0xFFFFFFFF) { if (GetMipsRegLo(count) == 0xFFFFFFFF || GetMipsRegHi(count) == 0xFFFFFFFF) {
MoveConstToX86reg(0xFFFFFFFF, x86_ESI); MoveConstToX86reg(0xFFFFFFFF, x86_ESI);
bEsiSign = TRUE; bEsiSign = TRUE;
} }
if (MipsRegHi(count) == 0) { if (GetMipsRegHi(count) == 0) {
MoveX86regToVariable(x86_EDI,&_GPR[count].UW[1],CRegName::GPR_Hi[count]); MoveX86regToVariable(x86_EDI,&_GPR[count].UW[1],CRegName::GPR_Hi[count]);
} else if (MipsRegLo(count) == 0xFFFFFFFF) { } else if (GetMipsRegLo(count) == 0xFFFFFFFF) {
MoveX86regToVariable(x86_ESI,&_GPR[count].UW[1],CRegName::GPR_Hi[count]); MoveX86regToVariable(x86_ESI,&_GPR[count].UW[1],CRegName::GPR_Hi[count]);
} else { } else {
MoveConstToVariable(MipsRegHi(count),&_GPR[count].UW[1],CRegName::GPR_Hi[count]); MoveConstToVariable(GetMipsRegHi(count),&_GPR[count].UW[1],CRegName::GPR_Hi[count]);
} }
if (MipsRegLo(count) == 0) { if (GetMipsRegLo(count) == 0) {
MoveX86regToVariable(x86_EDI,&_GPR[count].UW[0],CRegName::GPR_Lo[count]); MoveX86regToVariable(x86_EDI,&_GPR[count].UW[0],CRegName::GPR_Lo[count]);
} else if (MipsRegLo(count) == 0xFFFFFFFF) { } else if (GetMipsRegLo(count) == 0xFFFFFFFF) {
MoveX86regToVariable(x86_ESI,&_GPR[count].UW[0],CRegName::GPR_Lo[count]); MoveX86regToVariable(x86_ESI,&_GPR[count].UW[0],CRegName::GPR_Lo[count]);
} else { } else {
MoveConstToVariable(MipsRegLo(count),&_GPR[count].UW[0],CRegName::GPR_Lo[count]); MoveConstToVariable(GetMipsRegLo(count),&_GPR[count].UW[0],CRegName::GPR_Lo[count]);
} }
SetMipsRegState(count, CRegInfo::STATE_UNKNOWN); SetMipsRegState(count, CRegInfo::STATE_UNKNOWN);
break; break;

27
Source/Project64/N64 System/Recompiler/Reg Info.h
View File

@ -105,13 +105,12 @@ public:
inline REG_STATE MipsRegState ( int Reg ) const { return m_MIPS_RegState[Reg]; } inline REG_STATE MipsRegState ( int Reg ) const { return m_MIPS_RegState[Reg]; }
inline unsigned _int64 MipsReg ( int Reg ) const { return m_MIPS_RegVal[Reg].UDW; } inline unsigned _int64 MipsReg ( int Reg ) const { return m_MIPS_RegVal[Reg].UDW; }
inline _int64 & MipsReg_S ( int Reg ) { return m_MIPS_RegVal[Reg].DW; } inline _int64 & MipsReg_S ( int Reg ) { return m_MIPS_RegVal[Reg].DW; }
inline DWORD & MipsRegLo ( int Reg ) { return m_MIPS_RegVal[Reg].UW[0]; } inline DWORD GetMipsRegLo ( int Reg ) const { return m_MIPS_RegVal[Reg].UW[0]; }
inline long & MipsRegLo_S ( int Reg ) { return m_MIPS_RegVal[Reg].W[0]; } inline long GetMipsRegLo_S ( int Reg ) const { return m_MIPS_RegVal[Reg].W[0]; }
inline DWORD & MipsRegHi ( int Reg ) { return m_MIPS_RegVal[Reg].UW[1]; } inline DWORD GetMipsRegHi ( int Reg ) const { return m_MIPS_RegVal[Reg].UW[1]; }
inline long & MipsRegHi_S ( int Reg ) { return m_MIPS_RegVal[Reg].W[1]; } inline long GetMipsRegHi_S ( int Reg ) const { return m_MIPS_RegVal[Reg].W[1]; }
inline CX86Ops::x86Reg MipsRegMapLo ( int Reg ) const { return m_RegMapLo[Reg]; } inline CX86Ops::x86Reg GetMipsRegMapLo ( int Reg ) const { return m_RegMapLo[Reg]; }
inline CX86Ops::x86Reg MipsRegMapHi ( int Reg ) const { return m_RegMapHi[Reg]; } inline CX86Ops::x86Reg GetMipsRegMapHi ( int Reg ) const { return m_RegMapHi[Reg]; }
inline bool X86Protected ( x86Reg Reg ) const { return m_x86reg_Protected[Reg]; }
inline DWORD GetX86MapOrder ( x86Reg Reg ) const { return m_x86reg_MapOrder[Reg]; } inline DWORD GetX86MapOrder ( x86Reg Reg ) const { return m_x86reg_MapOrder[Reg]; }
inline bool GetX86Protected ( x86Reg Reg ) const { return m_x86reg_Protected[Reg]; } inline bool GetX86Protected ( x86Reg Reg ) const { return m_x86reg_Protected[Reg]; }
@ -119,15 +118,11 @@ public:
inline DWORD GetBlockCycleCount ( void ) const { return m_CycleCount; } inline DWORD GetBlockCycleCount ( void ) const { return m_CycleCount; }
inline void SetMipsReg ( int Reg, unsigned __int64 value ) { m_MIPS_RegVal[Reg].UDW = value; } inline void SetMipsReg ( int Reg, unsigned __int64 Value ) { m_MIPS_RegVal[Reg].UDW = Value; }
inline void SetMipsRegMapLo ( int MipsReg, x86Reg Reg ) inline void SetMipsRegLo ( int Reg, DWORD Value ) { m_MIPS_RegVal[Reg].UW[0] = Value; }
{ inline void SetMipsRegHi ( int Reg, DWORD Value ) { m_MIPS_RegVal[Reg].UW[1] = Value; }
m_RegMapLo[MipsReg] = Reg; inline void SetMipsRegMapLo ( int MipsReg, x86Reg Reg ) { m_RegMapLo[MipsReg] = Reg; }
} inline void SetMipsRegMapHi ( int MipsReg, x86Reg Reg ) { m_RegMapHi[MipsReg] = Reg; }
inline void SetMipsRegMapHi ( int MipsReg, x86Reg Reg )
{
m_RegMapHi[MipsReg] = Reg;
}
inline void SetMipsRegState ( int MipsReg, REG_STATE State ) { m_MIPS_RegState[MipsReg] = State; } inline void SetMipsRegState ( int MipsReg, REG_STATE State ) { m_MIPS_RegState[MipsReg] = State; }
inline void SetX86MapOrder ( x86Reg Reg, DWORD Order ) { m_x86reg_MapOrder[Reg] = Order; } inline void SetX86MapOrder ( x86Reg Reg, DWORD Order ) { m_x86reg_MapOrder[Reg] = Order; }