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Core: Remove CRegisters::DoTLBReadMiss and CRegisters::DoTLBWriteMiss

This commit is contained in:
zilmar 2023-10-05 09:54:41 +10:30
parent b7311cc611
commit 35105e814e
7 changed files with 26 additions and 31 deletions
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4
Source/Project64-core/N64System/Interpreter/InterpreterCPU.cpp
View File

@ -69,7 +69,7 @@ void CInterpreterCPU::ExecuteCPU()
{ {
if (!g_MMU->MemoryValue32(PROGRAM_COUNTER, Opcode.Value)) if (!g_MMU->MemoryValue32(PROGRAM_COUNTER, Opcode.Value))
{ {
g_Reg->DoTLBReadMiss(PROGRAM_COUNTER); g_Reg->TriggerAddressException(PROGRAM_COUNTER, EXC_RMISS);
PROGRAM_COUNTER = JumpToLocation; PROGRAM_COUNTER = JumpToLocation;
PipelineStage = PIPELINE_STAGE_NORMAL; PipelineStage = PIPELINE_STAGE_NORMAL;
continue; continue;
@ -281,7 +281,7 @@ void CInterpreterCPU::ExecuteOps(int32_t Cycles)
} }
else else
{ {
g_Reg->DoTLBReadMiss(PROGRAM_COUNTER); g_Reg->TriggerAddressException(PROGRAM_COUNTER, EXC_RMISS);
PROGRAM_COUNTER = JumpToLocation; PROGRAM_COUNTER = JumpToLocation;
PipelineStage = PIPELINE_STAGE_NORMAL; PipelineStage = PIPELINE_STAGE_NORMAL;
} }

8
Source/Project64-core/N64System/Interpreter/InterpreterOps.cpp
View File

@ -1091,7 +1091,7 @@ void R4300iOp::SWL()
} }
else else
{ {
g_Reg->DoTLBWriteMiss(Address); g_Reg->TriggerAddressException(Address, EXC_WMISS);
} }
} }
@ -1124,7 +1124,7 @@ void R4300iOp::SDL()
} }
else else
{ {
g_Reg->DoTLBWriteMiss(Address); g_Reg->TriggerAddressException(Address, EXC_WMISS);
} }
} }
@ -1152,7 +1152,7 @@ void R4300iOp::SDR()
} }
else else
{ {
g_Reg->DoTLBWriteMiss(Address); g_Reg->TriggerAddressException(Address, EXC_WMISS);
} }
} }
@ -1170,7 +1170,7 @@ void R4300iOp::SWR()
} }
else else
{ {
g_Reg->DoTLBWriteMiss(Address); g_Reg->TriggerAddressException(Address, EXC_WMISS);
} }
} }

12
Source/Project64-core/N64System/Mips/MemoryVirtualMem.cpp
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@ -588,7 +588,7 @@ bool CMipsMemoryVM::LB_VAddr32(uint32_t VAddr, uint8_t & Value)
uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12]; uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
if (BaseAddress == -1) if (BaseAddress == -1)
{ {
m_Reg.DoTLBReadMiss(VAddr); m_Reg.TriggerAddressException(VAddr, EXC_RMISS);
return false; return false;
} }
return LB_PhysicalAddress(BaseAddress + VAddr, Value); return LB_PhysicalAddress(BaseAddress + VAddr, Value);
@ -599,7 +599,7 @@ bool CMipsMemoryVM::LH_VAddr32(uint32_t VAddr, uint16_t & Value)
uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12]; uint32_t BaseAddress = m_TLB_ReadMap[VAddr >> 12];
if (BaseAddress == -1) if (BaseAddress == -1)
{ {
m_Reg.DoTLBReadMiss(VAddr); m_Reg.TriggerAddressException(VAddr, EXC_RMISS);
return false; return false;
} }
return LH_PhysicalAddress(BaseAddress + VAddr, Value); return LH_PhysicalAddress(BaseAddress + VAddr, Value);
@ -742,7 +742,7 @@ bool CMipsMemoryVM::SB_VAddr32(uint32_t VAddr, uint32_t Value)
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12]; uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1) if (BaseAddress == -1)
{ {
m_Reg.DoTLBWriteMiss(VAddr); m_Reg.TriggerAddressException(VAddr, EXC_WMISS);
return false; return false;
} }
return SB_PhysicalAddress(BaseAddress + VAddr, Value); return SB_PhysicalAddress(BaseAddress + VAddr, Value);
@ -753,7 +753,7 @@ bool CMipsMemoryVM::SH_VAddr32(uint32_t VAddr, uint32_t Value)
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12]; uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1) if (BaseAddress == -1)
{ {
m_Reg.DoTLBWriteMiss(VAddr); m_Reg.TriggerAddressException(VAddr, EXC_WMISS);
return false; return false;
} }
return SH_PhysicalAddress(BaseAddress + VAddr, Value); return SH_PhysicalAddress(BaseAddress + VAddr, Value);
@ -764,7 +764,7 @@ bool CMipsMemoryVM::SW_VAddr32(uint32_t VAddr, uint32_t Value)
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12]; uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1) if (BaseAddress == -1)
{ {
m_Reg.DoTLBWriteMiss(VAddr); m_Reg.TriggerAddressException(VAddr, EXC_WMISS);
return false; return false;
} }
return SW_PhysicalAddress(BaseAddress + VAddr, Value); return SW_PhysicalAddress(BaseAddress + VAddr, Value);
@ -775,7 +775,7 @@ bool CMipsMemoryVM::SD_VAddr32(uint32_t VAddr, uint64_t Value)
uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12]; uint32_t BaseAddress = m_TLB_WriteMap[VAddr >> 12];
if (BaseAddress == -1) if (BaseAddress == -1)
{ {
m_Reg.DoTLBWriteMiss(VAddr); m_Reg.TriggerAddressException(VAddr, EXC_WMISS);
return false; return false;
} }
return SD_PhysicalAddress(BaseAddress + VAddr, Value); return SD_PhysicalAddress(BaseAddress + VAddr, Value);

16
Source/Project64-core/N64System/Mips/Register.cpp
View File

@ -781,18 +781,14 @@ bool CRegisters::DoIntrException()
return true; return true;
} }
void CRegisters::DoTLBReadMiss(uint64_t BadVaddr) void CRegisters::TriggerAddressException(uint64_t Address, uint32_t ExceptionCode)
{ {
TriggerAddressException(BadVaddr, EXC_RMISS, !m_TLB.AddressDefined(BadVaddr)); bool SpecialOffset = false;
if (ExceptionCode == EXC_RMISS || ExceptionCode == EXC_WMISS)
{
SpecialOffset = !m_TLB.AddressDefined(Address);
} }
void CRegisters::DoTLBWriteMiss(uint64_t BadVaddr)
{
TriggerAddressException(BadVaddr, EXC_WMISS, !m_TLB.AddressDefined(BadVaddr));
}
void CRegisters::TriggerAddressException(uint64_t Address, uint32_t ExceptionCode, bool SpecialOffset)
{
BAD_VADDR_REGISTER = Address; BAD_VADDR_REGISTER = Address;
ENTRYHI_REGISTER.VPN2 = Address >> 13; ENTRYHI_REGISTER.VPN2 = Address >> 13;
ENTRYHI_REGISTER.R = Address >> 62; ENTRYHI_REGISTER.R = Address >> 62;
@ -801,7 +797,7 @@ void CRegisters::TriggerAddressException(uint64_t Address, uint32_t ExceptionCod
XCONTEXT_REGISTER.R = Address >> 62; XCONTEXT_REGISTER.R = Address >> 62;
TriggerException(ExceptionCode, 0); TriggerException(ExceptionCode, 0);
if (SpecialOffset && STATUS_REGISTER.ExceptionLevel == 0) if (SpecialOffset)
{ {
m_System.m_JumpToLocation = (m_System.m_JumpToLocation & 0xFFFF0000); m_System.m_JumpToLocation = (m_System.m_JumpToLocation & 0xFFFF0000);
switch (STATUS_REGISTER.PrivilegeMode) switch (STATUS_REGISTER.PrivilegeMode)

4
Source/Project64-core/N64System/Mips/Register.h
View File

@ -468,12 +468,10 @@ public:
void CheckInterrupts(); void CheckInterrupts();
void DoAddressError(uint64_t BadVaddr, bool FromRead); void DoAddressError(uint64_t BadVaddr, bool FromRead);
bool DoIntrException(); bool DoIntrException();
void DoTLBReadMiss(uint64_t BadVaddr);
void DoTLBWriteMiss(uint64_t BadVaddr);
void FixFpuLocations(); void FixFpuLocations();
void Reset(bool bPostPif, CMipsMemoryVM & MMU); void Reset(bool bPostPif, CMipsMemoryVM & MMU);
void SetAsCurrentSystem(); void SetAsCurrentSystem();
void TriggerAddressException(uint64_t Address, uint32_t ExceptionCode, bool SpecialOffset = false); void TriggerAddressException(uint64_t Address, uint32_t ExceptionCode);
void TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor = 0); void TriggerException(uint32_t ExceptionCode, uint32_t Coprocessor = 0);
uint64_t Cop0_MF(COP0Reg Reg); uint64_t Cop0_MF(COP0Reg Reg);

6
Source/Project64-core/N64System/Recompiler/Recompiler.cpp
View File

@ -87,7 +87,7 @@ void CRecompiler::RecompilerMain_VirtualTable()
{ {
if (!m_MMU.ValidVaddr(PC)) if (!m_MMU.ValidVaddr(PC))
{ {
m_Registers.DoTLBReadMiss(PC); m_Registers.TriggerAddressException(PC, EXC_RMISS);
PC = g_System->m_JumpToLocation; PC = g_System->m_JumpToLocation;
g_System->m_PipelineStage = PIPELINE_STAGE_NORMAL; g_System->m_PipelineStage = PIPELINE_STAGE_NORMAL;
if (!m_MMU.ValidVaddr(PC)) if (!m_MMU.ValidVaddr(PC))
@ -149,7 +149,7 @@ void CRecompiler::RecompilerMain_Lookup()
{ {
if (!m_MMU.VAddrToPAddr(PROGRAM_COUNTER, PhysicalAddr)) if (!m_MMU.VAddrToPAddr(PROGRAM_COUNTER, PhysicalAddr))
{ {
m_Registers.DoTLBReadMiss(PROGRAM_COUNTER); m_Registers.TriggerAddressException(PROGRAM_COUNTER, EXC_RMISS);
if (!m_MMU.VAddrToPAddr(PROGRAM_COUNTER, PhysicalAddr)) if (!m_MMU.VAddrToPAddr(PROGRAM_COUNTER, PhysicalAddr))
{ {
g_Notify->DisplayError(stdstr_f("Failed to translate PC to a PAddr: %X\n\nEmulation stopped", PROGRAM_COUNTER).c_str()); g_Notify->DisplayError(stdstr_f("Failed to translate PC to a PAddr: %X\n\nEmulation stopped", PROGRAM_COUNTER).c_str());
@ -208,7 +208,7 @@ void CRecompiler::RecompilerMain_Lookup_validate()
{ {
if (!m_MMU.VAddrToPAddr(PC, PhysicalAddr)) if (!m_MMU.VAddrToPAddr(PC, PhysicalAddr))
{ {
m_Registers.DoTLBReadMiss(PC); m_Registers.TriggerAddressException(PC, EXC_RMISS);
if (!m_MMU.VAddrToPAddr(PC, PhysicalAddr)) if (!m_MMU.VAddrToPAddr(PC, PhysicalAddr))
{ {
g_Notify->DisplayError(stdstr_f("Failed to translate PC to a PAddr: %X\n\nEmulation stopped", PC).c_str()); g_Notify->DisplayError(stdstr_f("Failed to translate PC to a PAddr: %X\n\nEmulation stopped", PC).c_str());

5
Source/Project64-core/N64System/Recompiler/x86/x86RecompilerOps.cpp
View File

@ -50,7 +50,7 @@ void CX86RecompilerOps::x86CompilerBreakPoint()
uint32_t OpcodeValue; uint32_t OpcodeValue;
if (!g_MMU->MemoryValue32(g_Reg->m_PROGRAM_COUNTER, OpcodeValue)) if (!g_MMU->MemoryValue32(g_Reg->m_PROGRAM_COUNTER, OpcodeValue))
{ {
g_Reg->DoTLBReadMiss(g_Reg->m_PROGRAM_COUNTER); g_Reg->TriggerAddressException(g_Reg->m_PROGRAM_COUNTER, EXC_RMISS);
g_Reg->m_PROGRAM_COUNTER = g_System->JumpToLocation(); g_Reg->m_PROGRAM_COUNTER = g_System->JumpToLocation();
g_System->m_PipelineStage = PIPELINE_STAGE_NORMAL; g_System->m_PipelineStage = PIPELINE_STAGE_NORMAL;
continue; continue;
@ -9704,9 +9704,10 @@ void CX86RecompilerOps::CompileExit(uint32_t JumpPC, uint32_t TargetPC, CRegInfo
break; break;
case ExitReason_TLBReadMiss: case ExitReason_TLBReadMiss:
m_Assembler.MoveConstToVariable(&g_System->m_PipelineStage, "System->m_PipelineStage", InDelaySlot ? PIPELINE_STAGE_JUMP : PIPELINE_STAGE_NORMAL); m_Assembler.MoveConstToVariable(&g_System->m_PipelineStage, "System->m_PipelineStage", InDelaySlot ? PIPELINE_STAGE_JUMP : PIPELINE_STAGE_NORMAL);
m_Assembler.PushImm32("EXC_RMISS", EXC_RMISS);
m_Assembler.MoveVariableToX86reg(asmjit::x86::edx, g_TLBLoadAddress, "g_TLBLoadAddress"); m_Assembler.MoveVariableToX86reg(asmjit::x86::edx, g_TLBLoadAddress, "g_TLBLoadAddress");
m_Assembler.push(asmjit::x86::edx); m_Assembler.push(asmjit::x86::edx);
m_Assembler.CallThis((uint32_t)g_Reg, AddressOf(&CRegisters::DoTLBReadMiss), "CRegisters::DoTLBReadMiss", 12); m_Assembler.CallThis((uint32_t)g_Reg, AddressOf(&CRegisters::TriggerAddressException), "CRegisters::TriggerAddressException", 12);
m_Assembler.MoveVariableToX86reg(asmjit::x86::edx, &g_System->m_JumpToLocation, "System->m_JumpToLocation"); m_Assembler.MoveVariableToX86reg(asmjit::x86::edx, &g_System->m_JumpToLocation, "System->m_JumpToLocation");
m_Assembler.MoveX86regToVariable(&g_Reg->m_PROGRAM_COUNTER, "PROGRAM_COUNTER", asmjit::x86::edx); m_Assembler.MoveX86regToVariable(&g_Reg->m_PROGRAM_COUNTER, "PROGRAM_COUNTER", asmjit::x86::edx);
m_Assembler.MoveConstToVariable(&g_System->m_PipelineStage, "g_System->m_PipelineStage", PIPELINE_STAGE_NORMAL); m_Assembler.MoveConstToVariable(&g_System->m_PipelineStage, "g_System->m_PipelineStage", PIPELINE_STAGE_NORMAL);