2010-05-30 01:54:42 +00:00
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class CRegInfo :
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2012-10-14 01:05:52 +00:00
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private CGameSettings,
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2010-06-04 06:25:07 +00:00
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private CX86Ops,
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private CSystemRegisters
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2010-05-30 01:54:42 +00:00
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{
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public:
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//enums
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enum REG_STATE {
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2012-10-20 23:19:09 +00:00
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STATE_UNKNOWN = 0x00,
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STATE_KNOWN_VALUE = 0x01,
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STATE_X86_MAPPED = 0x02,
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STATE_SIGN = 0x04,
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STATE_32BIT = 0x08,
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STATE_MODIFIED = 0x10,
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2010-05-30 01:54:42 +00:00
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STATE_MAPPED_64 = (STATE_KNOWN_VALUE | STATE_X86_MAPPED), // = 3
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STATE_MAPPED_32_ZERO = (STATE_KNOWN_VALUE | STATE_X86_MAPPED | STATE_32BIT), // = 11
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STATE_MAPPED_32_SIGN = (STATE_KNOWN_VALUE | STATE_X86_MAPPED | STATE_32BIT | STATE_SIGN), // = 15
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STATE_CONST_32 = (STATE_KNOWN_VALUE | STATE_32BIT | STATE_SIGN), // = 13
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STATE_CONST_64 = (STATE_KNOWN_VALUE), // = 1
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};
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enum REG_MAPPED {
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NotMapped = 0,
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GPR_Mapped = 1,
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Temp_Mapped = 2,
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Stack_Mapped = 3,
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};
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enum FPU_STATE {
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2010-06-04 06:25:07 +00:00
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FPU_Any = -1,
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FPU_Unknown = 0,
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FPU_Dword = 1,
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FPU_Qword = 2,
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FPU_Float = 3,
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FPU_Double = 4,
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2010-05-30 01:54:42 +00:00
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};
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enum FPU_ROUND {
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2010-06-04 06:25:07 +00:00
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RoundUnknown = -1,
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RoundDefault = 0,
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RoundTruncate = 1,
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RoundNearest = 2,
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RoundDown = 3,
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RoundUp = 4,
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2010-05-30 01:54:42 +00:00
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};
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public:
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2012-10-14 01:05:52 +00:00
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CRegInfo();
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CRegInfo(const CRegInfo&);
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~CRegInfo();
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CRegInfo& operator=(const CRegInfo&);
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2010-05-30 01:54:42 +00:00
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bool operator==(const CRegInfo& right) const;
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bool operator!=(const CRegInfo& right) const;
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static REG_STATE ConstantsType ( __int64 Value );
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void FixRoundModel ( FPU_ROUND RoundMethod );
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2010-06-04 06:25:07 +00:00
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void ChangeFPURegFormat ( int Reg, FPU_STATE OldFormat, FPU_STATE NewFormat, FPU_ROUND RoundingModel );
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void Load_FPR_ToTop ( int Reg, int RegToLoad, FPU_STATE Format);
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BOOL RegInStack ( int Reg, FPU_STATE Format );
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void UnMap_AllFPRs ( void );
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void UnMap_FPR ( int Reg, int WriteBackValue );
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x86FpuValues StackPosition ( int Reg );
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2010-05-30 01:54:42 +00:00
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x86Reg FreeX86Reg ( void );
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x86Reg Free8BitX86Reg ( void );
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2012-10-22 10:36:57 +00:00
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void Map_GPR_32bit ( int MipsReg, bool SignValue, int MipsRegToLoad );
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2010-05-30 01:54:42 +00:00
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void Map_GPR_64bit ( int MipsReg, int MipsRegToLoad );
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2010-10-29 03:20:25 +00:00
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x86Reg Get_MemoryStack ( void ) const;
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x86Reg Map_MemoryStack ( x86Reg Reg, bool bMapRegister, bool LoadValue = true );
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2010-05-30 01:54:42 +00:00
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x86Reg Map_TempReg ( x86Reg Reg, int MipsReg, BOOL LoadHiWord );
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void ProtectGPR ( DWORD Reg );
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2010-05-31 00:21:08 +00:00
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void UnProtectGPR ( DWORD Reg );
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2010-05-30 01:54:42 +00:00
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void ResetX86Protection ( void );
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x86Reg UnMap_TempReg ( void );
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void UnMap_GPR ( DWORD Reg, bool WriteBackValue );
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bool UnMap_X86reg ( x86Reg Reg );
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void WriteBackRegisters ( void );
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2012-10-04 11:01:10 +00:00
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inline bool IsKnown(int Reg) const { return ((MipsRegState(Reg) & STATE_KNOWN_VALUE) != 0); }
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inline bool IsUnknown(int Reg) const { return ((MipsRegState(Reg) & STATE_KNOWN_VALUE) == 0); }
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2012-10-20 23:19:09 +00:00
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inline bool IsModified(int Reg) const { return ((MipsRegState(Reg) & STATE_MODIFIED) != 0); }
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2010-05-30 01:54:42 +00:00
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2012-10-04 11:01:10 +00:00
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inline bool IsMapped(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_X86_MAPPED)); }
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inline bool IsConst(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_X86_MAPPED)) == STATE_KNOWN_VALUE); }
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2010-05-30 01:54:42 +00:00
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2012-10-04 11:01:10 +00:00
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inline bool IsSigned(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_SIGN)) == (STATE_KNOWN_VALUE | STATE_SIGN)); }
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inline bool IsUnsigned(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_SIGN)) == STATE_KNOWN_VALUE); }
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2010-05-30 01:54:42 +00:00
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2012-10-04 11:01:10 +00:00
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inline bool Is32Bit(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT)) == (STATE_KNOWN_VALUE | STATE_32BIT)); }
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inline bool Is64Bit(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT)) == STATE_KNOWN_VALUE); }
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2010-05-30 01:54:42 +00:00
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2012-10-04 11:01:10 +00:00
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inline bool Is32BitMapped(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)); }
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inline bool Is64BitMapped(int Reg) const { return ((MipsRegState(Reg) & (STATE_KNOWN_VALUE | STATE_32BIT | STATE_X86_MAPPED)) == (STATE_KNOWN_VALUE | STATE_X86_MAPPED)); }
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2010-05-30 01:54:42 +00:00
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2012-10-14 01:05:52 +00:00
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inline _int64 cMipsReg_S ( int Reg ) const { return m_MIPS_RegVal[Reg].DW; }
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inline DWORD cMipsRegLo ( int Reg ) const { return m_MIPS_RegVal[Reg].UW[0]; }
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inline long cMipsRegLo_S ( int Reg ) const { return m_MIPS_RegVal[Reg].W[0]; }
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inline DWORD cMipsRegHi ( int Reg ) const { return m_MIPS_RegVal[Reg].UW[1]; }
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inline long cMipsRegHi_S ( int Reg ) const { return m_MIPS_RegVal[Reg].W[1]; }
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inline REG_STATE MipsRegState ( int Reg ) const { return m_MIPS_RegState[Reg]; }
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inline unsigned _int64 MipsReg ( int Reg ) const { return m_MIPS_RegVal[Reg].UDW; }
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inline _int64 & MipsReg_S ( int Reg ) { return m_MIPS_RegVal[Reg].DW; }
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inline DWORD & MipsRegLo ( int Reg ) { return m_MIPS_RegVal[Reg].UW[0]; }
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inline long & MipsRegLo_S ( int Reg ) { return m_MIPS_RegVal[Reg].W[0]; }
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inline DWORD & MipsRegHi ( int Reg ) { return m_MIPS_RegVal[Reg].UW[1]; }
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inline long & MipsRegHi_S ( int Reg ) { return m_MIPS_RegVal[Reg].W[1]; }
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inline CX86Ops::x86Reg MipsRegMapLo ( int Reg ) const { return m_RegMapLo[Reg]; }
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inline CX86Ops::x86Reg MipsRegMapHi ( int Reg ) const { return m_RegMapHi[Reg]; }
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inline bool X86Protected ( x86Reg Reg ) const { return m_x86reg_Protected[Reg]; }
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inline DWORD GetX86MapOrder ( x86Reg Reg ) const { return m_x86reg_MapOrder[Reg]; }
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inline bool GetX86Protected ( x86Reg Reg ) const { return m_x86reg_Protected[Reg]; }
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inline REG_MAPPED GetX86Mapped ( x86Reg Reg ) const { return m_x86reg_MappedTo[Reg]; }
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2010-07-23 10:45:35 +00:00
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inline DWORD GetBlockCycleCount ( void ) const { return m_CycleCount; }
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2012-10-14 01:05:52 +00:00
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inline void SetMipsReg ( int Reg, unsigned __int64 value ) { m_MIPS_RegVal[Reg].UDW = value; }
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2012-10-04 11:01:10 +00:00
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inline void SetMipsRegMapLo ( int MipsReg, x86Reg Reg )
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{
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2012-10-14 01:05:52 +00:00
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m_RegMapLo[MipsReg] = Reg;
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2012-10-04 11:01:10 +00:00
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}
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inline void SetMipsRegMapHi ( int MipsReg, x86Reg Reg )
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{
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2012-10-14 01:05:52 +00:00
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m_RegMapHi[MipsReg] = Reg;
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2012-10-04 11:01:10 +00:00
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}
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2012-10-14 01:05:52 +00:00
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inline void SetMipsRegState ( int MipsReg, REG_STATE State ) { m_MIPS_RegState[MipsReg] = State; }
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2012-10-04 11:01:10 +00:00
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2012-10-14 01:05:52 +00:00
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inline void SetX86MapOrder ( x86Reg Reg, DWORD Order ) { m_x86reg_MapOrder[Reg] = Order; }
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inline void SetX86Protected ( x86Reg Reg, bool Protected ) { m_x86reg_Protected[Reg] = Protected; }
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inline void SetX86Mapped ( x86Reg Reg, REG_MAPPED Mapping ) { m_x86reg_MappedTo[Reg] = Mapping; }
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2010-05-30 01:54:42 +00:00
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2012-10-04 11:01:10 +00:00
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2010-05-30 01:54:42 +00:00
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inline void SetBlockCycleCount ( DWORD CyleCount ) { m_CycleCount = CyleCount; }
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2012-10-14 01:05:52 +00:00
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inline int & StackTopPos ( void ) { return m_Stack_TopPos; }
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2012-10-04 20:28:59 +00:00
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inline int & FpuMappedTo( int Reg) { return x86fpu_MappedTo[Reg]; }
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2010-05-30 01:54:42 +00:00
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inline FPU_STATE & FpuState(int Reg) { return x86fpu_State[Reg]; }
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inline FPU_ROUND & FpuRoundingModel(int Reg) { return x86fpu_RoundingModel[Reg]; }
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2012-10-14 01:05:52 +00:00
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inline bool & FpuBeenUsed (void ) { return m_Fpu_Used; }
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2010-07-23 10:45:35 +00:00
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inline FPU_ROUND GetRoundingModel ( void ) const { return m_RoundingModel; }
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inline void SetRoundingModel ( FPU_ROUND RoundingModel ) { m_RoundingModel = RoundingModel; }
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2010-05-30 01:54:42 +00:00
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private:
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2012-10-14 01:05:52 +00:00
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const char * RoundingModelName ( FPU_ROUND RoundType );
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2010-06-04 06:25:07 +00:00
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x86Reg UnMap_8BitTempReg ( void );
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2010-05-30 01:54:42 +00:00
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//r4k
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2012-10-14 01:05:52 +00:00
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REG_STATE m_MIPS_RegState[32];
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MIPS_DWORD m_MIPS_RegVal[32];
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x86Reg m_RegMapHi[32];
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x86Reg m_RegMapLo[32];
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REG_MAPPED m_x86reg_MappedTo[10];
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DWORD m_x86reg_MapOrder[10];
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bool m_x86reg_Protected[10];
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2010-05-30 01:54:42 +00:00
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DWORD m_CycleCount;
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//FPU
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2012-10-14 01:05:52 +00:00
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int m_Stack_TopPos;
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2012-10-04 20:28:59 +00:00
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int x86fpu_MappedTo[8];
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2010-05-30 01:54:42 +00:00
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FPU_STATE x86fpu_State[8];
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2010-06-14 21:14:58 +00:00
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BOOL x86fpu_StateChanged[8];
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2010-05-30 01:54:42 +00:00
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FPU_ROUND x86fpu_RoundingModel[8];
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2012-10-14 01:05:52 +00:00
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bool m_Fpu_Used;
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2010-07-23 10:45:35 +00:00
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FPU_ROUND m_RoundingModel;
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2010-05-30 01:54:42 +00:00
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static unsigned int m_fpuControl;
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};
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