2015-11-13 13:23:43 +00:00
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#include "stdafx.h"
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2016-01-13 07:23:22 +00:00
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#include <Project64-core/Logging.h>
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2015-12-21 19:41:08 +00:00
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2015-12-21 19:46:04 +00:00
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#include <stdio.h>
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#include <stdarg.h>
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2015-11-13 13:23:43 +00:00
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#include <Common/path.h>
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2015-12-06 09:59:58 +00:00
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#include <Project64-core/N64System/SystemGlobals.h>
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#include <Project64-core/N64System/Mips/TranslateVaddr.h>
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2015-12-21 07:35:22 +00:00
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#include <Project64-core/N64System/Mips/MemoryVirtualMem.h>
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2021-04-14 05:34:15 +00:00
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#include <Project64-core/N64System/N64Rom.h>
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2015-11-13 13:23:43 +00:00
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2021-04-12 11:35:39 +00:00
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CFile * CLogging::m_hLogFile = nullptr;
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2015-11-13 13:23:43 +00:00
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void CLogging::Log_LW(uint32_t PC, uint32_t VAddr)
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{
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2015-12-21 07:16:29 +00:00
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if (!GenerateLog())
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{
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return;
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}
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if (VAddr < 0xA0000000 || VAddr >= 0xC0000000)
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{
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uint32_t PAddr;
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if (!g_TransVaddr->TranslateVaddr(VAddr, PAddr))
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{
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if (LogUnknown())
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{
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LogMessage("%08X: read from unknown ??? (%08X)", PC, VAddr);
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}
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return;
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}
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VAddr = PAddr + 0xA0000000;
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}
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uint32_t Value;
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if (VAddr >= 0xA0000000 && VAddr < (0xA0000000 + g_MMU->RdramSize()))
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{
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return;
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}
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if (VAddr >= 0xA3F00000 && VAddr <= 0xA3F00024)
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{
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2022-02-21 09:17:14 +00:00
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return;
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2015-12-21 07:16:29 +00:00
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}
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if (VAddr >= 0xA4000000 && VAddr <= 0xA4001FFC)
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{
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return;
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}
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if (VAddr == 0xA4080000)
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{
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return;
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}
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if (VAddr >= 0xA4100000 && VAddr <= 0xA410001C)
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{
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2022-02-21 11:26:25 +00:00
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return;
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2015-12-21 07:16:29 +00:00
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}
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if (VAddr >= 0xA4300000 && VAddr <= 0xA430000C)
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{
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2022-03-04 12:23:30 +00:00
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return;
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2015-12-21 07:16:29 +00:00
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}
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if (VAddr >= 0xA4400000 && VAddr <= 0xA4400034)
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{
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2022-03-07 23:48:56 +00:00
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return;
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2015-12-21 07:16:29 +00:00
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}
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if (VAddr >= 0xA4500000 && VAddr <= 0xA4500014)
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{
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2022-03-21 00:29:02 +00:00
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return;
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2015-12-21 07:16:29 +00:00
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}
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if (VAddr == 0xA4800000)
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{
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if (!LogSerialInterface())
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{
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return;
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}
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g_MMU->LW_VAddr(VAddr, Value);
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LogMessage("%08X: read from SI_DRAM_ADDR_REG (%08X)", PC, Value);
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return;
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}
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if (VAddr == 0xA4800004)
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{
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if (!LogSerialInterface())
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{
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return;
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}
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g_MMU->LW_VAddr(VAddr, Value);
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LogMessage("%08X: read from SI_PIF_ADDR_RD64B_REG (%08X)", PC, Value);
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return;
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}
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if (VAddr == 0xA4800010)
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{
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if (!LogSerialInterface())
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{
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return;
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}
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g_MMU->LW_VAddr(VAddr, Value);
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LogMessage("%08X: read from SI_PIF_ADDR_WR64B_REG (%08X)", PC, Value);
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return;
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}
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if (VAddr == 0xA4800018)
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{
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if (!LogSerialInterface())
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{
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return;
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}
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g_MMU->LW_VAddr(VAddr, Value);
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LogMessage("%08X: read from SI_STATUS_REG (%08X)", PC, Value);
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return;
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}
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if (VAddr >= 0xBFC00000 && VAddr <= 0xBFC007C0)
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{
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return;
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}
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if (VAddr >= 0xBFC007C0 && VAddr <= 0xBFC007FC)
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{
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if (!LogPRDirectMemLoads())
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{
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return;
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}
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g_MMU->LW_VAddr(VAddr, Value);
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2021-04-02 07:33:39 +00:00
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LogMessage("%08X: read word from PIF RAM at 0x%X (%08X)", PC, VAddr - 0xBFC007C0, Value);
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2015-12-21 07:16:29 +00:00
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return;
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}
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if (VAddr >= 0xB0000040 && ((VAddr - 0xB0000000) < g_Rom->GetRomSize()))
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{
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return;
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}
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if (VAddr >= 0xB0000000 && VAddr < 0xB0000040)
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{
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if (!LogRomHeader())
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{
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return;
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}
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g_MMU->LW_VAddr(VAddr, Value);
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switch (VAddr)
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{
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2021-04-02 07:33:39 +00:00
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case 0xB0000004: LogMessage("%08X: read from ROM clock rate (%08X)", PC, Value); break;
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case 0xB0000008: LogMessage("%08X: read from ROM boot address offset (%08X)", PC, Value); break;
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case 0xB000000C: LogMessage("%08X: read from ROM release offset (%08X)", PC, Value); break;
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case 0xB0000010: LogMessage("%08X: read from ROM CRC1 (%08X)", PC, Value); break;
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case 0xB0000014: LogMessage("%08X: read from ROM CRC2 (%08X)", PC, Value); break;
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default: LogMessage("%08X: read from ROM header 0x%X (%08X)", PC, VAddr & 0xFF, Value); break;
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2015-12-21 07:16:29 +00:00
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}
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return;
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}
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if (!LogUnknown())
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{
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return;
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}
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LogMessage("%08X: read from unknown ??? (%08X)", PC, VAddr);
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2015-11-13 13:23:43 +00:00
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}
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void CLogging::Log_SW(uint32_t PC, uint32_t VAddr, uint32_t Value)
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{
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2015-12-21 07:16:29 +00:00
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if (!GenerateLog())
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{
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return;
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}
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if (VAddr < 0xA0000000 || VAddr >= 0xC0000000)
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{
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uint32_t PAddr;
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if (!g_TransVaddr->TranslateVaddr(VAddr, PAddr))
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{
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if (LogUnknown())
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{
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LogMessage("%08X: Writing 0x%08X to %08X", PC, Value, VAddr);
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}
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return;
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}
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VAddr = PAddr + 0xA0000000;
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}
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if (VAddr >= 0xA0000000 && VAddr < (0xA0000000 + g_MMU->RdramSize()))
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{
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return;
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}
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if (VAddr >= 0xA3F00000 && VAddr <= 0xA3F00024)
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{
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}
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if (VAddr >= 0xA4000000 && VAddr <= 0xA4001FFC)
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{
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return;
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}
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if (VAddr >= 0xA4040000 && VAddr <= 0xA404001C)
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{
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2022-01-24 12:43:10 +00:00
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return;
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2015-12-21 07:16:29 +00:00
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}
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if (VAddr == 0xA4080000)
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{
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2022-01-24 12:43:10 +00:00
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return;
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2015-12-21 07:16:29 +00:00
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}
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if (VAddr >= 0xA4100000 && VAddr <= 0xA410001C)
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{
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2022-02-21 11:26:25 +00:00
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return;
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2015-12-21 07:16:29 +00:00
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}
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if (VAddr >= 0xA4200000 && VAddr <= 0xA420000C)
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{
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if (!LogDPSRegisters())
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{
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return;
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}
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switch (VAddr)
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{
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case 0xA4200000: LogMessage("%08X: Writing 0x%08X to DPS_TBIST_REG", PC, Value); return;
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case 0xA4200004: LogMessage("%08X: Writing 0x%08X to DPS_TEST_MODE_REG", PC, Value); return;
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case 0xA4200008: LogMessage("%08X: Writing 0x%08X to DPS_BUFTEST_ADDR_REG", PC, Value); return;
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case 0xA420000C: LogMessage("%08X: Writing 0x%08X to DPS_BUFTEST_DATA_REG", PC, Value); return;
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}
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}
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2022-03-21 00:29:02 +00:00
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if ((VAddr >= 0xA4300000 && VAddr <= 0xA430000C) ||
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(VAddr >= 0xA4400000 && VAddr <= 0xA4400034) ||
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(VAddr >= 0xA4500000 && VAddr <= 0xA4500014))
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2015-12-21 07:16:29 +00:00
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{
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2022-03-07 23:48:56 +00:00
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return;
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2015-12-21 07:16:29 +00:00
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}
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if (VAddr == 0xA4800000)
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{
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if (!LogSerialInterface())
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{
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return;
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}
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LogMessage("%08X: Writing 0x%08X to SI_DRAM_ADDR_REG", PC, Value); return;
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}
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if (VAddr == 0xA4800004)
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{
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if (LogPRDMAOperations())
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{
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2021-04-02 07:33:39 +00:00
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LogMessage("%08X: A DMA transfer from the PIF RAM has occurred", PC);
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2015-12-21 07:16:29 +00:00
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}
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if (!LogSerialInterface())
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{
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return;
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}
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LogMessage("%08X: Writing 0x%08X to SI_PIF_ADDR_RD64B_REG", PC, Value); return;
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}
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if (VAddr == 0xA4800010)
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{
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if (LogPRDMAOperations())
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{
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2021-04-02 07:33:39 +00:00
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LogMessage("%08X: A DMA transfer to the PIF RAM has occurred", PC);
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2015-12-21 07:16:29 +00:00
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}
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if (!LogSerialInterface())
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{
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return;
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}
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LogMessage("%08X: Writing 0x%08X to SI_PIF_ADDR_WR64B_REG", PC, Value); return;
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}
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if (VAddr == 0xA4800018)
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{
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if (!LogSerialInterface())
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{
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return;
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}
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LogMessage("%08X: Writing 0x%08X to SI_STATUS_REG", PC, Value); return;
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}
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if (VAddr >= 0xBFC007C0 && VAddr <= 0xBFC007FC)
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{
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if (!LogPRDirectMemStores())
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{
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return;
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}
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2021-04-02 07:33:39 +00:00
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LogMessage("%08X: Writing 0x%08X to PIF RAM at 0x%X", PC, Value, VAddr - 0xBFC007C0);
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2015-12-21 07:16:29 +00:00
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return;
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}
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if (!LogUnknown())
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{
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return;
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}
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LogMessage("%08X: Writing 0x%08X to %08X ????", PC, Value, VAddr);
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2015-11-13 13:23:43 +00:00
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}
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void CLogging::LogMessage(const char * Message, ...)
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{
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2015-12-21 07:16:29 +00:00
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char Msg[400];
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va_list ap;
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2015-11-13 13:23:43 +00:00
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2015-12-21 07:16:29 +00:00
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if (!g_Settings->LoadBool(Debugger_Enabled))
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{
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return;
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}
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2021-04-12 11:35:39 +00:00
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if (m_hLogFile == nullptr)
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2015-12-21 07:16:29 +00:00
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{
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return;
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}
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2015-11-13 13:23:43 +00:00
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2015-12-21 07:16:29 +00:00
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va_start(ap, Message);
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vsprintf(Msg, Message, ap);
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va_end(ap);
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2015-11-13 13:23:43 +00:00
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2015-12-21 07:16:29 +00:00
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strcat(Msg, "\r\n");
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2015-11-13 13:23:43 +00:00
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2015-12-21 07:16:29 +00:00
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m_hLogFile->Write(Msg, strlen(Msg));
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2015-11-13 13:23:43 +00:00
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}
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void CLogging::StartLog(void)
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{
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2015-12-21 07:16:29 +00:00
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if (!GenerateLog())
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{
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StopLog();
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return;
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}
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2021-04-12 11:35:39 +00:00
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if (m_hLogFile != nullptr)
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2015-12-21 07:16:29 +00:00
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{
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return;
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}
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2016-03-10 11:15:40 +00:00
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CPath LogFile(g_Settings->LoadStringVal(Directory_Log).c_str(), "cpudebug.log");
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2015-11-13 13:23:43 +00:00
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m_hLogFile = new CFile(LogFile, CFileBase::modeCreate | CFileBase::modeWrite);
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}
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void CLogging::StopLog(void)
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{
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2015-12-21 07:16:29 +00:00
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if (m_hLogFile)
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{
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2015-11-13 13:23:43 +00:00
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delete m_hLogFile;
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2021-04-12 11:35:39 +00:00
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m_hLogFile = nullptr;
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2015-12-21 07:16:29 +00:00
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}
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2021-04-02 07:33:39 +00:00
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}
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