2022-01-24 12:43:10 +00:00
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#include "stdafx.h"
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#include "SPRegistersHandler.h"
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#include <Project64-core\N64System\N64System.h>
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#include <Project64-core\N64System\Mips\MemoryVirtualMem.h>
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#include <Project64-core\N64System\Mips\Register.h>
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#include <Project64-core\N64System\SystemGlobals.h>
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SPRegistersReg::SPRegistersReg(uint32_t * SignalProcessorInterface) :
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SP_MEM_ADDR_REG(SignalProcessorInterface[0]),
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SP_DRAM_ADDR_REG(SignalProcessorInterface[1]),
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SP_RD_LEN_REG(SignalProcessorInterface[2]),
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SP_WR_LEN_REG(SignalProcessorInterface[3]),
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SP_STATUS_REG(SignalProcessorInterface[4]),
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SP_DMA_FULL_REG(SignalProcessorInterface[5]),
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SP_DMA_BUSY_REG(SignalProcessorInterface[6]),
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SP_SEMAPHORE_REG(SignalProcessorInterface[7]),
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SP_PC_REG(SignalProcessorInterface[8]),
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SP_IBIST_REG(SignalProcessorInterface[9])
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{
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}
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SPRegistersHandler::SPRegistersHandler(CN64System & System, CMipsMemoryVM & MMU, CRegisters & Reg) :
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SPRegistersReg(Reg.m_SigProcessor_Interface),
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2022-06-20 04:51:32 +00:00
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MIPSInterfaceReg(Reg.m_Mips_Interface),
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m_SPMemAddrRegRead(0),
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m_SPDramAddrRegRead(0),
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m_ExecutedDMARead(false),
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2022-01-24 12:43:10 +00:00
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m_System(System),
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m_MMU(MMU),
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m_Reg(Reg),
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m_RspIntrReg(Reg.m_RspIntrReg),
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m_PC(Reg.m_PROGRAM_COUNTER)
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{
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2022-06-20 04:51:32 +00:00
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System.RegisterCallBack(CN64SystemCB_Reset, this, (CN64System::CallBackFunction)stSystemReset);
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System.RegisterCallBack(CN64SystemCB_LoadedGameState, this, (CN64System::CallBackFunction)stLoadedGameState);
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2022-01-24 12:43:10 +00:00
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}
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bool SPRegistersHandler::Read32(uint32_t Address, uint32_t & Value)
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{
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switch (Address & 0x1FFFFFFF)
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{
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2022-06-20 04:51:32 +00:00
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case 0x04040000: Value = m_ExecutedDMARead ? m_SPMemAddrRegRead : SP_MEM_ADDR_REG; break;
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case 0x04040004: Value = m_ExecutedDMARead ? m_SPDramAddrRegRead : SP_DRAM_ADDR_REG; break;
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case 0x04040008: Value = SP_RD_LEN_REG; break;
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case 0x0404000C: Value = SP_WR_LEN_REG; break;
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2022-01-24 12:43:10 +00:00
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case 0x04040010: Value = SP_STATUS_REG; break;
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case 0x04040014: Value = SP_DMA_FULL_REG; break;
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case 0x04040018: Value = SP_DMA_BUSY_REG; break;
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case 0x0404001C:
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Value = SP_SEMAPHORE_REG;
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SP_SEMAPHORE_REG = 1;
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break;
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case 0x04080000: Value = SP_PC_REG; break;
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default:
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Value = 0;
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2022-09-05 01:30:15 +00:00
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if (BreakOnUnhandledMemory())
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2022-01-24 12:43:10 +00:00
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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}
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if (LogSPRegisters())
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{
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switch (Address & 0x1FFFFFFF)
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{
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case 0x04040000: LogMessage("%08X: read from SP_MEM_ADDR_REG (%08X)", m_PC, Value); break;
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case 0x04040004: LogMessage("%08X: read from SP_DRAM_ADDR_REG (%08X)", m_PC, Value); break;
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case 0x04040008: LogMessage("%08X: read from SP_RD_LEN_REG (%08X)", m_PC, Value); break;
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case 0x0404000C: LogMessage("%08X: read from SP_WR_LEN_REG (%08X)", m_PC, Value); break;
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case 0x04040010: LogMessage("%08X: read from SP_STATUS_REG (%08X)", m_PC, Value); break;
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case 0x04040014: LogMessage("%08X: read from SP_DMA_FULL_REG (%08X)", m_PC, Value); break;
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case 0x04040018: LogMessage("%08X: read from SP_DMA_BUSY_REG (%08X)", m_PC, Value); break;
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case 0x0404001C: LogMessage("%08X: read from SP_SEMAPHORE_REG (%08X)", m_PC, Value); break;
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case 0x04080000: LogMessage("%08X: read from SP_PC (%08X)", m_PC, Value); break;
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default:
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2022-09-05 01:30:15 +00:00
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if (BreakOnUnhandledMemory())
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2022-01-24 12:43:10 +00:00
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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}
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}
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return true;
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}
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bool SPRegistersHandler::Write32(uint32_t Address, uint32_t Value, uint32_t Mask)
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{
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2022-02-21 11:26:25 +00:00
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if (GenerateLog() && LogSPRegisters())
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2022-01-24 12:43:10 +00:00
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{
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switch (Address & 0x1FFFFFFF)
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{
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case 0x04040000: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to SP_MEM_ADDR_REG", m_PC, Value, Mask); break;
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case 0x04040004: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to SP_DRAM_ADDR_REG", m_PC, Value, Mask); break;
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case 0x04040008: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to SP_RD_LEN_REG", m_PC, Value, Mask); break;
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case 0x0404000C: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to SP_WR_LEN_REG", m_PC, Value, Mask); break;
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case 0x04040010: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to SP_STATUS_REG", m_PC, Value, Mask); break;
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case 0x04040014: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to SP_DMA_FULL_REG", m_PC, Value, Mask); break;
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case 0x04040018: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to SP_DMA_BUSY_REG", m_PC, Value, Mask); break;
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case 0x0404001C: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to SP_SEMAPHORE_REG", m_PC, Value, Mask); break;
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case 0x04080000: LogMessage("%08X: Writing 0x%08X (Mask: 0x%08X) to SP_PC", m_PC, Value, Mask); break;
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default:
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2022-09-05 01:30:15 +00:00
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if (BreakOnUnhandledMemory())
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2022-01-24 12:43:10 +00:00
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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}
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}
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uint32_t MaskedValue = Value & Mask;
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switch (Address & 0x1FFFFFFF)
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{
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case 0x04040000: SP_MEM_ADDR_REG = (SP_MEM_ADDR_REG & ~Mask) | (MaskedValue); break;
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case 0x04040004: SP_DRAM_ADDR_REG = (SP_DRAM_ADDR_REG & ~Mask) | (MaskedValue); break;
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case 0x04040008:
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2022-06-20 04:51:32 +00:00
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SP_RD_LEN_REG = MaskedValue;
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2022-02-01 02:54:25 +00:00
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SP_DMA_READ();
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2022-01-24 12:43:10 +00:00
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break;
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case 0x0404000C:
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SP_WR_LEN_REG = (SP_WR_LEN_REG & ~Mask) | (MaskedValue);
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2022-06-13 02:16:06 +00:00
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SP_DMA_WRITE();
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2022-01-24 12:43:10 +00:00
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break;
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case 0x04040010:
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if ((MaskedValue & SP_CLR_HALT) != 0) { SP_STATUS_REG &= ~SP_STATUS_HALT; }
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if ((MaskedValue & SP_SET_HALT) != 0) { SP_STATUS_REG |= SP_STATUS_HALT; }
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if ((MaskedValue & SP_CLR_BROKE) != 0) { SP_STATUS_REG &= ~SP_STATUS_BROKE; }
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if ((MaskedValue & SP_CLR_INTR) != 0)
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{
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2022-06-20 04:51:32 +00:00
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MI_INTR_REG &= ~MI_INTR_SP;
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2022-01-24 12:43:10 +00:00
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m_RspIntrReg &= ~MI_INTR_SP;
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m_Reg.CheckInterrupts();
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}
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2022-09-05 01:30:15 +00:00
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if ((MaskedValue & SP_SET_INTR) != 0) { if (BreakOnUnhandledMemory()) { g_Notify->BreakPoint(__FILE__, __LINE__); } }
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2022-01-24 12:43:10 +00:00
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if ((MaskedValue & SP_CLR_SSTEP) != 0) { SP_STATUS_REG &= ~SP_STATUS_SSTEP; }
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if ((MaskedValue & SP_SET_SSTEP) != 0) { SP_STATUS_REG |= SP_STATUS_SSTEP; }
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if ((MaskedValue & SP_CLR_INTR_BREAK) != 0) { SP_STATUS_REG &= ~SP_STATUS_INTR_BREAK; }
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if ((MaskedValue & SP_SET_INTR_BREAK) != 0) { SP_STATUS_REG |= SP_STATUS_INTR_BREAK; }
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if ((MaskedValue & SP_CLR_SIG0) != 0) { SP_STATUS_REG &= ~SP_STATUS_SIG0; }
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if ((MaskedValue & SP_SET_SIG0) != 0) { SP_STATUS_REG |= SP_STATUS_SIG0; }
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if ((MaskedValue & SP_CLR_SIG1) != 0) { SP_STATUS_REG &= ~SP_STATUS_SIG1; }
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if ((MaskedValue & SP_SET_SIG1) != 0) { SP_STATUS_REG |= SP_STATUS_SIG1; }
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if ((MaskedValue & SP_CLR_SIG2) != 0) { SP_STATUS_REG &= ~SP_STATUS_SIG2; }
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if ((MaskedValue & SP_SET_SIG2) != 0) { SP_STATUS_REG |= SP_STATUS_SIG2; }
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if ((MaskedValue & SP_CLR_SIG3) != 0) { SP_STATUS_REG &= ~SP_STATUS_SIG3; }
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if ((MaskedValue & SP_SET_SIG3) != 0) { SP_STATUS_REG |= SP_STATUS_SIG3; }
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if ((MaskedValue & SP_CLR_SIG4) != 0) { SP_STATUS_REG &= ~SP_STATUS_SIG4; }
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if ((MaskedValue & SP_SET_SIG4) != 0) { SP_STATUS_REG |= SP_STATUS_SIG4; }
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if ((MaskedValue & SP_CLR_SIG5) != 0) { SP_STATUS_REG &= ~SP_STATUS_SIG5; }
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if ((MaskedValue & SP_SET_SIG5) != 0) { SP_STATUS_REG |= SP_STATUS_SIG5; }
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if ((MaskedValue & SP_CLR_SIG6) != 0) { SP_STATUS_REG &= ~SP_STATUS_SIG6; }
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if ((MaskedValue & SP_SET_SIG6) != 0) { SP_STATUS_REG |= SP_STATUS_SIG6; }
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if ((MaskedValue & SP_CLR_SIG7) != 0) { SP_STATUS_REG &= ~SP_STATUS_SIG7; }
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if ((MaskedValue & SP_SET_SIG7) != 0) { SP_STATUS_REG |= SP_STATUS_SIG7; }
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if ((MaskedValue & SP_SET_SIG0) != 0 && RspAudioSignal())
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{
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2022-06-20 04:51:32 +00:00
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MI_INTR_REG |= MI_INTR_SP;
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2022-01-24 12:43:10 +00:00
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m_Reg.CheckInterrupts();
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}
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m_System.RunRSP();
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break;
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case 0x0404001C: SP_SEMAPHORE_REG = 0; break;
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case 0x04080000: SP_PC_REG = MaskedValue & 0xFFC; break;
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default:
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2022-09-05 01:30:15 +00:00
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if (BreakOnUnhandledMemory())
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2022-01-24 12:43:10 +00:00
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{
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g_Notify->BreakPoint(__FILE__, __LINE__);
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}
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}
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return true;
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}
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2022-02-01 02:54:25 +00:00
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void SPRegistersHandler::SP_DMA_READ()
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{
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2022-06-20 04:51:32 +00:00
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uint8_t * Dest = ((SP_MEM_ADDR_REG & 0x1000) != 0 ? m_MMU.Imem() : m_MMU.Dmem());
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uint8_t * Source = m_MMU.Rdram();
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uint32_t ReadPos = SP_DRAM_ADDR_REG & 0x00FFFFF8;
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int32_t Length = ((SP_RD_LEN_REG & 0xFFF) | 7) + 1;
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int32_t Count = ((SP_RD_LEN_REG >> 12) & 0xFF) + 1;
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int32_t Skip = (SP_RD_LEN_REG >> 20) & 0xF8;
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int32_t Pos = (SP_MEM_ADDR_REG & 0x0FF8);
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2022-02-01 02:54:25 +00:00
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2022-06-20 04:51:32 +00:00
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for (int32_t i = 0; i < Count; i++)
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2022-02-01 02:54:25 +00:00
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{
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2022-06-20 04:51:32 +00:00
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int32_t CopyLength = Length;
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if ((Pos + Length) > 0x1000)
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2022-02-01 02:54:25 +00:00
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{
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2022-06-20 04:51:32 +00:00
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CopyLength = 0x1000 - Pos;
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if (CopyLength <= 0)
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{
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break;
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}
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2022-02-01 02:54:25 +00:00
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}
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2022-06-20 04:51:32 +00:00
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uint32_t NullLen = 0;
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if ((ReadPos + Length) > m_MMU.RdramSize())
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2022-02-01 02:54:25 +00:00
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{
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2022-06-20 04:51:32 +00:00
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if ((m_MMU.RdramSize() - ReadPos) < (uint32_t)CopyLength)
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{
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CopyLength = (int32_t)m_MMU.RdramSize() - (int32_t)ReadPos;
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}
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else
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{
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NullLen = CopyLength;
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}
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2022-02-01 02:54:25 +00:00
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}
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2022-06-20 04:51:32 +00:00
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if (NullLen != 0)
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{
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memset(&Dest[Pos], 0, NullLen);
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}
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else
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{
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memcpy(&Dest[Pos], &Source[ReadPos], CopyLength);
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}
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if (CopyLength != Length)
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{
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ReadPos = (ReadPos + CopyLength) & 0x00FFFFFF;
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CopyLength = Length - CopyLength;
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Pos = 0;
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if ((CopyLength + ReadPos) > m_MMU.RdramSize())
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{
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int32_t CopyAmount = m_MMU.RdramSize() - ReadPos;
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if (CopyAmount < 0) { CopyAmount = 0; }
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NullLen = CopyLength - CopyAmount;
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if (CopyAmount > 0)
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{
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memcpy(&Dest[Pos], &Source[ReadPos], CopyLength);
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}
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if (NullLen > 0)
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{
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memset(&Dest[Pos], 0, NullLen);
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}
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}
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else
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{
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memcpy(&Dest[Pos], &Source[ReadPos], CopyLength);
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}
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}
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ReadPos += CopyLength + Skip;
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Pos += CopyLength;
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2022-02-01 02:54:25 +00:00
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}
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2022-06-20 04:51:32 +00:00
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if (Count > 1)
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2022-02-01 02:54:25 +00:00
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{
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2022-06-20 04:51:32 +00:00
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ReadPos -= Skip;
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2022-02-01 02:54:25 +00:00
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}
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SP_DMA_BUSY_REG = 0;
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SP_STATUS_REG &= ~SP_STATUS_DMA_BUSY;
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2022-06-20 04:51:32 +00:00
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m_ExecutedDMARead = true;
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m_SPMemAddrRegRead = Pos | (SP_MEM_ADDR_REG & 0x1000);
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m_SPDramAddrRegRead = ReadPos;
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SP_RD_LEN_REG = (SP_RD_LEN_REG & 0xFF800000) | 0x00000FF8;
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SP_WR_LEN_REG = (SP_RD_LEN_REG & 0xFF800000) | 0x00000FF8;
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2022-02-01 02:54:25 +00:00
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}
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2022-06-13 02:16:06 +00:00
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void SPRegistersHandler::SP_DMA_WRITE()
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{
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2022-06-20 04:51:32 +00:00
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uint8_t * Source = ((SP_MEM_ADDR_REG & 0x1000) != 0 ? m_MMU.Imem() : m_MMU.Dmem());
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uint8_t * Dest = m_MMU.Rdram();
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uint32_t WritePos = SP_DRAM_ADDR_REG & 0x00FFFFF8;
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int32_t Length = ((SP_WR_LEN_REG & 0xFFF) | 7) + 1;
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int32_t Count = ((SP_WR_LEN_REG >> 12) & 0xFF) + 1;
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int32_t Skip = (SP_WR_LEN_REG >> 20) & 0xF8;
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int32_t Pos = (SP_MEM_ADDR_REG & 0x0FF8);
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|
|
|
for (int32_t i = 0; i < Count; i++)
|
2022-06-13 02:16:06 +00:00
|
|
|
{
|
2022-06-20 04:51:32 +00:00
|
|
|
int32_t CopyLength = Length;
|
|
|
|
if (Pos + Length > 0x1000)
|
2022-06-13 02:16:06 +00:00
|
|
|
{
|
2022-06-20 04:51:32 +00:00
|
|
|
CopyLength = 0x1000 - Pos;
|
|
|
|
if (CopyLength <= 0)
|
|
|
|
{
|
|
|
|
break;
|
|
|
|
}
|
2022-06-13 02:16:06 +00:00
|
|
|
}
|
|
|
|
|
2022-06-20 04:51:32 +00:00
|
|
|
if (WritePos < m_MMU.RdramSize())
|
2022-06-13 02:16:06 +00:00
|
|
|
{
|
2022-06-20 04:51:32 +00:00
|
|
|
int32_t CopyAmount = (int32_t)m_MMU.RdramSize() - (int32_t)WritePos;
|
|
|
|
if (CopyLength < CopyAmount)
|
|
|
|
{
|
|
|
|
CopyAmount = CopyLength;
|
|
|
|
}
|
|
|
|
if (CopyAmount > 0)
|
|
|
|
{
|
|
|
|
memcpy(&Dest[WritePos], &Source[Pos], CopyAmount);
|
|
|
|
}
|
2022-06-13 02:16:06 +00:00
|
|
|
}
|
|
|
|
|
2022-06-20 04:51:32 +00:00
|
|
|
if (CopyLength != Length)
|
|
|
|
{
|
|
|
|
WritePos = (WritePos + CopyLength) & 0x00FFFFFF;
|
|
|
|
CopyLength = Length - CopyLength;
|
|
|
|
Pos = 0;
|
2022-06-13 02:16:06 +00:00
|
|
|
|
2022-06-20 04:51:32 +00:00
|
|
|
int32_t CopyAmount = (int32_t)m_MMU.RdramSize() - (int32_t)WritePos;
|
|
|
|
if (CopyLength < CopyAmount)
|
|
|
|
{
|
|
|
|
CopyAmount = CopyLength;
|
|
|
|
}
|
|
|
|
if (CopyAmount > 0)
|
|
|
|
{
|
|
|
|
memcpy(&Dest[WritePos], &Source[Pos], CopyAmount);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
WritePos += CopyLength + Skip;
|
|
|
|
Pos += CopyLength;
|
2022-06-13 02:16:06 +00:00
|
|
|
}
|
2022-06-20 04:51:32 +00:00
|
|
|
|
|
|
|
if (Count > 1)
|
2022-06-13 02:16:06 +00:00
|
|
|
{
|
2022-06-20 04:51:32 +00:00
|
|
|
WritePos -= Skip;
|
2022-06-13 02:16:06 +00:00
|
|
|
}
|
|
|
|
|
2022-06-20 04:51:32 +00:00
|
|
|
SP_DMA_BUSY_REG = 0;
|
|
|
|
SP_STATUS_REG &= ~SP_STATUS_DMA_BUSY;
|
|
|
|
|
|
|
|
m_ExecutedDMARead = true;
|
|
|
|
m_SPMemAddrRegRead = Pos | (SP_MEM_ADDR_REG & 0x1000);
|
|
|
|
m_SPDramAddrRegRead = WritePos;
|
|
|
|
SP_RD_LEN_REG = (SP_WR_LEN_REG & 0xFF800000) | 0x00000FF8;
|
|
|
|
SP_WR_LEN_REG = (SP_WR_LEN_REG & 0xFF800000) | 0x00000FF8;
|
|
|
|
}
|
2022-06-13 02:16:06 +00:00
|
|
|
|
2022-06-20 04:51:32 +00:00
|
|
|
void SPRegistersHandler::SystemReset(void)
|
|
|
|
{
|
|
|
|
SP_RD_LEN_REG = 0x00000FF8;
|
|
|
|
SP_WR_LEN_REG = 0x00000FF8;
|
|
|
|
}
|
|
|
|
|
|
|
|
void SPRegistersHandler::LoadedGameState(void)
|
|
|
|
{
|
|
|
|
m_SPMemAddrRegRead = 0;
|
|
|
|
m_ExecutedDMARead = false;
|
2022-06-13 02:16:06 +00:00
|
|
|
}
|