mirror of https://github.com/PCSX2/pcsx2.git
447 lines
12 KiB
C
447 lines
12 KiB
C
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2009 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#ifndef __HW_H__
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#define __HW_H__
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extern u8 *psH; // hw mem
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#define psHs8(mem) (*(s8 *)&PS2MEM_HW[(mem) & 0xffff])
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#define psHs16(mem) (*(s16*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHs32(mem) (*(s32*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHs64(mem) (*(s64*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu8(mem) (*(u8 *)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu16(mem) (*(u16*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu32(mem) (*(u32*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu64(mem) (*(u64*)&PS2MEM_HW[(mem) & 0xffff])
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extern void CPU_INT( u32 n, s32 ecycle );
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//////////////////////////////////////////////////////////////////////////
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// Hardware FIFOs (128 bit access only!)
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//
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// VIF0 -- 0x10004000 -- psH[0x4000]
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// VIF1 -- 0x10005000 -- psH[0x5000]
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// GIF -- 0x10006000 -- psH[0x6000]
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// IPUout -- 0x10007000 -- psH[0x7000]
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// IPUin -- 0x10007010 -- psH[0x7010]
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void __fastcall ReadFIFO_page_4(u32 mem, mem128_t *out);
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void __fastcall ReadFIFO_page_5(u32 mem, mem128_t *out);
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void __fastcall ReadFIFO_page_6(u32 mem, mem128_t *out);
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void __fastcall ReadFIFO_page_7(u32 mem, mem128_t *out);
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void __fastcall WriteFIFO_page_4(u32 mem, const mem128_t *value);
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void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value);
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void __fastcall WriteFIFO_page_6(u32 mem, const mem128_t *value);
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void __fastcall WriteFIFO_page_7(u32 mem, const mem128_t *value);
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//
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// --- DMA ---
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//
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struct DMACh {
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u32 chcr;
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u32 null0[3];
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u32 madr;
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u32 null1[3];
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u16 qwc; u16 pad;
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u32 null2[3];
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u32 tadr;
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u32 null3[3];
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u32 asr0;
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u32 null4[3];
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u32 asr1;
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u32 null5[11];
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u32 sadr;
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};
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// HW defines
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#define RCNT0_COUNT 0x10000000
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#define RCNT0_MODE 0x10000010
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#define RCNT0_TARGET 0x10000020
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#define RCNT0_HOLD 0x10000030
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#define RCNT1_COUNT 0x10000800
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#define RCNT1_MODE 0x10000810
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#define RCNT1_TARGET 0x10000820
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#define RCNT1_HOLD 0x10000830
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#define RCNT2_COUNT 0x10001000
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#define RCNT2_MODE 0x10001010
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#define RCNT2_TARGET 0x10001020
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#define RCNT3_COUNT 0x10001800
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#define RCNT3_MODE 0x10001810
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#define RCNT3_TARGET 0x10001820
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#define IPU_CMD 0x10002000
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#define IPU_CTRL 0x10002010
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#define IPU_BP 0x10002020
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#define IPU_TOP 0x10002030
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#define GIF_CTRL 0x10003000
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#define GIF_MODE 0x10003010
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#define GIF_STAT 0x10003020
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#define GIF_TAG0 0x10003040
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#define GIF_TAG1 0x10003050
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#define GIF_TAG2 0x10003060
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#define GIF_TAG3 0x10003070
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#define GIF_CNT 0x10003080
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#define GIF_P3CNT 0x10003090
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#define GIF_P3TAG 0x100030A0
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#define GIF_FIFO 0x10006000
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#define IPUout_FIFO 0x10007000
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#define IPUin_FIFO 0x10007010
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//VIF0
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#define D0_CHCR 0x10008000
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#define D0_MADR 0x10008010
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#define D0_QWC 0x10008020
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//VIF1
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#define D1_CHCR 0x10009000
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#define D1_MADR 0x10009010
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#define D1_QWC 0x10009020
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#define D1_TADR 0x10009030
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#define D1_ASR0 0x10009040
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#define D1_ASR1 0x10009050
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#define D1_SADR 0x10009080
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//GS
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#define D2_CHCR 0x1000A000
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#define D2_MADR 0x1000A010
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#define D2_QWC 0x1000A020
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#define D2_TADR 0x1000A030
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#define D2_ASR0 0x1000A040
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#define D2_ASR1 0x1000A050
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#define D2_SADR 0x1000A080
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//fromIPU
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#define D3_CHCR 0x1000B000
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#define D3_MADR 0x1000B010
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#define D3_QWC 0x1000B020
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#define D3_TADR 0x1000B030
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#define D3_SADR 0x1000B080
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//toIPU
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#define D4_CHCR 0x1000B400
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#define D4_MADR 0x1000B410
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#define D4_QWC 0x1000B420
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#define D4_TADR 0x1000B430
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#define D4_SADR 0x1000B480
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//SIF0
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#define D5_CHCR 0x1000C000
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#define D5_MADR 0x1000C010
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#define D5_QWC 0x1000C020
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//SIF1
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#define D6_CHCR 0x1000C400
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#define D6_MADR 0x1000C410
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#define D6_QWC 0x1000C420
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//SIF2
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#define D7_CHCR 0x1000C800
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#define D7_MADR 0x1000C810
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#define D7_QWC 0x1000C820
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//fromSPR
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#define D8_CHCR 0x1000D000
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#define D8_MADR 0x1000D010
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#define D8_QWC 0x1000D020
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#define D8_SADR 0x1000D080
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#define DMAC_CTRL 0x1000E000
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#define DMAC_STAT 0x1000E010
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#define DMAC_PCR 0x1000E020
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#define DMAC_SQWC 0x1000E030
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#define DMAC_RBSR 0x1000E040
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#define DMAC_RBOR 0x1000E050
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#define DMAC_STADR 0x1000E060
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#define INTC_STAT 0x1000F000
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#define INTC_MASK 0x1000F010
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#define SBUS_F220 0x1000F220
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#define SBUS_SMFLG 0x1000F230
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#define SBUS_F240 0x1000F240
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#define DMAC_ENABLER 0x1000F520
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#define DMAC_ENABLEW 0x1000F590
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#define SBFLG_IOPALIVE 0x10000
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#define SBFLG_IOPSYNC 0x40000
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#define GS_PMODE 0x12000000
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#define GS_SMODE1 0x12000010
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#define GS_SMODE2 0x12000020
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#define GS_SRFSH 0x12000030
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#define GS_SYNCH1 0x12000040
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#define GS_SYNCH2 0x12000050
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#define GS_SYNCV 0x12000060
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#define GS_DISPFB1 0x12000070
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#define GS_DISPLAY1 0x12000080
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#define GS_DISPFB2 0x12000090
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#define GS_DISPLAY2 0x120000A0
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#define GS_EXTBUF 0x120000B0
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#define GS_EXTDATA 0x120000C0
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#define GS_EXTWRITE 0x120000D0
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#define GS_BGCOLOR 0x120000E0
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#define GS_CSR 0x12001000
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#define GS_IMR 0x12001010
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#define GS_BUSDIR 0x12001040
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#define GS_SIGLBLID 0x12001080
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#define INTC_GS 0
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#define INTC_SBUS 1
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#define INTC_VBLANK_S 2
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#define INTC_VBLANK_E 3
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#define INTC_VIF0 4
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#define INTC_VIF1 5
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#define INTC_VU0 6
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#define INTC_VU1 7
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#define INTC_IPU 8
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#define INTC_TIM0 9
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#define INTC_TIM1 10
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#define INTC_TIM2 11
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#define INTC_TIM3 12
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#define DMAC_STAT_SIS (1<<13) // stall condition
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#define DMAC_STAT_MEIS (1<<14) // mfifo empty
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#define DMAC_STAT_BEIS (1<<15) // bus error
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#define DMAC_STAT_SIM (1<<29) // stall mask
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#define DMAC_STAT_MEIM (1<<30) // mfifo mask
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#define DMAC_VIF0 0
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#define DMAC_VIF1 1
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#define DMAC_GIF 2
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#define DMAC_FROM_IPU 3
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#define DMAC_TO_IPU 4
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#define DMAC_SIF0 5
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#define DMAC_SIF1 6
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#define DMAC_SIF2 7
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#define DMAC_FROM_SPR 8
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#define DMAC_TO_SPR 9
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#define DMAC_ERROR 15
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#define VIF0_STAT_VPS_W (1)
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#define VIF0_STAT_VPS_D (2)
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#define VIF0_STAT_VPS_T (3)
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#define VIF0_STAT_VPS (3)
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#define VIF0_STAT_VEW (1<<2)
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#define VIF0_STAT_MRK (1<<6)
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#define VIF0_STAT_DBF (1<<7)
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#define VIF0_STAT_VSS (1<<8)
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#define VIF0_STAT_VFS (1<<9)
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#define VIF0_STAT_VIS (1<<10)
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#define VIF0_STAT_INT (1<<11)
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#define VIF0_STAT_ER0 (1<<12)
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#define VIF0_STAT_ER1 (1<<13)
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#define VIF1_STAT_VPS_W (1)
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#define VIF1_STAT_VPS_D (2)
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#define VIF1_STAT_VPS_T (3)
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#define VIF1_STAT_VPS (3)
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#define VIF1_STAT_VEW (1<<2)
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#define VIF1_STAT_VGW (1<<3)
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#define VIF1_STAT_MRK (1<<6)
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#define VIF1_STAT_DBF (1<<7)
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#define VIF1_STAT_VSS (1<<8)
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#define VIF1_STAT_VFS (1<<9)
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#define VIF1_STAT_VIS (1<<10)
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#define VIF1_STAT_INT (1<<11)
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#define VIF1_STAT_ER0 (1<<12)
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#define VIF1_STAT_ER1 (1<<13)
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#define VIF1_STAT_FDR (1<<23)
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//DMA interrupts & masks
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#define BEISintr (0x8000)
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#define VIF0intr (0x10001)
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#define VIF1intr (0x20002)
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#define GIFintr (0x40004)
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#define IPU0intr (0x80008)
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#define IPU1intr (0x100010)
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#define SIF0intr (0x200020)
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#define SIF1intr (0x400040)
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#define SIF2intr (0x800080)
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#define SPR0intr (0x1000100)
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#define SPR1intr (0x2000200)
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#define SISintr (0x20002000)
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#define MEISintr (0x40004000)
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#define DMAend(dma, num) { \
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dma->chcr &= ~0x100; \
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psHu32(DMAC_STAT)|= 1<<num; \
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return; \
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}
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#define DMAerror(dma, num) { \
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psHu32(DMAC_STAT)|= 1<<15; /* BUS error */ \
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DMAend(dma, num); \
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}
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#define _dmaGetAddr(dma, ptr, addr, num) \
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ptr = (u32*)dmaGetAddr(addr); \
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if (ptr == NULL) DMAerror(dma, num);
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#ifdef PCSX2_VIRTUAL_MEM
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#define dmaGetAddrBase(addr) (((addr) & 0x80000000) ? (void*)&PS2MEM_SCRATCH[(addr) & 0x3ff0] : (void*)(PS2MEM_BASE+TRANSFORM_ADDR(addr)))
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#ifdef _WIN32
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extern PSMEMORYMAP* memLUT;
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#endif
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// VM-version of dmaGetAddr -- Left in for references purposes for now (air)
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static __forceinline u8* dmaGetAddr(u32 mem)
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{
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u8* p, *pbase;
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mem &= ~0xf;
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if( (mem&0xffff0000) == 0x50000000 ) {// reserved scratch pad mem
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SysPrintf("dmaGetAddr: reserved scratch pad mem\n");
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return NULL;//(u8*)&PS2MEM_SCRATCH[(mem) & 0x3ff0];
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}
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p = (u8*)dmaGetAddrBase(mem);
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#ifdef _WIN32
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// do manual LUT since IPU/SPR seems to use addrs 0x3000xxxx quite often
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// linux doesn't suffer from this because it has better vm support
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if( memLUT[ (p-PS2MEM_BASE)>>12 ].aPFNs == NULL ) {
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SysPrintf("dmaGetAddr: memLUT PFN warning\n");
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return NULL;//p;
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}
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pbase = (u8*)memLUT[ (p-PS2MEM_BASE)>>12 ].aVFNs[0];
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if( pbase != NULL )
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p = pbase + ((u32)p&0xfff);
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#endif
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return p;
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}
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#else
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// Note: Dma addresses are guaranteed to be aligned to 16 bytes (128 bits)
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static __forceinline void *dmaGetAddr(u32 addr) {
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u8 *ptr;
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// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x\n", addr); }
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if (addr & 0x80000000) { // teh sux why the f00k 0xE0000000
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return (void*)&psS[addr & 0x3ff0];
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}
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ptr = (u8*)vtlb_GetPhyPtr(addr&0x1FFFFFF0);
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if (ptr == NULL) {
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Console::Error("*PCSX2*: DMA error: %8.8x", params addr);
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return NULL;
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}
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return ptr;
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}
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#endif
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void hwInit();
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void hwReset();
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void hwShutdown();
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// hw read functions
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extern u8 hwRead8 (u32 mem);
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extern u16 hwRead16(u32 mem);
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extern mem32_t __fastcall hwRead32_page_00(u32 mem);
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extern mem32_t __fastcall hwRead32_page_01(u32 mem);
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extern mem32_t __fastcall hwRead32_page_02(u32 mem);
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extern mem32_t __fastcall hwRead32_page_0F(u32 mem);
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extern mem32_t __fastcall hwRead32_page_0F_INTC_HACK(u32 mem);
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extern mem32_t __fastcall hwRead32_generic(u32 mem);
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extern void __fastcall hwRead64_page_00(u32 mem, mem64_t* result );
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extern void __fastcall hwRead64_page_01(u32 mem, mem64_t* result );
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extern void __fastcall hwRead64_page_02(u32 mem, mem64_t* result );
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extern void __fastcall hwRead64_generic_INTC_HACK(u32 mem, mem64_t *out);
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extern void __fastcall hwRead64_generic(u32 mem, mem64_t* result );
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extern void __fastcall hwRead128_page_00(u32 mem, mem128_t* result );
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extern void __fastcall hwRead128_page_01(u32 mem, mem128_t* result );
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extern void __fastcall hwRead128_page_02(u32 mem, mem128_t* result );
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extern void __fastcall hwRead128_generic(u32 mem, mem128_t *out);
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// hw write functions
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extern void hwWrite8 (u32 mem, u8 value);
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extern void hwWrite16(u32 mem, u16 value);
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extern void __fastcall hwWrite32_page_00( u32 mem, u32 value );
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extern void __fastcall hwWrite32_page_01( u32 mem, u32 value );
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extern void __fastcall hwWrite32_page_02( u32 mem, u32 value );
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extern void __fastcall hwWrite32_page_03( u32 mem, u32 value );
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extern void __fastcall hwWrite32_page_0B( u32 mem, u32 value );
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extern void __fastcall hwWrite32_page_0E( u32 mem, u32 value );
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extern void __fastcall hwWrite32_page_0F( u32 mem, u32 value );
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extern void __fastcall hwWrite32_generic( u32 mem, u32 value );
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extern void __fastcall hwWrite64_page_02( u32 mem, const mem64_t* srcval );
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extern void __fastcall hwWrite64_page_03( u32 mem, const mem64_t* srcval );
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extern void __fastcall hwWrite64_page_0E( u32 mem, const mem64_t* srcval );
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extern void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval );
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extern void __fastcall hwWrite128_generic(u32 mem, const mem128_t *srcval);
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// legacy - used for debugging sometimes
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//extern mem32_t __fastcall hwRead32(u32 mem);
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//extern void __fastcall hwWrite32(u32 mem, u32 value);
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//extern void hwWrite64(u32 mem, u64 value);
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//extern void hwWrite128(u32 mem, const u64 *value);
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void hwIntcIrq(int n);
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void hwDmacIrq(int n);
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int hwMFIFORead(u32 addr, u8 *data, u32 size);
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int hwMFIFOWrite(u32 addr, u8 *data, u32 size);
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int hwDmacSrcChainWithStack(DMACh *dma, int id);
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int hwDmacSrcChain(DMACh *dma, int id);
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int hwConstRead8 (u32 x86reg, u32 mem, u32 sign);
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int hwConstRead16(u32 x86reg, u32 mem, u32 sign);
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int hwConstRead32(u32 x86reg, u32 mem);
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void hwConstRead64(u32 mem, int mmreg);
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void hwConstRead128(u32 mem, int xmmreg);
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void hwConstWrite8 (u32 mem, int mmreg);
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void hwConstWrite16(u32 mem, int mmreg);
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void hwConstWrite32(u32 mem, int mmreg);
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void hwConstWrite64(u32 mem, int mmreg);
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void hwConstWrite128(u32 mem, int xmmreg);
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extern void intcInterrupt();
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extern void dmacInterrupt();
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extern int rdram_devices, rdram_sdevid;
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#endif /* __HW_H__ */
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