mirror of https://github.com/PCSX2/pcsx2.git
513 lines
13 KiB
C++
513 lines
13 KiB
C++
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2009 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "PrecompiledHeader.h"
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#define _PC_ // disables MIPS opcode macros.
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#include "IopCommon.h"
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#include "Sifcmd.h"
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using namespace std;
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DMACh *sif0ch;
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DMACh *sif1ch;
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DMACh *sif2ch;
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#define FIFO_SIF0_W 128
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#define FIFO_SIF1_W 128
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struct _sif0
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{
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u32 fifoData[FIFO_SIF0_W];
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s32 fifoReadPos;
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s32 fifoWritePos;
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s32 fifoSize;
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s32 chain;
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s32 end;
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s32 tagMode;
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s32 counter;
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struct sifData sifData;
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};
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struct _sif1
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{
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u32 fifoData[FIFO_SIF1_W];
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s32 fifoReadPos;
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s32 fifoWritePos;
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s32 fifoSize;
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s32 chain;
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s32 end;
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s32 tagMode;
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s32 counter;
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};
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static _sif0 sif0;
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static _sif1 sif1;
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int eesifbusy[2] = { 0, 0 };
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extern int iopsifbusy[2];
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void sifInit()
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{
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memzero_obj(sif0);
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memzero_obj(sif1);
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memzero_obj(eesifbusy);
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memzero_obj(iopsifbusy);
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}
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static __forceinline void SIF0write(u32 *from, int words)
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{
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const int wP0 = min((FIFO_SIF0_W - sif0.fifoWritePos), words);
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const int wP1 = words - wP0;
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memcpy(&sif0.fifoData[sif0.fifoWritePos], from, wP0 << 2);
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memcpy(&sif0.fifoData[0], &from[wP0], wP1 << 2);
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sif0.fifoWritePos = (sif0.fifoWritePos + words) & (FIFO_SIF0_W - 1);
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sif0.fifoSize += words;
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SIF_LOG(" SIF0 + %d = %d (pos=%d)", words, sif0.fifoSize, sif0.fifoWritePos);
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}
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static __forceinline void SIF0read(u32 *to, int words)
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{
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const int wP0 = min((FIFO_SIF0_W - sif0.fifoReadPos), words);
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const int wP1 = words - wP0;
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memcpy(to, &sif0.fifoData[sif0.fifoReadPos], wP0 << 2);
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memcpy(&to[wP0], &sif0.fifoData[0], wP1 << 2);
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sif0.fifoReadPos = (sif0.fifoReadPos + words) & (FIFO_SIF0_W - 1);
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sif0.fifoSize -= words;
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SIF_LOG(" SIF0 - %d = %d (pos=%d)", words, sif0.fifoSize, sif0.fifoReadPos);
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}
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__forceinline void SIF1write(u32 *from, int words)
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{
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const int wP0 = min((FIFO_SIF1_W - sif1.fifoWritePos), words);
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const int wP1 = words - wP0;
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memcpy(&sif1.fifoData[sif1.fifoWritePos], from, wP0 << 2);
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memcpy(&sif1.fifoData[0], &from[wP0], wP1 << 2);
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sif1.fifoWritePos = (sif1.fifoWritePos + words) & (FIFO_SIF1_W - 1);
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sif1.fifoSize += words;
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SIF_LOG(" SIF1 + %d = %d (pos=%d)", words, sif1.fifoSize, sif1.fifoWritePos);
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}
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static __forceinline void SIF1read(u32 *to, int words)
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{
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const int wP0 = min((FIFO_SIF1_W - sif1.fifoReadPos), words);
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const int wP1 = words - wP0;
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memcpy(to, &sif1.fifoData[sif1.fifoReadPos], wP0 << 2);
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memcpy(&to[wP0], &sif1.fifoData[0], wP1 << 2);
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sif1.fifoReadPos = (sif1.fifoReadPos + words) & (FIFO_SIF1_W - 1);
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sif1.fifoSize -= words;
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SIF_LOG(" SIF1 - %d = %d (pos=%d)", words, sif1.fifoSize, sif1.fifoReadPos);
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}
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__forceinline void SIF0Dma()
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{
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u32 *ptag;
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bool done = FALSE;
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int cycles = 0, psxCycles = 0;
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SIF_LOG("SIF0 DMA start...");
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do
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{
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if (iopsifbusy[0] == 1) // If EE SIF0 is enabled
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{
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if (sif0.counter == 0) // If there's no more to transfer
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{
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// Note.. add normal mode here
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if (sif0.sifData.data & 0xC0000000) // If NORMAL mode or end of CHAIN, or interrupt then stop DMA
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{
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SIF_LOG(" IOP SIF Stopped");
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// Stop & signal interrupts on IOP
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iopsifbusy[0] = 0;
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// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords)
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// So when we're all done, the equation looks like thus:
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//PSX_INT(IopEvt_SIF0, ( ( psxCycles*BIAS ) / 4 ) / 8);
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PSX_INT(IopEvt_SIF0, psxCycles);
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sif0.sifData.data = 0;
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done = TRUE;
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}
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else // Chain mode
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{
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// Process DMA tag at HW_DMA9_TADR
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sif0.sifData = *(sifData *)iopPhysMem(HW_DMA9_TADR);
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sif0.sifData.words = (sif0.sifData.words + 3) & 0xfffffffc; // Round up to nearest 4.
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SIF0write((u32*)iopPhysMem(HW_DMA9_TADR + 8), 4);
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HW_DMA9_MADR = sif0.sifData.data & 0xFFFFFF;
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HW_DMA9_TADR += 16; ///HW_DMA9_MADR + 16 + sif0.sifData.words << 2;
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sif0.counter = sif0.sifData.words & 0xFFFFFF;
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SIF_LOG(" SIF0 Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", HW_DMA9_MADR, HW_DMA9_TADR, sif0.counter, sif0.sifData.words, sif0.sifData.data);
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if (sif0.sifData.data & 0x40000000)
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SIF_LOG(" END");
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else
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SIF_LOG(" CNT %08X, %08X", sif0.sifData.data, sif0.sifData.words);
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done = FALSE;
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}
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}
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else // There's some data ready to transfer into the fifo..
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{
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int wTransfer = min(sif0.counter, FIFO_SIF0_W - sif0.fifoSize); // HW_DMA9_BCR >> 16;
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SIF_LOG("+++++++++++ %lX of %lX", wTransfer, sif0.counter /*(HW_DMA9_BCR >> 16)*/);
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SIF0write((u32*)iopPhysMem(HW_DMA9_MADR), wTransfer);
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HW_DMA9_MADR += wTransfer << 2;
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psxCycles += (wTransfer / 4) * BIAS; // fixme : should be / 16
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sif0.counter -= wTransfer;
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}
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}
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if (eesifbusy[0] == 1) // If EE SIF enabled and there's something to transfer
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{
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int size = sif0dma->qwc;
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if ((psHu32(DMAC_CTRL) & 0x30) == 0x10) // STS == fromSIF0
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{
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SIF_LOG("SIF0 stall control");
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}
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if (size > 0) // If we're reading something continue to do so
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{
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int readSize = min(size, (sif0.fifoSize >> 2));
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//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr);
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SIF_LOG("----------- %lX of %lX", readSize << 2, size << 2);
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ptag = _dmaGetAddr(sif0dma, sif0dma->madr, 5);
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if (ptag == NULL) return;
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//_dmaGetAddr(sif0dma, *ptag, sif0dma->madr, 5);
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SIF0read((u32*)ptag, readSize << 2);
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// Clearing handled by vtlb memory protection and manual blocks.
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//Cpu->Clear(sif0dma->madr, readSize*4);
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cycles += readSize; // fixme : BIAS is factored in below
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sif0dma->qwc -= readSize;
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sif0dma->madr += readSize << 4;
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}
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if (sif0dma->qwc == 0)
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{
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if (((sif0dma->chcr & 0x80000080) == 0x80000080) || (sif0.end)) // Stop on tag IRQ or END
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{
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if (sif0.end)
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SIF_LOG(" EE SIF end");
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else
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SIF_LOG(" EE SIF interrupt");
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eesifbusy[0] = 0;
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CPU_INT(5, cycles*BIAS);
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done = TRUE;
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}
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else if (sif0.fifoSize >= 4) // Read a tag
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{
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static PCSX2_ALIGNED16(u32 tag[4]);
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SIF0read((u32*)&tag[0], 4); // Tag
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SIF_LOG(" EE SIF read tag: %x %x %x %x", tag[0], tag[1], tag[2], tag[3]);
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sif0dma->qwc = (u16)tag[0];
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sif0dma->madr = tag[1];
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sif0dma->chcr = (sif0dma->chcr & 0xffff) | (tag[0] & 0xffff0000);
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SIF_LOG(" EE SIF dest chain tag madr:%08X qwc:%04X id:%X irq:%d(%08X_%08X)", sif0dma->madr, sif0dma->qwc, (tag[0] >> 28)&3, (tag[0] >> 31)&1, tag[1], tag[0]);
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if ((psHu32(DMAC_CTRL) & 0x30) != 0 && ((tag[0] >> 28)&3) == 0)
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psHu32(DMAC_STADR) = sif0dma->madr + (sif0dma->qwc * 16);
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sif0.chain = 1;
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if (tag[0] & 0x40000000) sif0.end = 1;
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done = FALSE;
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}
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}
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}
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}
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while (!done);
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}
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__forceinline void SIF1Dma()
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{
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int id;
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u32 *ptag;
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bool done = FALSE;
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int cycles = 0, psxCycles = 0;
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do
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{
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if (eesifbusy[1] == 1) // If EE SIF1 is enabled
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{
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if ((psHu32(DMAC_CTRL) & 0xC0) == 0xC0)
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SIF_LOG("SIF1 stall control"); // STS == fromSIF1
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if (sif1dma->qwc == 0) // If there's no more to transfer
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{
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if ((sif1dma->chcr & 0xc) == 0 || sif1.end) // If NORMAL mode or end of CHAIN then stop DMA
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{
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// Stop & signal interrupts on EE
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SIF_LOG("EE SIF1 End %x", sif1.end);
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eesifbusy[1] = 0;
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done = TRUE;
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CPU_INT(6, cycles*BIAS);
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sif1.chain = 0;
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sif1.end = 0;
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}
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else // Chain mode
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{
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// Process DMA tag at sif1dma->tadr
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done = FALSE;
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ptag = _dmaGetAddr(sif1dma, sif1dma->tadr, 6);
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if (ptag == NULL) return;
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//_dmaGetAddr(sif1dma, *ptag, sif1dma->tadr, 6);
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sif1dma->chcr = (sif1dma->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); // Copy the tag
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sif1dma->qwc = (u16)ptag[0];
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if (sif1dma->chcr & 0x40)
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{
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Console::WriteLn("SIF1 TTE");
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SIF1write(ptag + 2, 2);
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}
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sif1.chain = 1;
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id = (ptag[0] >> 28) & 0x7;
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switch (id)
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{
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case 0: // refe
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SIF_LOG(" REFE %08X", ptag[1]);
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sif1.end = 1;
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sif1dma->madr = ptag[1];
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sif1dma->tadr += 16;
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break;
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case 1: // cnt
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SIF_LOG(" CNT");
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sif1dma->madr = sif1dma->tadr + 16;
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sif1dma->tadr = sif1dma->madr + (sif1dma->qwc << 4);
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break;
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case 2: // next
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SIF_LOG(" NEXT %08X", ptag[1]);
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sif1dma->madr = sif1dma->tadr + 16;
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sif1dma->tadr = ptag[1];
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break;
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case 3: // ref
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case 4: // refs
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SIF_LOG(" REF %08X", ptag[1]);
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sif1dma->madr = ptag[1];
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sif1dma->tadr += 16;
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break;
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case 7: // end
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SIF_LOG(" END");
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sif1.end = 1;
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sif1dma->madr = sif1dma->tadr + 16;
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sif1dma->tadr = sif1dma->madr + (sif1dma->qwc << 4);
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break;
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default:
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Console::WriteLn("Bad addr1 source chain");
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}
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if ((sif1dma->chcr & 0x80) && (ptag[0] >> 31))
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{
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Console::WriteLn("SIF1 TIE");
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sif1.end = 1;
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}
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}
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}
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else // There's some data ready to transfer into the fifo..
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{
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int qwTransfer = sif1dma->qwc;
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u32 *data;
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data = _dmaGetAddr(sif1dma, sif1dma->madr, 6);
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if (data == NULL) return;
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//_dmaGetAddr(sif1dma, *data, sif1dma->madr, 6);
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if (qwTransfer > (FIFO_SIF1_W - sif1.fifoSize) / 4) // Copy part of sif1dma into FIFO
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qwTransfer = (FIFO_SIF1_W - sif1.fifoSize) / 4;
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SIF1write(data, qwTransfer << 2);
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sif1dma->madr += qwTransfer << 4;
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cycles += qwTransfer; // fixme : BIAS is factored in above
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sif1dma->qwc -= qwTransfer;
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}
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}
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if (iopsifbusy[1] == 1) // If IOP SIF enabled and there's something to transfer
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{
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int size = sif1.counter;
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if (size > 0) // If we're reading something continue to do so
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{
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int readSize = size;
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if (readSize > sif1.fifoSize) readSize = sif1.fifoSize;
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SIF_LOG(" IOP SIF doing transfer %04X to %08X", readSize, HW_DMA10_MADR);
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SIF1read((u32*)iopPhysMem(HW_DMA10_MADR), readSize);
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psxCpu->Clear(HW_DMA10_MADR, readSize);
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psxCycles += readSize / 4; // fixme: should be / 16
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sif1.counter = size - readSize;
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HW_DMA10_MADR += readSize << 2;
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}
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if (sif1.counter <= 0)
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{
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if ((sif1.tagMode & 0x80) || (sif1.tagMode & 0x40)) // Stop on tag IRQ or END
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{
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if (sif1.tagMode & 0x40)
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SIF_LOG(" IOP SIF end");
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else
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SIF_LOG(" IOP SIF interrupt");
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iopsifbusy[1] = 0;
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PSX_INT(IopEvt_SIF1, psxCycles);
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sif1.tagMode = 0;
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done = TRUE;
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}
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else if (sif1.fifoSize >= 4) // Read a tag
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{
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struct sifData d;
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SIF1read((u32*)&d, 4);
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SIF_LOG(" IOP SIF dest chain tag madr:%08X wc:%04X id:%X irq:%d", d.data & 0xffffff, d.words, (d.data >> 28)&7, (d.data >> 31)&1);
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HW_DMA10_MADR = d.data & 0xffffff;
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sif1.counter = d.words;
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sif1.tagMode = (d.data >> 24) & 0xFF;
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done = FALSE;
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}
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}
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}
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}
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while (!done);
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}
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__forceinline void sif0Interrupt()
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{
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HW_DMA9_CHCR &= ~0x01000000;
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psxDmaInterrupt2(2);
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}
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__forceinline void sif1Interrupt()
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{
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HW_DMA10_CHCR &= ~0x01000000; //reset TR flag
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psxDmaInterrupt2(3);
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}
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__forceinline void EEsif0Interrupt()
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{
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sif0dma->chcr &= ~0x100;
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hwDmacIrq(DMAC_SIF0);
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}
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__forceinline void EEsif1Interrupt()
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{
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hwDmacIrq(DMAC_SIF1);
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sif1dma->chcr &= ~0x100;
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}
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__forceinline void dmaSIF0()
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{
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SIF_LOG("EE: dmaSIF0 chcr = %lx, madr = %lx, qwc = %lx, tadr = %lx",
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sif0dma->chcr, sif0dma->madr, sif0dma->qwc, sif0dma->tadr);
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if (sif0.fifoReadPos != sif0.fifoWritePos)
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{
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SIF_LOG("warning, sif0.fifoReadPos != sif0.fifoWritePos");
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}
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psHu32(SBUS_F240) |= 0x2000;
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eesifbusy[0] = 1;
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if (iopsifbusy[0] == 1)
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{
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FreezeXMMRegs(1);
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hwIntcIrq(INTC_SBUS);
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SIF0Dma();
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psHu32(SBUS_F240) &= ~0x20;
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psHu32(SBUS_F240) &= ~0x2000;
|
|
FreezeXMMRegs(0);
|
|
}
|
|
}
|
|
|
|
__forceinline void dmaSIF1()
|
|
{
|
|
SIF_LOG("EE: dmaSIF1 chcr = %lx, madr = %lx, qwc = %lx, tadr = %lx",
|
|
sif1dma->chcr, sif1dma->madr, sif1dma->qwc, sif1dma->tadr);
|
|
|
|
if (sif1.fifoReadPos != sif1.fifoWritePos)
|
|
{
|
|
SIF_LOG("warning, sif1.fifoReadPos != sif1.fifoWritePos");
|
|
}
|
|
|
|
psHu32(SBUS_F240) |= 0x4000;
|
|
eesifbusy[1] = 1;
|
|
if (iopsifbusy[1] == 1)
|
|
{
|
|
FreezeXMMRegs(1);
|
|
SIF1Dma();
|
|
psHu32(SBUS_F240) &= ~0x40;
|
|
psHu32(SBUS_F240) &= ~0x100;
|
|
psHu32(SBUS_F240) &= ~0x4000;
|
|
FreezeXMMRegs(0);
|
|
}
|
|
|
|
}
|
|
|
|
__forceinline void dmaSIF2()
|
|
{
|
|
SIF_LOG("dmaSIF2 chcr = %lx, madr = %lx, qwc = %lx",
|
|
sif2dma->chcr, sif2dma->madr, sif2dma->qwc);
|
|
|
|
sif2dma->chcr &= ~0x100;
|
|
hwDmacIrq(DMAC_SIF2);
|
|
Console::WriteLn("*PCSX2*: dmaSIF2");
|
|
}
|
|
|
|
|
|
void SaveState::sifFreeze()
|
|
{
|
|
FreezeTag("SIFdma");
|
|
|
|
Freeze(sif0);
|
|
Freeze(sif1);
|
|
|
|
Freeze(eesifbusy);
|
|
Freeze(iopsifbusy);
|
|
}
|