mirror of https://github.com/PCSX2/pcsx2.git
425 lines
8.3 KiB
C++
425 lines
8.3 KiB
C++
/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2002-2009 Pcsx2 Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include "R5900.h"
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#include "R5900OpcodeTables.h"
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#include <float.h>
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using namespace R5900; // for OPCODE and OpcodeImpl
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extern int vu0branch, vu1branch;
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static int branch2 = 0;
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static u32 cpuBlockCycles = 0; // 3 bit fixed point version of cycle count
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static std::string disOut;
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// These macros are used to assemble the repassembler functions
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static void debugI()
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{
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if( !IsDevBuild ) return;
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if( cpuRegs.GPR.n.r0.UD[0] || cpuRegs.GPR.n.r0.UD[1] ) Console::Error("R0 is not zero!!!!");
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}
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//long int runs=0;
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static void execI()
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{
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cpuRegs.code = memRead32( cpuRegs.pc );
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if( IsDebugBuild )
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debugI();
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const OPCODE& opcode = GetCurrentInstruction();
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//use this to find out what opcodes your game uses. very slow! (rama)
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//runs++;
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//if (runs > 1599999999){ //leave some time to startup the testgame
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// if (opcode.Name[0] == 'L') { //find all opcodes beginning with "L"
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// Console::WriteLn ("Load %s", params opcode.Name);
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// }
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//}
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// Another method of instruction dumping:
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/*if( cpuRegs.cycle > 0x4f24d714 )
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{
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//CPU_LOG( "%s", disR5900Current.getCString());
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disOut.clear();
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opcode.disasm( disOut );
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disOut += '\n';
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CPU_LOG( disOut.c_str() );
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}*/
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cpuBlockCycles += opcode.cycles;
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cpuRegs.pc += 4;
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opcode.interpret();
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}
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static bool EventRaised = false;
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static __forceinline void _doBranch_shared(u32 tar)
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{
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branch2 = cpuRegs.branch = 1;
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execI();
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// branch being 0 means an exception was thrown, since only the exception
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// handler should ever clear it.
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if( cpuRegs.branch != 0 )
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{
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cpuRegs.pc = tar;
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cpuRegs.branch = 0;
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}
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}
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static void __fastcall doBranch( u32 target )
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{
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_doBranch_shared( target );
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cpuRegs.cycle += cpuBlockCycles >> 3;
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cpuBlockCycles &= (1<<3)-1;
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EventRaised |= intEventTest();
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}
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void __fastcall intDoBranch(u32 target)
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{
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//Console::WriteLn("Interpreter Branch ");
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_doBranch_shared( target );
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if( Cpu == &intCpu )
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{
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cpuRegs.cycle += cpuBlockCycles >> 3;
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cpuBlockCycles &= (1<<3)-1;
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EventRaised |= intEventTest();
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}
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}
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void intSetBranch()
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{
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branch2 = /*cpuRegs.branch =*/ 1;
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}
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////////////////////////////////////////////////////////////////////
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// R5900 Branching Instructions!
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// These are the interpreter versions of the branch instructions. Unlike other
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// types of interpreter instructions which can be called safely from the recompilers,
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// these instructions are not "recSafe" because they may not invoke the
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// necessary branch test logic that the recs need to maintain sync with the
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// cpuRegs.pc and delaySlot instruction and such.
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namespace R5900 {
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namespace Interpreter {
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namespace OpcodeImpl {
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/*********************************************************
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* Jump to target *
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* Format: OP target *
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*********************************************************/
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// fixme: looking at the other branching code, shouldn't those _SetLinks in BGEZAL and such only be set
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// if the condition is true? --arcum42
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void J()
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{
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doBranch(_JumpTarget_);
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}
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void JAL()
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{
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_SetLink(31);
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doBranch(_JumpTarget_);
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}
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/*********************************************************
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* Register branch logic *
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* Format: OP rs, rt, offset *
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*********************************************************/
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void BEQ() // Branch if Rs == Rt
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] == cpuRegs.GPR.r[_Rt_].SD[0])
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doBranch(_BranchTarget_);
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else
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intEventTest();
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}
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void BNE() // Branch if Rs != Rt
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] != cpuRegs.GPR.r[_Rt_].SD[0])
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doBranch(_BranchTarget_);
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else
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intEventTest();
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}
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/*********************************************************
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* Register branch logic *
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* Format: OP rs, offset *
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*********************************************************/
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void BGEZ() // Branch if Rs >= 0
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
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{
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doBranch(_BranchTarget_);
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}
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}
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void BGEZAL() // Branch if Rs >= 0 and link
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
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{
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_SetLink(31);
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doBranch(_BranchTarget_);
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}
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}
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void BGTZ() // Branch if Rs > 0
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] > 0)
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{
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doBranch(_BranchTarget_);
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}
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}
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void BLEZ() // Branch if Rs <= 0
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] <= 0)
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{
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doBranch(_BranchTarget_);
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}
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}
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void BLTZ() // Branch if Rs < 0
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] < 0)
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{
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doBranch(_BranchTarget_);
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}
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}
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void BLTZAL() // Branch if Rs < 0 and link
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{
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if (cpuRegs.GPR.r[_Rs_].SD[0] < 0)
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{
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_SetLink(31);
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doBranch(_BranchTarget_);
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}
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}
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/*********************************************************
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* Register branch logic Likely *
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* Format: OP rs, offset *
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*********************************************************/
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void BEQL() // Branch if Rs == Rt
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] == cpuRegs.GPR.r[_Rt_].SD[0])
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BNEL() // Branch if Rs != Rt
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] != cpuRegs.GPR.r[_Rt_].SD[0])
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BLEZL() // Branch if Rs <= 0
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] <= 0)
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BGTZL() // Branch if Rs > 0
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] > 0)
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BLTZL() // Branch if Rs < 0
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] < 0)
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BGEZL() // Branch if Rs >= 0
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
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{
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BLTZALL() // Branch if Rs < 0 and link
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] < 0)
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{
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_SetLink(31);
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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void BGEZALL() // Branch if Rs >= 0 and link
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{
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if(cpuRegs.GPR.r[_Rs_].SD[0] >= 0)
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{
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_SetLink(31);
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doBranch(_BranchTarget_);
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}
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else
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{
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cpuRegs.pc +=4;
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intEventTest();
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}
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}
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/*********************************************************
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* Register jump *
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* Format: OP rs, rd *
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*********************************************************/
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void JR()
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{
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doBranch(cpuRegs.GPR.r[_Rs_].UL[0]);
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}
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void JALR()
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{
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u32 temp = cpuRegs.GPR.r[_Rs_].UL[0];
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if (_Rd_) _SetLink(_Rd_);
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doBranch(temp);
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}
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} } } // end namespace R5900::Interpreter::OpcodeImpl
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////////////////////////////////////////////////////////
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void intAlloc()
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{
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// fixme : detect cpu for use the optimize asm code
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}
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void intReset()
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{
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cpuRegs.branch = 0;
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branch2 = 0;
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}
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bool intEventTest()
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{
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// Perform counters, ints, and IOP updates:
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return _cpuBranchTest_Shared();
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}
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void intExecute()
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{
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g_EEFreezeRegs = false;
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// Mem protection should be handled by the caller here so that it can be
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// done in a more optimized fashion.
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EventRaised = false;
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while( !EventRaised )
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{
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execI();
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}
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}
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static void intExecuteBlock()
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{
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g_EEFreezeRegs = false;
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branch2 = 0;
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while (!branch2) execI();
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}
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static void intStep()
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{
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g_EEFreezeRegs = false;
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execI();
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}
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static void intClear(u32 Addr, u32 Size)
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{
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}
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static void intShutdown() {
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}
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R5900cpu intCpu = {
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intAlloc,
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intReset,
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intStep,
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intExecute,
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intExecuteBlock,
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intClear,
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intShutdown
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};
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