mirror of https://github.com/PCSX2/pcsx2.git
986 lines
31 KiB
C++
986 lines
31 KiB
C++
/* PCSX2 - PS2 Emulator for PCs
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* Copyright (C) 2002-2010 PCSX2 Dev Team
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*
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms
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* of the GNU Lesser General Public License as published by the Free Software Found-
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* ation, either version 3 of the License, or (at your option) any later version.
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*
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with PCSX2.
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* If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "PrecompiledHeader.h"
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#include "Common.h"
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#include <float.h>
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#include "R5900.h"
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#include "R5900OpcodeTables.h"
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#include "R5900Exceptions.h"
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static __fi bool _add64_Overflow( s64 x, s64 y, s64 &ret )
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{
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const s64 result = x + y;
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// Let's all give gigaherz a big round of applause for finding this gem,
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// which apparently works, and generates compact/fast x86 code too (the
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// other method below is like 5-10 times slower).
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if( ((~(x^y))&(x^result)) < 0 ) {
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cpuException(0x30, cpuRegs.branch); // fixme: is 0x30 right for overflow??
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return true;
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}
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// the not-as-fast style!
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//if( ((x >= 0) && (y >= 0) && (result < 0)) ||
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// ((x < 0) && (y < 0) && (result >= 0)) )
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// cpuException(0x30, cpuRegs.branch);
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ret = result;
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return false;
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}
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static __fi bool _add32_Overflow( s32 x, s32 y, s64 &ret )
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{
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GPR_reg64 result; result.SD[0] = (s64)x + y;
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// This 32bit method can rely on the MIPS documented method of checking for
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// overflow, whichs imply compares bit 32 (rightmost bit of the upper word),
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// against bit 31 (leftmost of the lower word).
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// If bit32 != bit31 then we have an overflow.
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if( (result.UL[0]>>31) != (result.UL[1] & 1) ) {
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cpuException(0x30, cpuRegs.branch);
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return true;
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}
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ret = result.SD[0];
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return false;
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}
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const R5900::OPCODE& R5900::GetCurrentInstruction()
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{
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const OPCODE* opcode = &R5900::OpcodeTables::tbl_Standard[_Opcode_];
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while( opcode->getsubclass != NULL )
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opcode = &opcode->getsubclass();
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return *opcode;
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}
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const char * const R5900::bios[256]=
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{
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//0x00
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"RFU000_FullReset", "ResetEE", "SetGsCrt", "RFU003",
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"Exit", "RFU005", "LoadExecPS2", "ExecPS2",
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"RFU008", "RFU009", "AddSbusIntcHandler", "RemoveSbusIntcHandler",
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"Interrupt2Iop", "SetVTLBRefillHandler", "SetVCommonHandler", "SetVInterruptHandler",
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//0x10
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"AddIntcHandler", "RemoveIntcHandler", "AddDmacHandler", "RemoveDmacHandler",
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"_EnableIntc", "_DisableIntc", "_EnableDmac", "_DisableDmac",
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"_SetAlarm", "_ReleaseAlarm", "_iEnableIntc", "_iDisableIntc",
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"_iEnableDmac", "_iDisableDmac", "_iSetAlarm", "_iReleaseAlarm",
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//0x20
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"CreateThread", "DeleteThread", "StartThread", "ExitThread",
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"ExitDeleteThread", "TerminateThread", "iTerminateThread", "DisableDispatchThread",
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"EnableDispatchThread", "ChangeThreadPriority", "iChangeThreadPriority", "RotateThreadReadyQueue",
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"iRotateThreadReadyQueue", "ReleaseWaitThread", "iReleaseWaitThread", "GetThreadId",
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//0x30
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"ReferThreadStatus","iReferThreadStatus", "SleepThread", "WakeupThread",
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"_iWakeupThread", "CancelWakeupThread", "iCancelWakeupThread", "SuspendThread",
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"iSuspendThread", "ResumeThread", "iResumeThread", "JoinThread",
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"RFU060", "RFU061", "EndOfHeap", "RFU063",
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//0x40
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"CreateSema", "DeleteSema", "SignalSema", "iSignalSema",
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"WaitSema", "PollSema", "iPollSema", "ReferSemaStatus",
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"iReferSemaStatus", "RFU073", "SetOsdConfigParam", "GetOsdConfigParam",
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"GetGsHParam", "GetGsVParam", "SetGsHParam", "SetGsVParam",
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//0x50
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"RFU080_CreateEventFlag", "RFU081_DeleteEventFlag",
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"RFU082_SetEventFlag", "RFU083_iSetEventFlag",
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"RFU084_ClearEventFlag", "RFU085_iClearEventFlag",
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"RFU086_WaitEventFlag", "RFU087_PollEventFlag",
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"RFU088_iPollEventFlag", "RFU089_ReferEventFlagStatus",
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"RFU090_iReferEventFlagStatus", "RFU091_GetEntryAddress",
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"EnableIntcHandler_iEnableIntcHandler",
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"DisableIntcHandler_iDisableIntcHandler",
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"EnableDmacHandler_iEnableDmacHandler",
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"DisableDmacHandler_iDisableDmacHandler",
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//0x60
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"KSeg0", "EnableCache", "DisableCache", "GetCop0",
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"FlushCache", "RFU101", "CpuConfig", "iGetCop0",
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"iFlushCache", "RFU105", "iCpuConfig", "sceSifStopDma",
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"SetCPUTimerHandler", "SetCPUTimer", "SetOsdConfigParam2", "SetOsdConfigParam2",
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//0x70
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"GsGetIMR_iGsGetIMR", "GsGetIMR_iGsPutIMR", "SetPgifHandler", "SetVSyncFlag",
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"RFU116", "print", "sceSifDmaStat_isceSifDmaStat", "sceSifSetDma_isceSifSetDma",
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"sceSifSetDChain_isceSifSetDChain", "sceSifSetReg", "sceSifGetReg", "ExecOSD",
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"Deci2Call", "PSMode", "MachineType", "GetMemorySize",
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};
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static u32 deci2addr = 0;
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static u32 deci2handler = 0;
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static char deci2buffer[256];
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void Deci2Reset()
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{
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deci2handler = 0;
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deci2addr = 0;
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memzero( deci2buffer );
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}
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void SaveStateBase::deci2Freeze()
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{
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FreezeTag( "deci2" );
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Freeze( deci2addr );
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Freeze( deci2handler );
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Freeze( deci2buffer );
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}
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/*
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* int Deci2Call(int, u_int *);
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*
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* HLE implementation of the Deci2 interface.
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*/
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static int __Deci2Call(int call, u32 *addr)
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{
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if (call > 0x10)
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return -1;
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switch (call)
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{
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case 1: // open
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if( addr != NULL )
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{
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deci2addr = addr[1];
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BIOS_LOG("deci2open: %x,%x,%x,%x",
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addr[3], addr[2], addr[1], addr[0]);
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deci2handler = addr[2];
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}
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else
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{
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deci2handler = 0;
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DevCon.Warning( "Deci2Call.Open > NULL address ignored." );
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}
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return 1;
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case 2: // close
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deci2addr = 0;
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deci2handler = 0;
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return 1;
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case 3: // reqsend
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{
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char reqaddr[128];
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if( addr != NULL )
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sprintf( reqaddr, "%x %x %x %x", addr[3], addr[2], addr[1], addr[0] );
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if (!deci2addr) return 1;
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const u32* d2ptr = (u32*)PSM(deci2addr);
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BIOS_LOG("deci2reqsend: %s: deci2addr: %x,%x,%x,buf=%x %x,%x,len=%x,%x",
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(( addr == NULL ) ? "NULL" : reqaddr),
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d2ptr[7], d2ptr[6], d2ptr[5], d2ptr[4],
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d2ptr[3], d2ptr[2], d2ptr[1], d2ptr[0]);
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// cpuRegs.pc = deci2handler;
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// Console.WriteLn("deci2msg: %s", (char*)PSM(d2ptr[4]+0xc));
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if (d2ptr[1]>0xc){
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// this looks horribly wrong, justification please?
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u8* pdeciaddr = (u8*)dmaGetAddr(d2ptr[4]+0xc, false);
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if( pdeciaddr == NULL )
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pdeciaddr = (u8*)PSM(d2ptr[4]+0xc);
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else
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pdeciaddr += (d2ptr[4]+0xc) % 16;
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const int copylen = std::min<uint>(255, d2ptr[1]-0xc);
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memcpy_fast(deci2buffer, pdeciaddr, copylen );
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deci2buffer[copylen] = '\0';
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eeConLog( ShiftJIS_ConvertString(deci2buffer) );
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}
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((u32*)PSM(deci2addr))[3] = 0;
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return 1;
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}
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case 4: // poll
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if( addr != NULL )
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BIOS_LOG("deci2poll: %x,%x,%x,%x\n", addr[3], addr[2], addr[1], addr[0]);
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return 1;
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case 5: // exrecv
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return 1;
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case 6: // exsend
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return 1;
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case 0x10://kputs
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if( addr != NULL )
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{
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eeDeci2Log( ShiftJIS_ConvertString((char*)PSM(*addr)) );
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}
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return 1;
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}
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return 0;
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}
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namespace R5900 {
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namespace Interpreter {
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namespace OpcodeImpl {
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void COP2()
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{
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//std::string disOut;
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//disR5900Fasm(disOut, cpuRegs.code, cpuRegs.pc);
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//VU0_LOG("%s", disOut.c_str());
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Int_COP2PrintTable[_Rs_]();
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}
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void Unknown() {
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CPU_LOG("%8.8lx: Unknown opcode called", cpuRegs.pc);
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}
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void MMI_Unknown() { Console.Warning("Unknown MMI opcode called"); }
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void COP0_Unknown() { Console.Warning("Unknown COP0 opcode called"); }
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void COP1_Unknown() { Console.Warning("Unknown FPU/COP1 opcode called"); }
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/*********************************************************
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* Arithmetic with immediate operand *
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* Format: OP rt, rs, immediate *
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*********************************************************/
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// Implementation Notes:
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// * It is important that instructions perform overflow checks prior to shortcutting on
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// the zero register (when it is used as a destination). Overflow exceptions are still
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// handled even though the result is discarded.
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// Rt = Rs + Im signed [exception on overflow]
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void ADDI()
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{
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s64 result;
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bool overflow = _add32_Overflow( cpuRegs.GPR.r[_Rs_].SD[0], _Imm_, result );
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if (overflow || !_Rt_) return;
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cpuRegs.GPR.r[_Rt_].SD[0] = result;
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}
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// Rt = Rs + Im signed !!! [overflow ignored]
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// This instruction is effectively identical to ADDI. It is not a true unsigned operation,
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// but rather it is a signed operation that ignores overflows.
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void ADDIU()
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{
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if (!_Rt_) return;
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cpuRegs.GPR.r[_Rt_].SD[0] = cpuRegs.GPR.r[_Rs_].SL[0] + _Imm_;
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}
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// Rt = Rs + Im [exception on overflow]
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// This is the full 64 bit version of ADDI. Overflow occurs at 64 bits instead
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// of at 32 bits.
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void DADDI()
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{
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s64 result;
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bool overflow = _add64_Overflow( cpuRegs.GPR.r[_Rs_].SD[0], _Imm_, result );
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if (overflow || !_Rt_) return;
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cpuRegs.GPR.r[_Rt_].SD[0] = result;
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}
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// Rt = Rs + Im [overflow ignored]
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// This instruction is effectively identical to DADDI. It is not a true unsigned operation,
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// but rather it is a signed operation that ignores overflows.
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void DADDIU()
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{
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if (!_Rt_) return;
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cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] + _Imm_;
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}
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void ANDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] & (u64)_ImmU_; } // Rt = Rs And Im (zero-extended)
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void ORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] | (u64)_ImmU_; } // Rt = Rs Or Im (zero-extended)
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void XORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] ^ (u64)_ImmU_; } // Rt = Rs Xor Im (zero-extended)
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void SLTI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = (cpuRegs.GPR.r[_Rs_].SD[0] < (s64)(_Imm_)) ? 1 : 0; } // Rt = Rs < Im (signed)
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void SLTIU() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = (cpuRegs.GPR.r[_Rs_].UD[0] < (u64)(_Imm_)) ? 1 : 0; } // Rt = Rs < Im (unsigned)
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/*********************************************************
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* Register arithmetic *
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* Format: OP rd, rs, rt *
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*********************************************************/
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// Rd = Rs + Rt (Exception on Integer Overflow)
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void ADD()
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{
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s64 result;
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bool overflow = _add32_Overflow( cpuRegs.GPR.r[_Rs_].SD[0], cpuRegs.GPR.r[_Rt_].SD[0], result );
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if (overflow || !_Rd_) return;
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cpuRegs.GPR.r[_Rd_].SD[0] = result;
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}
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void DADD()
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{
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s64 result;
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bool overflow = _add64_Overflow( cpuRegs.GPR.r[_Rs_].SD[0], cpuRegs.GPR.r[_Rt_].SD[0], result );
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if (overflow || !_Rd_) return;
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cpuRegs.GPR.r[_Rd_].SD[0] = result;
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}
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// Rd = Rs - Rt (Exception on Integer Overflow)
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void SUB()
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{
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s64 result;
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bool overflow = _add32_Overflow( cpuRegs.GPR.r[_Rs_].SD[0], -cpuRegs.GPR.r[_Rt_].SD[0], result );
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if (overflow || !_Rd_) return;
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cpuRegs.GPR.r[_Rd_].SD[0] = result;
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}
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// Rd = Rs - Rt (Exception on Integer Overflow)
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void DSUB()
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{
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s64 result;
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bool overflow = _add64_Overflow( cpuRegs.GPR.r[_Rs_].SD[0], -cpuRegs.GPR.r[_Rt_].SD[0], result );
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if (overflow || !_Rd_) return;
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cpuRegs.GPR.r[_Rd_].SD[0] = result;
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}
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void ADDU() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rs_].SL[0] + cpuRegs.GPR.r[_Rt_].SL[0];} // Rd = Rs + Rt
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void DADDU() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] + cpuRegs.GPR.r[_Rt_].SD[0]; }
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void SUBU() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rs_].SL[0] - cpuRegs.GPR.r[_Rt_].SL[0]; } // Rd = Rs - Rt
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void DSUBU() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] - cpuRegs.GPR.r[_Rt_].SD[0]; }
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void AND() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] & cpuRegs.GPR.r[_Rt_].UD[0]; } // Rd = Rs And Rt
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void OR() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] | cpuRegs.GPR.r[_Rt_].UD[0]; } // Rd = Rs Or Rt
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void XOR() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] ^ cpuRegs.GPR.r[_Rt_].UD[0]; } // Rd = Rs Xor Rt
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void NOR() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] =~(cpuRegs.GPR.r[_Rs_].UD[0] | cpuRegs.GPR.r[_Rt_].UD[0]); }// Rd = Rs Nor Rt
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void SLT() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = (cpuRegs.GPR.r[_Rs_].SD[0] < cpuRegs.GPR.r[_Rt_].SD[0]) ? 1 : 0; } // Rd = Rs < Rt (signed)
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void SLTU() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = (cpuRegs.GPR.r[_Rs_].UD[0] < cpuRegs.GPR.r[_Rt_].UD[0]) ? 1 : 0; } // Rd = Rs < Rt (unsigned)
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/*********************************************************
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* Register mult/div & Register trap logic *
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* Format: OP rs, rt *
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*********************************************************/
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// Signed division "overflows" on (0x80000000 / -1), here (LO = 0x80000000, HI = 0) is returned by MIPS
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// in division by zero on MIPS, it appears that:
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// LO gets 1 if rs is negative (and the division is signed) and -1 otherwise.
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// HI gets the value of rs.
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// Result is stored in HI/LO [no arithmetic exceptions]
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void DIV()
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{
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if (cpuRegs.GPR.r[_Rs_].UL[0] == 0x80000000 && cpuRegs.GPR.r[_Rt_].UL[0] == 0xffffffff)
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{
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cpuRegs.LO.SD[0] = (s32)0x80000000;
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cpuRegs.HI.SD[0] = (s32)0x0;
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}
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else if (cpuRegs.GPR.r[_Rt_].SL[0] != 0)
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{
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cpuRegs.LO.SD[0] = cpuRegs.GPR.r[_Rs_].SL[0] / cpuRegs.GPR.r[_Rt_].SL[0];
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cpuRegs.HI.SD[0] = cpuRegs.GPR.r[_Rs_].SL[0] % cpuRegs.GPR.r[_Rt_].SL[0];
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}
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else
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{
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cpuRegs.LO.SD[0] = (cpuRegs.GPR.r[_Rs_].SL[0] < 0) ? 1 : -1;
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cpuRegs.HI.SD[0] = cpuRegs.GPR.r[_Rs_].SL[0];
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}
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}
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// Result is stored in HI/LO [no arithmetic exceptions]
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void DIVU()
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{
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if (cpuRegs.GPR.r[_Rt_].UL[0] != 0)
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{
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// note: DIVU has no sign extension when assigning back to 64 bits
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// note 2: reference material strongly disagrees. (air)
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cpuRegs.LO.SD[0] = (s32)(cpuRegs.GPR.r[_Rs_].UL[0] / cpuRegs.GPR.r[_Rt_].UL[0]);
|
|
cpuRegs.HI.SD[0] = (s32)(cpuRegs.GPR.r[_Rs_].UL[0] % cpuRegs.GPR.r[_Rt_].UL[0]);
|
|
}
|
|
else
|
|
{
|
|
cpuRegs.LO.SD[0] = -1;
|
|
cpuRegs.HI.SD[0] = cpuRegs.GPR.r[_Rs_].SL[0];
|
|
}
|
|
}
|
|
|
|
// Result is written to both HI/LO and to the _Rd_ (Lo only)
|
|
void MULT()
|
|
{
|
|
s64 res = (s64)cpuRegs.GPR.r[_Rs_].SL[0] * cpuRegs.GPR.r[_Rt_].SL[0];
|
|
|
|
// Sign-extend into 64 bits:
|
|
cpuRegs.LO.SD[0] = (s32)(res & 0xffffffff);
|
|
cpuRegs.HI.SD[0] = (s32)(res >> 32);
|
|
|
|
if( _Rd_ ) cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.LO.UD[0];
|
|
}
|
|
|
|
// Result is written to both HI/LO and to the _Rd_ (Lo only)
|
|
void MULTU()
|
|
{
|
|
u64 res = (u64)cpuRegs.GPR.r[_Rs_].UL[0] * cpuRegs.GPR.r[_Rt_].UL[0];
|
|
|
|
// Note: sign-extend into 64 bits even though it's an unsigned mult.
|
|
cpuRegs.LO.SD[0] = (s32)(res & 0xffffffff);
|
|
cpuRegs.HI.SD[0] = (s32)(res >> 32);
|
|
|
|
if( _Rd_ ) cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.LO.UD[0];
|
|
}
|
|
|
|
/*********************************************************
|
|
* Load higher 16 bits of the first word in GPR with imm *
|
|
* Format: OP rt, immediate *
|
|
*********************************************************/
|
|
void LUI() {
|
|
if (!_Rt_) return;
|
|
cpuRegs.GPR.r[_Rt_].UD[0] = (s32)(cpuRegs.code << 16);
|
|
}
|
|
|
|
/*********************************************************
|
|
* Move from HI/LO to GPR *
|
|
* Format: OP rd *
|
|
*********************************************************/
|
|
void MFHI() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.HI.UD[0]; } // Rd = Hi
|
|
void MFLO() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.LO.UD[0]; } // Rd = Lo
|
|
|
|
/*********************************************************
|
|
* Move to GPR to HI/LO & Register jump *
|
|
* Format: OP rs *
|
|
*********************************************************/
|
|
void MTHI() { cpuRegs.HI.UD[0] = cpuRegs.GPR.r[_Rs_].UD[0]; } // Hi = Rs
|
|
void MTLO() { cpuRegs.LO.UD[0] = cpuRegs.GPR.r[_Rs_].UD[0]; } // Lo = Rs
|
|
|
|
|
|
/*********************************************************
|
|
* Shift arithmetic with constant shift *
|
|
* Format: OP rd, rt, sa *
|
|
*********************************************************/
|
|
void SRA() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].SD[0] = (s32)(cpuRegs.GPR.r[_Rt_].SL[0] >> _Sa_); } // Rd = Rt >> sa (arithmetic)
|
|
void SRL() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].SD[0] = (s32)(cpuRegs.GPR.r[_Rt_].UL[0] >> _Sa_); } // Rd = Rt >> sa (logical) [sign extend!!]
|
|
void SLL() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].SD[0] = (s32)(cpuRegs.GPR.r[_Rt_].UL[0] << _Sa_); } // Rd = Rt << sa
|
|
void DSLL() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = (u64)(cpuRegs.GPR.r[_Rt_].UD[0] << _Sa_); }
|
|
void DSLL32(){ if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = (u64)(cpuRegs.GPR.r[_Rt_].UD[0] << (_Sa_+32));}
|
|
void DSRA() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].SD[0] = cpuRegs.GPR.r[_Rt_].SD[0] >> _Sa_; }
|
|
void DSRA32(){ if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].SD[0] = cpuRegs.GPR.r[_Rt_].SD[0] >> (_Sa_+32);}
|
|
void DSRL() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rt_].UD[0] >> _Sa_; }
|
|
void DSRL32(){ if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rt_].UD[0] >> (_Sa_+32);}
|
|
|
|
/*********************************************************
|
|
* Shift arithmetic with variant register shift *
|
|
* Format: OP rd, rt, rs *
|
|
*********************************************************/
|
|
void SLLV() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].SD[0] = (s32)(cpuRegs.GPR.r[_Rt_].UL[0] << (cpuRegs.GPR.r[_Rs_].UL[0] &0x1f));} // Rd = Rt << rs
|
|
void SRAV() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].SD[0] = (s32)(cpuRegs.GPR.r[_Rt_].SL[0] >> (cpuRegs.GPR.r[_Rs_].UL[0] &0x1f));} // Rd = Rt >> rs (arithmetic)
|
|
void SRLV() { if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].SD[0] = (s32)(cpuRegs.GPR.r[_Rt_].UL[0] >> (cpuRegs.GPR.r[_Rs_].UL[0] &0x1f));} // Rd = Rt >> rs (logical)
|
|
void DSLLV(){ if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = (u64)(cpuRegs.GPR.r[_Rt_].UD[0] << (cpuRegs.GPR.r[_Rs_].UL[0] &0x3f));}
|
|
void DSRAV(){ if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].SD[0] = (s64)(cpuRegs.GPR.r[_Rt_].SD[0] >> (cpuRegs.GPR.r[_Rs_].UL[0] &0x3f));}
|
|
void DSRLV(){ if (!_Rd_) return; cpuRegs.GPR.r[_Rd_].UD[0] = (u64)(cpuRegs.GPR.r[_Rt_].UD[0] >> (cpuRegs.GPR.r[_Rs_].UL[0] &0x3f));}
|
|
|
|
/*********************************************************
|
|
* Load and store for GPR *
|
|
* Format: OP rt, offset(base) *
|
|
*********************************************************/
|
|
|
|
// Implementation Notes Regarding Memory Operations:
|
|
// * It it 'correct' to do all loads into temp variables, even if the destination GPR
|
|
// is the zero reg (which nullifies the result). The memory needs to be accessed
|
|
// regardless so that hardware registers behave as expected (some clear on read) and
|
|
// so that TLB Misses are handled as expected as well.
|
|
//
|
|
// * Low/High varieties of instructions, such as LWL/LWH, do *not* raise Address Error
|
|
// exceptions, since the lower bits of the address are used to determine the portions
|
|
// of the address/register operations.
|
|
|
|
|
|
void LB()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
s8 temp = memRead8(addr);
|
|
|
|
if (!_Rt_) return;
|
|
cpuRegs.GPR.r[_Rt_].SD[0] = temp;
|
|
}
|
|
|
|
void LBU()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
u8 temp = memRead8(addr);
|
|
|
|
if (!_Rt_) return;
|
|
cpuRegs.GPR.r[_Rt_].UD[0] = temp;
|
|
}
|
|
|
|
void LH()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
|
|
if( addr & 1 )
|
|
throw R5900Exception::AddressError( addr, false );
|
|
|
|
s16 temp = memRead16(addr);
|
|
|
|
if (!_Rt_) return;
|
|
cpuRegs.GPR.r[_Rt_].SD[0] = temp;
|
|
}
|
|
|
|
void LHU()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
|
|
if( addr & 1 )
|
|
throw R5900Exception::AddressError( addr, false );
|
|
|
|
u16 temp = memRead16(addr);
|
|
|
|
if (!_Rt_) return;
|
|
cpuRegs.GPR.r[_Rt_].UD[0] = temp;
|
|
}
|
|
|
|
void LW()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
|
|
if( addr & 3 )
|
|
throw R5900Exception::AddressError( addr, false );
|
|
|
|
u32 temp = memRead32(addr);
|
|
|
|
if (!_Rt_) return;
|
|
cpuRegs.GPR.r[_Rt_].SD[0] = (s32)temp;
|
|
}
|
|
|
|
void LWU()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
|
|
if( addr & 3 )
|
|
throw R5900Exception::AddressError( addr, false );
|
|
|
|
u32 temp = memRead32(addr);
|
|
|
|
if (!_Rt_) return;
|
|
cpuRegs.GPR.r[_Rt_].UD[0] = temp;
|
|
}
|
|
|
|
static const s32 LWL_MASK[4] = { 0xffffff, 0x0000ffff, 0x000000ff, 0x00000000 };
|
|
static const s32 LWR_MASK[4] = { 0x000000, 0xff000000, 0xffff0000, 0xffffff00 };
|
|
static const u8 LWL_SHIFT[4] = { 24, 16, 8, 0 };
|
|
static const u8 LWR_SHIFT[4] = { 0, 8, 16, 24 };
|
|
|
|
void LWL()
|
|
{
|
|
s32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
u32 shift = addr & 3;
|
|
|
|
// ensure the compiler does correct sign extension into 64 bits by using s32
|
|
s32 mem = memRead32(addr & ~3);
|
|
|
|
if (!_Rt_) return;
|
|
|
|
cpuRegs.GPR.r[_Rt_].SD[0] = (cpuRegs.GPR.r[_Rt_].SL[0] & LWL_MASK[shift]) |
|
|
(mem << LWL_SHIFT[shift]);
|
|
|
|
/*
|
|
Mem = 1234. Reg = abcd
|
|
(result is always sign extended into the upper 32 bits of the Rt)
|
|
|
|
0 4bcd (mem << 24) | (reg & 0x00ffffff)
|
|
1 34cd (mem << 16) | (reg & 0x0000ffff)
|
|
2 234d (mem << 8) | (reg & 0x000000ff)
|
|
3 1234 (mem ) | (reg & 0x00000000)
|
|
*/
|
|
}
|
|
|
|
void LWR()
|
|
{
|
|
s32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
u32 shift = addr & 3;
|
|
|
|
u32 mem = memRead32(addr & ~3);
|
|
|
|
if (!_Rt_) return;
|
|
|
|
// Use unsigned math here, and conditionally sign extend below, when needed.
|
|
mem = (cpuRegs.GPR.r[_Rt_].UL[0] & LWR_MASK[shift]) | (mem >> LWR_SHIFT[shift]);
|
|
|
|
if( shift == 0 )
|
|
{
|
|
// This special case requires sign extension into the full 64 bit dest.
|
|
cpuRegs.GPR.r[_Rt_].SD[0] = (s32)mem;
|
|
}
|
|
else
|
|
{
|
|
// This case sets the lower 32 bits of the target register. Upper
|
|
// 32 bits are always preserved.
|
|
cpuRegs.GPR.r[_Rt_].UL[0] = mem;
|
|
}
|
|
|
|
/*
|
|
Mem = 1234. Reg = abcd
|
|
|
|
0 1234 (mem ) | (reg & 0x00000000) [sign extend into upper 32 bits!]
|
|
1 a123 (mem >> 8) | (reg & 0xff000000)
|
|
2 ab12 (mem >> 16) | (reg & 0xffff0000)
|
|
3 abc1 (mem >> 24) | (reg & 0xffffff00)
|
|
*/
|
|
}
|
|
|
|
// dummy variable used as a destination address for writes to the zero register, so
|
|
// that the zero register always stays zero.
|
|
static __aligned16 GPR_reg m_dummy_gpr_zero;
|
|
|
|
// Returns the x86 address of the requested GPR, which is safe for writing. (includes
|
|
// special handling for returning a dummy var for GPR0(zero), so that it's value is
|
|
// always preserved)
|
|
static GPR_reg* gpr_GetWritePtr( uint gpr )
|
|
{
|
|
return (( gpr == 0 ) ? &m_dummy_gpr_zero : &cpuRegs.GPR.r[gpr]);
|
|
}
|
|
|
|
void LD()
|
|
{
|
|
s32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
|
|
if( addr & 7 )
|
|
throw R5900Exception::AddressError( addr, false );
|
|
|
|
memRead64(addr, (u64*)gpr_GetWritePtr(_Rt_));
|
|
}
|
|
|
|
static const u64 LDL_MASK[8] =
|
|
{ 0x00ffffffffffffffLL, 0x0000ffffffffffffLL, 0x000000ffffffffffLL, 0x00000000ffffffffLL,
|
|
0x0000000000ffffffLL, 0x000000000000ffffLL, 0x00000000000000ffLL, 0x0000000000000000LL
|
|
};
|
|
static const u64 LDR_MASK[8] =
|
|
{ 0x0000000000000000LL, 0xff00000000000000LL, 0xffff000000000000LL, 0xffffff0000000000LL,
|
|
0xffffffff00000000LL, 0xffffffffff000000LL, 0xffffffffffff0000LL, 0xffffffffffffff00LL
|
|
};
|
|
|
|
static const u8 LDR_SHIFT[8] = { 0, 8, 16, 24, 32, 40, 48, 56 };
|
|
static const u8 LDL_SHIFT[8] = { 56, 48, 40, 32, 24, 16, 8, 0 };
|
|
|
|
|
|
void LDL()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
u32 shift = addr & 7;
|
|
|
|
u64 mem;
|
|
memRead64(addr & ~7, &mem);
|
|
|
|
if( !_Rt_ ) return;
|
|
cpuRegs.GPR.r[_Rt_].UD[0] = (cpuRegs.GPR.r[_Rt_].UD[0] & LDL_MASK[shift]) |
|
|
(mem << LDL_SHIFT[shift]);
|
|
}
|
|
|
|
void LDR()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
u32 shift = addr & 7;
|
|
|
|
u64 mem;
|
|
memRead64(addr & ~7, &mem);
|
|
|
|
if (!_Rt_) return;
|
|
cpuRegs.GPR.r[_Rt_].UD[0] = (cpuRegs.GPR.r[_Rt_].UD[0] & LDR_MASK[shift]) |
|
|
(mem >> LDR_SHIFT[shift]);
|
|
}
|
|
|
|
void LQ()
|
|
{
|
|
// MIPS Note: LQ and SQ are special and "silently" align memory addresses, thus
|
|
// an address error due to unaligned access isn't possible like it is on other loads/stores.
|
|
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
memRead128(addr & ~0xf, (u128*)gpr_GetWritePtr(_Rt_));
|
|
}
|
|
|
|
void SB()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
memWrite8(addr, cpuRegs.GPR.r[_Rt_].UC[0]);
|
|
}
|
|
|
|
void SH()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
|
|
if( addr & 1 )
|
|
throw R5900Exception::AddressError( addr, true );
|
|
|
|
memWrite16(addr, cpuRegs.GPR.r[_Rt_].US[0]);
|
|
}
|
|
|
|
void SW()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
|
|
if( addr & 3 )
|
|
throw R5900Exception::AddressError( addr, true );
|
|
|
|
memWrite32(addr, cpuRegs.GPR.r[_Rt_].UL[0]);
|
|
}
|
|
|
|
static const u32 SWL_MASK[4] = { 0xffffff00, 0xffff0000, 0xff000000, 0x00000000 };
|
|
static const u32 SWR_MASK[4] = { 0x00000000, 0x000000ff, 0x0000ffff, 0x00ffffff };
|
|
|
|
static const u8 SWR_SHIFT[4] = { 0, 8, 16, 24 };
|
|
static const u8 SWL_SHIFT[4] = { 24, 16, 8, 0 };
|
|
|
|
void SWL()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
u32 shift = addr & 3;
|
|
u32 mem = memRead32( addr & ~3 );
|
|
|
|
memWrite32( addr & ~3,
|
|
(cpuRegs.GPR.r[_Rt_].UL[0] >> SWL_SHIFT[shift]) |
|
|
(mem & SWL_MASK[shift])
|
|
);
|
|
|
|
/*
|
|
Mem = 1234. Reg = abcd
|
|
|
|
0 123a (reg >> 24) | (mem & 0xffffff00)
|
|
1 12ab (reg >> 16) | (mem & 0xffff0000)
|
|
2 1abc (reg >> 8) | (mem & 0xff000000)
|
|
3 abcd (reg ) | (mem & 0x00000000)
|
|
*/
|
|
}
|
|
|
|
void SWR() {
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
u32 shift = addr & 3;
|
|
u32 mem = memRead32(addr & ~3);
|
|
|
|
memWrite32( addr & ~3,
|
|
(cpuRegs.GPR.r[_Rt_].UL[0] << SWR_SHIFT[shift]) |
|
|
(mem & SWR_MASK[shift])
|
|
);
|
|
|
|
/*
|
|
Mem = 1234. Reg = abcd
|
|
|
|
0 abcd (reg ) | (mem & 0x00000000)
|
|
1 bcd4 (reg << 8) | (mem & 0x000000ff)
|
|
2 cd34 (reg << 16) | (mem & 0x0000ffff)
|
|
3 d234 (reg << 24) | (mem & 0x00ffffff)
|
|
*/
|
|
}
|
|
|
|
void SD()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
|
|
if( addr & 7 )
|
|
throw R5900Exception::AddressError( addr, true );
|
|
|
|
memWrite64(addr,&cpuRegs.GPR.r[_Rt_].UD[0]);
|
|
}
|
|
|
|
static const u64 SDL_MASK[8] =
|
|
{ 0xffffffffffffff00LL, 0xffffffffffff0000LL, 0xffffffffff000000LL, 0xffffffff00000000LL,
|
|
0xffffff0000000000LL, 0xffff000000000000LL, 0xff00000000000000LL, 0x0000000000000000LL
|
|
};
|
|
static const u64 SDR_MASK[8] =
|
|
{ 0x0000000000000000LL, 0x00000000000000ffLL, 0x000000000000ffffLL, 0x0000000000ffffffLL,
|
|
0x00000000ffffffffLL, 0x000000ffffffffffLL, 0x0000ffffffffffffLL, 0x00ffffffffffffffLL
|
|
};
|
|
|
|
static const u8 SDL_SHIFT[8] = { 56, 48, 40, 32, 24, 16, 8, 0 };
|
|
static const u8 SDR_SHIFT[8] = { 0, 8, 16, 24, 32, 40, 48, 56 };
|
|
|
|
void SDL()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
u32 shift = addr & 7;
|
|
u64 mem;
|
|
|
|
memRead64(addr & ~7, &mem);
|
|
mem = (cpuRegs.GPR.r[_Rt_].UD[0] >> SDL_SHIFT[shift]) |
|
|
(mem & SDL_MASK[shift]);
|
|
memWrite64(addr & ~7, &mem);
|
|
}
|
|
|
|
|
|
void SDR()
|
|
{
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
u32 shift = addr & 7;
|
|
u64 mem;
|
|
|
|
memRead64(addr & ~7, &mem);
|
|
mem = (cpuRegs.GPR.r[_Rt_].UD[0] << SDR_SHIFT[shift]) |
|
|
(mem & SDR_MASK[shift]);
|
|
memWrite64(addr & ~7, &mem );
|
|
}
|
|
|
|
void SQ()
|
|
{
|
|
// MIPS Note: LQ and SQ are special and "silently" align memory addresses, thus
|
|
// an address error due to unaligned access isn't possible like it is on other loads/stores.
|
|
|
|
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
|
|
memWrite128(addr & ~0xf, cpuRegs.GPR.r[_Rt_].UQ);
|
|
}
|
|
|
|
/*********************************************************
|
|
* Conditional Move *
|
|
* Format: OP rd, rs, rt *
|
|
*********************************************************/
|
|
|
|
void MOVZ() {
|
|
if (!_Rd_) return;
|
|
if (cpuRegs.GPR.r[_Rt_].UD[0] == 0) {
|
|
cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0];
|
|
}
|
|
}
|
|
void MOVN() {
|
|
if (!_Rd_) return;
|
|
if (cpuRegs.GPR.r[_Rt_].UD[0] != 0) {
|
|
cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0];
|
|
}
|
|
}
|
|
|
|
/*********************************************************
|
|
* Special purpose instructions *
|
|
* Format: OP *
|
|
*********************************************************/
|
|
|
|
|
|
// This function is the only one that uses Sifcmd.h in Pcsx2.
|
|
#include "Sifcmd.h"
|
|
|
|
void SYSCALL()
|
|
{
|
|
u8 call;
|
|
|
|
if (cpuRegs.GPR.n.v1.SL[0] < 0)
|
|
call = (u8)(-cpuRegs.GPR.n.v1.SL[0]);
|
|
else
|
|
call = cpuRegs.GPR.n.v1.UC[0];
|
|
|
|
BIOS_LOG("Bios call: %s (%x)", R5900::bios[call], call);
|
|
|
|
if (call == 0x7c)
|
|
{
|
|
if(cpuRegs.GPR.n.a0.UL[0] == 0x10)
|
|
{
|
|
eeConLog( ShiftJIS_ConvertString((char*)PSM(memRead32(cpuRegs.GPR.n.a1.UL[0]))) );
|
|
}
|
|
else
|
|
__Deci2Call( cpuRegs.GPR.n.a0.UL[0], (u32*)PSM(cpuRegs.GPR.n.a1.UL[0]) );
|
|
}
|
|
|
|
// The only thing this code is used for is the one log message, so don't execute it if we aren't logging bios messages.
|
|
if (SysTraceActive(EE.Bios) && (call == 0x77))
|
|
{
|
|
t_sif_dma_transfer *dmat;
|
|
//struct t_sif_cmd_header *hdr;
|
|
//struct t_sif_rpc_bind *bind;
|
|
//struct t_rpc_server_data *server;
|
|
int n_transfer;
|
|
u32 addr;
|
|
//int sid;
|
|
|
|
n_transfer = cpuRegs.GPR.n.a1.UL[0] - 1;
|
|
if (n_transfer >= 0)
|
|
{
|
|
addr = cpuRegs.GPR.n.a0.UL[0] + n_transfer * sizeof(t_sif_dma_transfer);
|
|
dmat = (t_sif_dma_transfer*)PSM(addr);
|
|
|
|
BIOS_LOG("bios_%s: n_transfer=%d, size=%x, attr=%x, dest=%x, src=%x",
|
|
R5900::bios[cpuRegs.GPR.n.v1.UC[0]], n_transfer,
|
|
dmat->size, dmat->attr,
|
|
dmat->dest, dmat->src);
|
|
}
|
|
}
|
|
|
|
cpuRegs.pc -= 4;
|
|
cpuException(0x20, cpuRegs.branch);
|
|
}
|
|
|
|
void BREAK(void) {
|
|
cpuRegs.pc -= 4;
|
|
cpuException(0x24, cpuRegs.branch);
|
|
}
|
|
|
|
void MFSA( void ) {
|
|
if (!_Rd_) return;
|
|
cpuRegs.GPR.r[_Rd_].SD[0] = (s64)cpuRegs.sa;
|
|
}
|
|
|
|
void MTSA( void ) {
|
|
cpuRegs.sa = (s32)cpuRegs.GPR.r[_Rs_].SD[0] & 0xf;
|
|
}
|
|
|
|
// SNY supports three basic modes, two which synchronize memory accesses (related
|
|
// to the cache) and one which synchronizes the instruction pipeline (effectively
|
|
// a stall in either case). Our emulation model does not track EE-side pipeline
|
|
// status or stalls, nor does it implement the CACHE. Thus SYNC need do nothing.
|
|
void SYNC( void )
|
|
{
|
|
}
|
|
|
|
// Used to prefetch data into the EE's cache, or schedule a dirty write-back.
|
|
// CACHE is not emulated at this time (nor is there any need to emulate it), so
|
|
// this function does nothing in the context of our emulator.
|
|
void PREF( void )
|
|
{
|
|
}
|
|
|
|
static void trap(u16 code=0)
|
|
{
|
|
// unimplemented?
|
|
// throw R5900Exception::Trap(code);
|
|
|
|
cpuRegs.pc -= 4;
|
|
Console.Warning("Trap exception at 0x%08x", cpuRegs.pc);
|
|
cpuException(0x34, cpuRegs.branch);
|
|
}
|
|
|
|
/*********************************************************
|
|
* Register trap *
|
|
* Format: OP rs, rt *
|
|
*********************************************************/
|
|
void TGE() { if (cpuRegs.GPR.r[_Rs_].SD[0] >= cpuRegs.GPR.r[_Rt_].SD[0]) trap(_TrapCode_); }
|
|
void TGEU() { if (cpuRegs.GPR.r[_Rs_].UD[0] >= cpuRegs.GPR.r[_Rt_].UD[0]) trap(_TrapCode_); }
|
|
void TLT() { if (cpuRegs.GPR.r[_Rs_].SD[0] < cpuRegs.GPR.r[_Rt_].SD[0]) trap(_TrapCode_); }
|
|
void TLTU() { if (cpuRegs.GPR.r[_Rs_].UD[0] < cpuRegs.GPR.r[_Rt_].UD[0]) trap(_TrapCode_); }
|
|
void TEQ() { if (cpuRegs.GPR.r[_Rs_].SD[0] == cpuRegs.GPR.r[_Rt_].SD[0]) trap(_TrapCode_); }
|
|
void TNE() { if (cpuRegs.GPR.r[_Rs_].SD[0] != cpuRegs.GPR.r[_Rt_].SD[0]) trap(_TrapCode_); }
|
|
|
|
/*********************************************************
|
|
* Trap with immediate operand *
|
|
* Format: OP rs, rt *
|
|
*********************************************************/
|
|
void TGEI() { if (cpuRegs.GPR.r[_Rs_].SD[0] >= _Imm_) trap(); }
|
|
void TLTI() { if (cpuRegs.GPR.r[_Rs_].SD[0] < _Imm_) trap(); }
|
|
void TEQI() { if (cpuRegs.GPR.r[_Rs_].SD[0] == _Imm_) trap(); }
|
|
void TNEI() { if (cpuRegs.GPR.r[_Rs_].SD[0] != _Imm_) trap(); }
|
|
void TGEIU() { if (cpuRegs.GPR.r[_Rs_].UD[0] >= (u64)_Imm_) trap(); }
|
|
void TLTIU() { if (cpuRegs.GPR.r[_Rs_].UD[0] < (u64)_Imm_) trap(); }
|
|
|
|
/*********************************************************
|
|
* Sa intructions *
|
|
* Format: OP rs, rt *
|
|
*********************************************************/
|
|
|
|
void MTSAB() {
|
|
cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF));
|
|
}
|
|
|
|
void MTSAH() {
|
|
cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1;
|
|
}
|
|
|
|
} } } // end namespace R5900::Interpreter::OpcodeImpl
|