Commit Graph

110 Commits

Author SHA1 Message Date
Ty 71100679a3 R5900: Implement ARM NEON intrinsics for the EE cache 2025-01-20 15:14:25 -05:00
TheTechnician27 23fd57f641 Copyright: Change year from 2002-2024 to 2002-2025 2025-01-20 05:07:26 +01:00
TheLastRar de9d08075e Misc: Don't use deprecated fmt/core.h header 2025-01-17 04:35:29 +01:00
Ty Lamontagne 1842fe6db8 EE Cache: Make the SIMD path x86 only to support ARM interpreters 2025-01-03 14:17:24 -05:00
Ty Lamontagne 5d39c884b5 R5900: Improve the EE cache performance with SIMD 2024-12-27 14:18:32 -05:00
GovanifY 132431b7c8 headers: relicense to GPL-3.0+
also update to 2024 while i'm at it
2024-07-30 17:17:13 -04:00
Ty Lamontagne dbfd506c8a Clang Format: cache.cpp and vtlb.cpp 2024-07-02 17:45:33 +01:00
Ty Lamontagne d47cdfba2d EE Cache: Invalid physical address caching and line locking
Hopefully the final fix required for the find my own way demo to work.
2024-07-02 17:45:33 +01:00
Ty Lamontagne a0b42f069f EE Cache: Fix PageMask reg usage when checking TLB entry cache mode 2024-07-02 17:45:33 +01:00
Stenzek 22d929d171 VTLB: Fix unmapping all pages with 16K host 2024-06-14 17:06:45 +10:00
Stenzek d48f527d6d Common: Tidy up signal handlers
Move MacOS into its own file.
Fix assertion failure crash dumping.
2024-05-31 13:39:36 +10:00
Benjamin Moir 5f7e97c27c [SAVEVERSION+] EE: Expose advanced option for extra memory 2024-05-09 13:45:06 +10:00
Stenzek 9752a037be HostSys: Simplify page fault handler installation
And include whether it was a write or a read access.
2024-05-07 12:41:03 +10:00
Stenzek 59d29b3648 Common: Rename General to HostSys
Actually fits what it's doing.
2023-12-27 13:55:35 +10:00
Stenzek d9abe10308 Misc: Remove explicit PCH include, switch to SPDX 2023-12-24 14:03:14 +10:00
Stenzek dc859ca0a6 Misc: Simplify assertion macros 2023-12-24 14:03:14 +10:00
Stenzek 606cbb3883 System: Simplify memory allocation 2023-10-10 18:01:30 +10:00
Stenzek 377746f155 x86: Move dispatchers to recompiler code space 2023-10-10 18:01:30 +10:00
Stenzek 2b4c7d12b6 Common: Merge MathUtils.h into BitUtils.h 2023-07-23 21:52:36 +10:00
Stenzek 7c9c8e197c Common: Replace MemsetFast routines with C memset
And associated cleanup.

On most compilers these days, it'll either inline the memset with vector
fills or rep stosq, or outline with a call to memset.

I trust the compiler is probably going to make a better decision here,
than manual SSE intrinsics.

Ends up a couple of percent faster in FMV decoding.
2023-06-22 19:11:57 +10:00
Stenzek 9d3de8631c Patch: Add "bytes" type
Allows patching an arbitrary range of bytes.
2023-06-03 23:09:52 +01:00
Stenzek 369b9a4808 Misc: Fix up a few recent clang warnings 2023-04-05 12:43:45 +01:00
refractionpcsx2 d080e7e7bd VTLB: Show rough EE PC when a TLB miss happens 2023-03-26 22:14:28 +01:00
Stenzek 957ec1d3d3 VTLB: Add option to pause on TLB miss
Rather than making it contingent on dev builds.
2023-01-26 11:11:36 +00:00
Stenzek d12fa690c0 R5900: Remove exceptions 2023-01-26 11:11:36 +00:00
Stenzek 4cf041f6cb Common: Move VirtualMemory related functionality to core
Also rewrites page fault handling to not use EventSource junk.
2023-01-26 11:11:36 +00:00
Stenzek 6e907ae618 vtlb: Remove upper/lower 32-bit unmapped split
This was only necessary on 32-bit because the sign bit was abused for
representing handlers. Since we're 64-bit only, we use bit 63, which
won't clash with the guest's 32-bit virtual address.
2023-01-26 09:41:13 +00:00
Stenzek 07789f5dad Core: Warning fixes for clang-cl 2022-12-25 09:27:44 +00:00
Connor McLaughlin 0e73bf1e6d SaveState: Only remap changed TLB slots on load 2022-11-19 04:59:10 +00:00
Connor McLaughlin 1ccddb92d4 EE Rec/IOP Rec: Rewrite large portions
- Add fastmem
 - Add delay slot swapping
 - Add COP2 sync elision
 - Add block analysis and use analysis
 - Add GPR register caching and renaming
2022-11-19 04:59:10 +00:00
Connor McLaughlin 00bcb4cf02 System: Revamp memory allocation
Guest memory is now mapped into a shared memory/file mapping, for use
with fastmem.

64-bit and 128-bit arguments are passed by register/value instead of by
reference/address.

LDL/LDR/SDL/SDR now use 64-bit GPRs instead of SSE.
2022-10-14 22:24:42 +01:00
TellowKrinkle 738c8cb630 Core: Remove trailing whitespace from all files 2022-09-16 00:52:28 -05:00
Connor McLaughlin c0e65d9a36 vtlb: Add RAM accessors which avoid hw access 2022-06-04 18:10:46 +01:00
Connor McLaughlin 893b3c629d Everything: Remove a **lot** of wx, and px nonsense
- common has no wx left except for Path.
 - pcsx2core only has it in a few places (memory cards and path related
   stuff).
2022-05-22 13:58:56 +01:00
Connor McLaughlin d535331b4b Misc: Remove __fastcall, __fc, __concall and friends
These have no meaning in x64 (apart from throwing compiler warnings),
and we don't do 32-bit anymore. Also saves needing to include
`Pcsx2Defs.h` in files which don't otherwise need it.
2022-05-12 14:58:03 +01:00
TellowKrinkle be6b8dce25 VTLB: Fix ppmap allocation in 64-bit 2022-01-04 13:01:49 +00:00
TellowKrinkle f7476dfb63 Core: Replace alignment macros with alignas 2021-11-14 13:52:20 -06:00
TellowKrinkle 2351431d71 Misc: Remove custom countof macros in favor of std::size 2021-11-14 13:52:20 -06:00
TellowKrinkle e9518f78c7 vtlb: Switch read64 and read128 handlers to return in sse regs 2021-09-21 22:57:41 +01:00
kojin 8fdaaa2eab common: reorganize 2021-09-04 18:28:07 -04:00
Tellow Krinkle dc57270fb8 EE/IOP/VU: x86-64 recompiler support 2020-08-24 16:20:09 -05:00
tellowkrinkle 850efdc690
Move VTLB manipulation to class (#3524)
Another small piece of #3451

Moves all VTLB pointer manipulation into dedicated classes for the purpose, which should allow the algorithm to be changed much more easily in the future (only have to change the class and recVTLB.cpp assembly since it obviously can't use the class)

Also some of the functions that manipulated the VTLB previously used POINTER_SIGN_BIT (which 1 << 63 on 64-bit) while others used a sign-extended 0x80000000. Now they all use the same one (POINTER_SIGN_BIT)

Note: recVTLB.cpp was updated to keep it compiling but the rest of the x86-64 compatibility changes were left out

Also, Cache.cpp seems to assume VTLB entries are both sides of the union at the same time, which is impossible. Does anyone know how this actually worked (and if this patch breaks it) or if it never worked properly in the first place?
2020-08-19 09:37:23 +01:00
tellowkrinkle 75aac90452
Allocate memory in an x86-64-compatible way (#3523)
Allocate memory in an x86-64-compatible way

Another part of #3451

Note: While this shouldn't change how anything works, it's been the #1 source of breakage of 32-bit builds in #3451 (it was the cause for the failure of win32 to allocate memory and the failure of linux-32 afterward) so we should definitely make sure it gets tested

see #3523 for more information
2020-08-19 09:20:48 +01:00
Gregory Hainaut 9648e25018 pcsx2: don't obfuscate the template type with macro 2016-09-18 16:13:29 +02:00
Gregory Hainaut 41d13dc2c6 vtlb: remove SetBaseAddr
Base address is given in the constructor
2016-01-10 14:31:49 +01:00
Gregory Hainaut 17e3c570ba pcsx2-ee: properly set the running variable
Fix exception propagation. Behavior is now equivalent to Windows.
2015-10-28 14:25:12 +01:00
Gregory Hainaut a8ad598153 pcsx2:tlb: improve goemon gamefix log 2014-12-12 22:14:08 +01:00
Gregory Hainaut 2cfbc6e5ef pcsx2:tlb: extend goemon gamefix
Add GoemonUnloadTlb function that invalidate TLB cache.

Currently the function is only used on the interpreter. It fixes TLB error after a reload of data.

Next step: porting to the recompiler
2014-12-12 22:14:08 +01:00
Gregory Hainaut a30bd86311 pcsx2: interpreter: add an exception for tlb miss
When a tlb miss is detected current instruction must be skipped. We need
to immediately switch to the handler

Typical instruction bug case:
 lw a0, 0x8(a0)

a0 mustn't be loaded if we have a miss

v2: create a dedicated exception for tlb miss

v3:
* rename exception to CancelInstruction
* add a basic state machine on the exec loop so we keep same behavior
  for eeloadReplaceOSDSYS and eeGameStarting

v4: remove assert
2014-12-02 21:38:29 +01:00
Ryan Houdek bddb2504b5 Get the VTLB working on x86_64.
VTLB does some nonsense with signed integers for the pointers.
We've got to make sure to set the signed bit in the correct bit on 64bit pointers so it works.
2014-08-22 15:31:40 -05:00