mirror of https://github.com/PCSX2/pcsx2.git
Clang Format: cache.cpp and vtlb.cpp
This commit is contained in:
Ty Lamontagne
refractionpcsx2
parent
d47cdfba2d
commit
dbfd506c8a
238
pcsx2/Cache.cpp
238
pcsx2/Cache.cpp
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@ -47,9 +47,9 @@ namespace
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return rawValue & ALL_FLAGS;
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}
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bool isValid() const { return rawValue & VALID_FLAG; }
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bool isDirty() const { return rawValue & DIRTY_FLAG; }
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bool lrf() const { return rawValue & LRF_FLAG; }
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bool isValid() const { return rawValue & VALID_FLAG; }
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bool isDirty() const { return rawValue & DIRTY_FLAG; }
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bool lrf() const { return rawValue & LRF_FLAG; }
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bool isLocked() const { return rawValue & LOCK_FLAG; }
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bool isDirtyAndValid() const
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@ -57,11 +57,11 @@ namespace
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return (rawValue & (DIRTY_FLAG | VALID_FLAG)) == (DIRTY_FLAG | VALID_FLAG);
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}
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void setValid() { rawValue |= VALID_FLAG; }
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void setDirty() { rawValue |= DIRTY_FLAG; }
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void setValid() { rawValue |= VALID_FLAG; }
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void setDirty() { rawValue |= DIRTY_FLAG; }
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void setLocked() { rawValue |= LOCK_FLAG; }
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void clearValid() { rawValue &= ~VALID_FLAG; }
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void clearDirty() { rawValue &= ~DIRTY_FLAG; }
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void clearValid() { rawValue &= ~VALID_FLAG; }
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void clearDirty() { rawValue &= ~DIRTY_FLAG; }
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void clearLocked() { rawValue &= ~LOCK_FLAG; }
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void toggleLRF() { rawValue ^= LRF_FLAG; }
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@ -151,12 +151,12 @@ namespace
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CacheLine lineAt(int idx, int way)
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{
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return { sets[idx].tags[way], sets[idx].data[way], idx };
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return {sets[idx].tags[way], sets[idx].data[way], idx};
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}
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};
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static Cache cache = {};
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}
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} // namespace
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void resetCache()
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{
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@ -165,8 +165,7 @@ void resetCache()
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static bool findInCache(const CacheSet& set, uptr ppf, int* way)
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{
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auto check = [&](int checkWay) -> bool
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{
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auto check = [&](int checkWay) -> bool {
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if (!set.tags[checkWay].matches(ppf))
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return false;
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@ -349,139 +348,138 @@ void doCacheHitOp(u32 addr, const char* name, Op op)
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op(cache.lineAt(index, way));
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}
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namespace R5900 {
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namespace Interpreter
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namespace R5900
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{
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namespace OpcodeImpl
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{
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extern int Dcache;
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void CACHE()
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{
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u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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// CACHE_LOG("cpuRegs.GPR.r[_Rs_].UL[0] = %x, IMM = %x RT = %x", cpuRegs.GPR.r[_Rs_].UL[0], _Imm_, _Rt_);
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switch (_Rt_)
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namespace Interpreter
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{
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case 0x1a: //DHIN (Data Cache Hit Invalidate)
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doCacheHitOp(addr, "DHIN", [](CacheLine line)
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namespace OpcodeImpl
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{
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extern int Dcache;
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void CACHE()
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{
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line.clear();
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});
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break;
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u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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// CACHE_LOG("cpuRegs.GPR.r[_Rs_].UL[0] = %x, IMM = %x RT = %x", cpuRegs.GPR.r[_Rs_].UL[0], _Imm_, _Rt_);
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case 0x18: //DHWBIN (Data Cache Hit WriteBack with Invalidate)
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doCacheHitOp(addr, "DHWBIN", [](CacheLine line)
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{
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line.writeBackIfNeeded();
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line.clear();
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});
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break;
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switch (_Rt_)
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{
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case 0x1a: //DHIN (Data Cache Hit Invalidate)
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doCacheHitOp(addr, "DHIN", [](CacheLine line) {
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line.clear();
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});
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break;
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case 0x1c: //DHWOIN (Data Cache Hit WriteBack Without Invalidate)
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doCacheHitOp(addr, "DHWOIN", [](CacheLine line)
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{
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line.writeBackIfNeeded();
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});
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break;
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case 0x18: //DHWBIN (Data Cache Hit WriteBack with Invalidate)
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doCacheHitOp(addr, "DHWBIN", [](CacheLine line) {
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line.writeBackIfNeeded();
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line.clear();
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});
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break;
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case 0x16: //DXIN (Data Cache Index Invalidate)
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{
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const int index = cache.setIdxFor(addr);
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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case 0x1c: //DHWOIN (Data Cache Hit WriteBack Without Invalidate)
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doCacheHitOp(addr, "DHWOIN", [](CacheLine line) {
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line.writeBackIfNeeded();
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});
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break;
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CACHE_LOG("CACHE DXIN addr %x, index %d, way %d, flag %x", addr, index, way, line.tag.flags());
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case 0x16: //DXIN (Data Cache Index Invalidate)
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{
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const int index = cache.setIdxFor(addr);
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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line.clear();
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break;
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}
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CACHE_LOG("CACHE DXIN addr %x, index %d, way %d, flag %x", addr, index, way, line.tag.flags());
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case 0x11: //DXLDT (Data Cache Load Data into TagLo)
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{
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const int index = cache.setIdxFor(addr);
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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line.clear();
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break;
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}
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cpuRegs.CP0.n.TagLo = *reinterpret_cast<u32*>(&line.data.bytes[addr & 0x3C]);
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case 0x11: //DXLDT (Data Cache Load Data into TagLo)
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{
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const int index = cache.setIdxFor(addr);
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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CACHE_LOG("CACHE DXLDT addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
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break;
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}
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cpuRegs.CP0.n.TagLo = *reinterpret_cast<u32*>(&line.data.bytes[addr & 0x3C]);
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case 0x10: //DXLTG (Data Cache Load Tag into TagLo)
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{
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const int index = (addr >> 6) & 0x3F;
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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CACHE_LOG("CACHE DXLDT addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
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break;
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}
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// DXLTG demands that SYNC.L is called before this command, which forces the cache to write back, so presumably games are checking the cache has updated the memory
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// For speed, we will do it here.
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line.writeBackIfNeeded();
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case 0x10: //DXLTG (Data Cache Load Tag into TagLo)
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{
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const int index = (addr >> 6) & 0x3F;
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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// Our tags don't contain PS2 paddrs (instead they contain x86 addrs)
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cpuRegs.CP0.n.TagLo = line.tag.flags();
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// DXLTG demands that SYNC.L is called before this command, which forces the cache to write back, so presumably games are checking the cache has updated the memory
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// For speed, we will do it here.
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line.writeBackIfNeeded();
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CACHE_LOG("CACHE DXLTG addr %x, index %d, way %d, DATA %x OP %x ", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
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CACHE_LOG("WARNING: DXLTG emulation supports flags only, things could break");
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break;
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}
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// Our tags don't contain PS2 paddrs (instead they contain x86 addrs)
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cpuRegs.CP0.n.TagLo = line.tag.flags();
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case 0x13: //DXSDT (Data Cache Store 32bits from TagLo)
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{
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const int index = (addr >> 6) & 0x3F;
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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CACHE_LOG("CACHE DXLTG addr %x, index %d, way %d, DATA %x OP %x ", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
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CACHE_LOG("WARNING: DXLTG emulation supports flags only, things could break");
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break;
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}
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*reinterpret_cast<u32*>(&line.data.bytes[addr & 0x3C]) = cpuRegs.CP0.n.TagLo;
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case 0x13: //DXSDT (Data Cache Store 32bits from TagLo)
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{
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const int index = (addr >> 6) & 0x3F;
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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CACHE_LOG("CACHE DXSDT addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
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break;
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}
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*reinterpret_cast<u32*>(&line.data.bytes[addr & 0x3C]) = cpuRegs.CP0.n.TagLo;
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case 0x12: //DXSTG (Data Cache Store Tag from TagLo)
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{
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const int index = (addr >> 6) & 0x3F;
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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CACHE_LOG("CACHE DXSDT addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
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break;
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}
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line.tag.setAddr(cpuRegs.CP0.n.TagLo);
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line.tag.rawValue &= ~CacheTag::ALL_FLAGS;
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line.tag.rawValue |= (cpuRegs.CP0.n.TagLo & CacheTag::ALL_FLAGS);
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case 0x12: //DXSTG (Data Cache Store Tag from TagLo)
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{
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const int index = (addr >> 6) & 0x3F;
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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CACHE_LOG("CACHE DXSTG addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
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break;
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}
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line.tag.setAddr(cpuRegs.CP0.n.TagLo);
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line.tag.rawValue &= ~CacheTag::ALL_FLAGS;
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line.tag.rawValue |= (cpuRegs.CP0.n.TagLo & CacheTag::ALL_FLAGS);
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case 0x14: //DXWBIN (Data Cache Index WriteBack Invalidate)
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{
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const int index = (addr >> 6) & 0x3F;
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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CACHE_LOG("CACHE DXSTG addr %x, index %d, way %d, DATA %x OP %x", addr, index, way, cpuRegs.CP0.n.TagLo, cpuRegs.code);
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break;
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}
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CACHE_LOG("CACHE DXWBIN addr %x, index %d, way %d, flags %x paddr %zx", addr, index, way, line.tag.flags(), line.addr());
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line.writeBackIfNeeded();
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line.clear();
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break;
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}
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case 0x14: //DXWBIN (Data Cache Index WriteBack Invalidate)
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{
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const int index = (addr >> 6) & 0x3F;
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const int way = addr & 0x1;
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CacheLine line = cache.lineAt(index, way);
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case 0x7: //IXIN (Instruction Cache Index Invalidate)
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{
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//Not Implemented as we do not have instruction cache
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break;
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}
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CACHE_LOG("CACHE DXWBIN addr %x, index %d, way %d, flags %x paddr %zx", addr, index, way, line.tag.flags(), line.addr());
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line.writeBackIfNeeded();
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line.clear();
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break;
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}
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case 0xC: //BFH (BTAC Flush)
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{
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//Not Implemented as we do not cache Branch Target Addresses.
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break;
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}
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case 0x7: //IXIN (Instruction Cache Index Invalidate)
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{
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//Not Implemented as we do not have instruction cache
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break;
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}
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default:
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DevCon.Warning("Cache mode %x not implemented", _Rt_);
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break;
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}
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}
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} // end namespace OpcodeImpl
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case 0xC: //BFH (BTAC Flush)
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{
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//Not Implemented as we do not cache Branch Target Addresses.
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break;
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}
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}}
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default:
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DevCon.Warning("Cache mode %x not implemented", _Rt_);
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break;
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}
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}
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} // end namespace OpcodeImpl
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} // namespace Interpreter
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} // namespace R5900
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@ -113,7 +113,7 @@ __inline int ConvertPageMask(u32 PageMask)
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{
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const u32 mask = std::popcount(PageMask >> 13);
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pxAssertMsg (!((mask & 1) || mask > 12), "Invalid page mask for this TLB entry. EE cache doesn't know what to do here.");
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pxAssertMsg(!((mask & 1) || mask > 12), "Invalid page mask for this TLB entry. EE cache doesn't know what to do here.");
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return (1 << (12 + mask)) - 1;
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}
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