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core: massively sed old emitter syntax to the new one 

It misses jump & FPU. Jump need to be handled manually.

Syntax isn't perfect yet because of various casts. But it will allow to have a
single emitter syntax and rely on type safety on the future.

Conflicts:
	pcsx2/x86/iR3000Atables.cpp
	pcsx2/x86/ix86-32/iR5900-32.cpp
This commit is contained in:
Gregory Hainaut 2015-11-26 18:44:40 +01:00
parent bd1d3724c1
commit fcdbae6806
25 changed files with 4105 additions and 4105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

86
pcsx2/x86/iCOP0.cpp
View File

@ -54,12 +54,12 @@ static void _setupBranchTest()
// But using 32-bit loads here is ok (and faster), because we mask off
// everything except the lower 10 bits away.
MOV32MtoR( EAX, (uptr)&psHu32(DMAC_PCR) );
MOV32ItoR( ECX, 0x3ff ); // ECX is our 10-bit mask var
NOT32R( EAX );
OR32MtoR( EAX, (uptr)&psHu32(DMAC_STAT) );
AND32RtoR( EAX, ECX );
CMP32RtoR( EAX, ECX );
xMOV(eax, ptr[(&psHu32(DMAC_PCR) )]);
xMOV(ecx, 0x3ff ); // ECX is our 10-bit mask var
xNOT(eax);
xOR(eax, ptr[(&psHu32(DMAC_STAT) )]);
xAND(eax, ecx);
xCMP(eax, ecx);
}
void recBC0F()
@ -109,10 +109,10 @@ void recDI()
//iFlushCall(0);
//MOV32MtoR( EAX, (uptr)&cpuRegs.cycle );
//MOV32RtoM( (uptr)&g_nextBranchCycle, EAX );
//xMOV(eax, ptr[&cpuRegs.cycle ]);
//xMOV(ptr[&g_nextBranchCycle], eax);
//CALLFunc( (uptr)Interp::DI );
//xCALL((void*)(uptr)Interp::DI );
xMOV(eax, ptr[&cpuRegs.CP0.n.Status]);
xTEST(eax, 0x20006); // EXL | ERL | EDI
@ -138,23 +138,23 @@ void recMFC0()
if( _Rd_ == 9 )
{
// This case needs to be handled even if the write-back is ignored (_Rt_ == 0 )
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
MOV32RtoR(EAX, ECX);
SUB32MtoR(EAX, (uptr)&s_iLastCOP0Cycle);
xMOV(ecx, ptr[&cpuRegs.cycle]);
xMOV(eax, ecx);
xSUB(eax, ptr[&s_iLastCOP0Cycle]);
u8* skipInc = JNZ8( 0 );
INC32R(EAX);
xINC(eax);
x86SetJ8( skipInc );
ADD32RtoM((uptr)&cpuRegs.CP0.n.Count, EAX);
MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
MOV32MtoR( EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ] );
xADD(ptr[&cpuRegs.CP0.n.Count], eax);
xMOV(ptr[&s_iLastCOP0Cycle], ecx);
xMOV(eax, ptr[&cpuRegs.CP0.r[ _Rd_ ] ]);
if( !_Rt_ ) return;
_deleteEEreg(_Rt_, 0);
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
xMOV(ptr[&cpuRegs.GPR.r[_Rt_].UL[0]], eax);
CDQ();
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
xCDQ();
xMOV(ptr[&cpuRegs.GPR.r[_Rt_].UL[1]], edx);
return;
}
@ -165,7 +165,7 @@ void recMFC0()
switch(_Imm_ & 0x3F)
{
case 0:
MOV32MtoR(EAX, (uptr)&cpuRegs.PERF.n.pccr);
xMOV(eax, ptr[&cpuRegs.PERF.n.pccr]);
break;
case 1:
@ -180,10 +180,10 @@ void recMFC0()
break;
}
_deleteEEreg(_Rt_, 0);
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0],EAX);
xMOV(ptr[&cpuRegs.GPR.r[_Rt_].UL[0]], eax);
CDQ();
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
xCDQ();
xMOV(ptr[&cpuRegs.GPR.r[_Rt_].UL[1]], edx);
return;
}
@ -193,10 +193,10 @@ void recMFC0()
}
_eeOnWriteReg(_Rt_, 1);
_deleteEEreg(_Rt_, 0);
MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.r[ _Rd_ ]);
CDQ();
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0], EAX);
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
xMOV(eax, ptr[&cpuRegs.CP0.r[ _Rd_ ]]);
xCDQ();
xMOV(ptr[&cpuRegs.GPR.r[_Rt_].UL[0]], eax);
xMOV(ptr[&cpuRegs.GPR.r[_Rt_].UL[1]], edx);
}
void recMTC0()
@ -212,9 +212,9 @@ void recMTC0()
break;
case 9:
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
MOV32ItoM((uptr)&cpuRegs.CP0.r[9], g_cpuConstRegs[_Rt_].UL[0]);
xMOV(ecx, ptr[&cpuRegs.cycle]);
xMOV(ptr[&s_iLastCOP0Cycle], ecx);
xMOV(ptr32[&cpuRegs.CP0.r[9]], g_cpuConstRegs[_Rt_].UL[0]);
break;
case 25:
@ -228,15 +228,15 @@ void recMTC0()
break;
case 1:
MOV32MtoR(EAX, (uptr)&cpuRegs.cycle);
MOV32ItoM((uptr)&cpuRegs.PERF.n.pcr0, g_cpuConstRegs[_Rt_].UL[0]);
MOV32RtoM((uptr)&s_iLastPERFCycle[0], EAX);
xMOV(eax, ptr[&cpuRegs.cycle]);
xMOV(ptr32[&cpuRegs.PERF.n.pcr0], g_cpuConstRegs[_Rt_].UL[0]);
xMOV(ptr[&s_iLastPERFCycle[0]], eax);
break;
case 3:
MOV32MtoR(EAX, (uptr)&cpuRegs.cycle);
MOV32ItoM((uptr)&cpuRegs.PERF.n.pcr1, g_cpuConstRegs[_Rt_].UL[0]);
MOV32RtoM((uptr)&s_iLastPERFCycle[1], EAX);
xMOV(eax, ptr[&cpuRegs.cycle]);
xMOV(ptr32[&cpuRegs.PERF.n.pcr1], g_cpuConstRegs[_Rt_].UL[0]);
xMOV(ptr[&s_iLastPERFCycle[1]], eax);
break;
}
break;
@ -246,7 +246,7 @@ void recMTC0()
break;
default:
MOV32ItoM((uptr)&cpuRegs.CP0.r[_Rd_], g_cpuConstRegs[_Rt_].UL[0]);
xMOV(ptr32[&cpuRegs.CP0.r[_Rd_]], g_cpuConstRegs[_Rt_].UL[0]);
break;
}
}
@ -261,9 +261,9 @@ void recMTC0()
break;
case 9:
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
xMOV(ecx, ptr[&cpuRegs.cycle]);
_eeMoveGPRtoM((uptr)&cpuRegs.CP0.r[9], _Rt_);
MOV32RtoM((uptr)&s_iLastCOP0Cycle, ECX);
xMOV(ptr[&s_iLastCOP0Cycle], ecx);
break;
case 25:
@ -277,15 +277,15 @@ void recMTC0()
break;
case 1:
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
xMOV(ecx, ptr[&cpuRegs.cycle]);
_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr0, _Rt_);
MOV32RtoM((uptr)&s_iLastPERFCycle[0], ECX);
xMOV(ptr[&s_iLastPERFCycle[0]], ecx);
break;
case 3:
MOV32MtoR(ECX, (uptr)&cpuRegs.cycle);
xMOV(ecx, ptr[&cpuRegs.cycle]);
_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pcr1, _Rt_);
MOV32RtoM((uptr)&s_iLastPERFCycle[1], ECX);
xMOV(ptr[&s_iLastPERFCycle[1]], ecx);
break;
}
break;

148
pcsx2/x86/iCore.cpp
View File

@ -178,7 +178,7 @@ int _allocVFtoXMMreg(VURegs *VU, int xmmreg, int vfreg, int mode) {
xmmregs[i].needed = 1;
if( !(xmmregs[i].mode & MODE_READ) && (mode&MODE_READ) ) {
SSE_MOVAPS_M128_to_XMM(i, VU_VFx_ADDR(vfreg));
xMOVAPS(xRegisterSSE(i), ptr[(void*)(VU_VFx_ADDR(vfreg))]);
xmmregs[i].mode |= MODE_READ;
}
@ -202,8 +202,8 @@ int _allocVFtoXMMreg(VURegs *VU, int xmmreg, int vfreg, int mode) {
xmmregs[xmmreg].VU = XMM_CONV_VU(VU);
xmmregs[xmmreg].counter = g_xmmAllocCounter++;
if (mode & MODE_READ) {
if( readfromreg >= 0 ) SSE_MOVAPS_XMM_to_XMM(xmmreg, readfromreg);
else SSE_MOVAPS_M128_to_XMM(xmmreg, VU_VFx_ADDR(xmmregs[xmmreg].reg));
if( readfromreg >= 0 ) xMOVAPS(xRegisterSSE(xmmreg), xRegisterSSE(readfromreg));
else xMOVAPS(xRegisterSSE(xmmreg), ptr[(void*)(VU_VFx_ADDR(xmmregs[xmmreg].reg))]);
}
return xmmreg;
@ -259,7 +259,7 @@ int _allocACCtoXMMreg(VURegs *VU, int xmmreg, int mode) {
}
if( !(xmmregs[i].mode & MODE_READ) && (mode&MODE_READ)) {
SSE_MOVAPS_M128_to_XMM(i, VU_ACCx_ADDR);
xMOVAPS(xRegisterSSE(i), ptr[(void*)(VU_ACCx_ADDR)]);
xmmregs[i].mode |= MODE_READ;
}
@ -287,9 +287,9 @@ int _allocACCtoXMMreg(VURegs *VU, int xmmreg, int mode) {
if (mode & MODE_READ)
{
if( readfromreg >= 0 )
SSE_MOVAPS_XMM_to_XMM(xmmreg, readfromreg);
xMOVAPS(xRegisterSSE(xmmreg), xRegisterSSE(readfromreg));
else
SSE_MOVAPS_M128_to_XMM(xmmreg, VU_ACCx_ADDR);
xMOVAPS(xRegisterSSE(xmmreg), ptr[(void*)(VU_ACCx_ADDR)]);
}
return xmmreg;
@ -304,7 +304,7 @@ int _allocFPtoXMMreg(int xmmreg, int fpreg, int mode) {
if (xmmregs[i].reg != fpreg) continue;
if( !(xmmregs[i].mode & MODE_READ) && (mode & MODE_READ)) {
SSE_MOVSS_M32_to_XMM(i, (uptr)&fpuRegs.fpr[fpreg].f);
xMOVSSZX(xRegisterSSE(i), ptr[&fpuRegs.fpr[fpreg].f]);
xmmregs[i].mode |= MODE_READ;
}
@ -327,7 +327,7 @@ int _allocFPtoXMMreg(int xmmreg, int fpreg, int mode) {
xmmregs[xmmreg].counter = g_xmmAllocCounter++;
if (mode & MODE_READ)
SSE_MOVSS_M32_to_XMM(xmmreg, (uptr)&fpuRegs.fpr[fpreg].f);
xMOVSSZX(xRegisterSSE(xmmreg), ptr[&fpuRegs.fpr[fpreg].f]);
return xmmreg;
}
@ -350,13 +350,13 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
{
if (gprreg == 0 )
{
SSEX_PXOR_XMM_to_XMM(i, i);
xPXOR(xRegisterSSE(i), xRegisterSSE(i));
}
else
{
//pxAssert( !(g_cpuHasConstReg & (1<<gprreg)) || (g_cpuFlushedConstReg & (1<<gprreg)) );
_flushConstReg(gprreg);
SSEX_MOVDQA_M128_to_XMM(i, (uptr)&cpuRegs.GPR.r[gprreg].UL[0]);
xMOVDQA(xRegisterSSE(i), ptr[&cpuRegs.GPR.r[gprreg].UL[0]]);
}
xmmregs[i].mode |= MODE_READ;
}
@ -396,7 +396,7 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
{
if (gprreg == 0 )
{
SSEX_PXOR_XMM_to_XMM(xmmreg, xmmreg);
xPXOR(xRegisterSSE(xmmreg), xRegisterSSE(xmmreg));
}
else
{
@ -411,9 +411,9 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
{
// transfer
SetMMXstate();
SSE2_MOVQ2DQ_MM_to_XMM(xmmreg, mmxreg);
SSE2_PUNPCKLQDQ_XMM_to_XMM(xmmreg, xmmreg);
SSE2_PUNPCKHQDQ_M128_to_XMM(xmmreg, (uptr)&cpuRegs.GPR.r[gprreg].UL[0]);
xMOVQ(xRegisterSSE(xmmreg), xRegisterMMX(mmxreg));
xPUNPCK.LQDQ(xRegisterSSE(xmmreg), xRegisterSSE(xmmreg));
xPUNPCK.HQDQ(xRegisterSSE(xmmreg), ptr[&cpuRegs.GPR.r[gprreg].UL[0]]);
if (mmxregs[mmxreg].mode & MODE_WRITE )
{
@ -421,7 +421,7 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
if (!(mode & MODE_WRITE))
{
SetMMXstate();
MOVQRtoM((uptr)&cpuRegs.GPR.r[gprreg].UL[0], mmxreg);
xMOVQ(ptr[&cpuRegs.GPR.r[gprreg].UL[0]], xRegisterMMX(mmxreg));
}
//xmmregs[xmmreg].mode |= MODE_WRITE;
}
@ -430,7 +430,7 @@ int _allocGPRtoXMMreg(int xmmreg, int gprreg, int mode)
mmxregs[mmxreg].inuse = 0;
}
else
SSEX_MOVDQA_M128_to_XMM(xmmreg, (uptr)&cpuRegs.GPR.r[gprreg].UL[0]);
xMOVDQA(xRegisterSSE(xmmreg), ptr[&cpuRegs.GPR.r[gprreg].UL[0]]);
}
}
else
@ -448,7 +448,7 @@ int _allocFPACCtoXMMreg(int xmmreg, int mode)
if (xmmregs[i].type != XMMTYPE_FPACC) continue;
if( !(xmmregs[i].mode & MODE_READ) && (mode&MODE_READ)) {
SSE_MOVSS_M32_to_XMM(i, (uptr)&fpuRegs.ACC.f);
xMOVSSZX(xRegisterSSE(i), ptr[&fpuRegs.ACC.f]);
xmmregs[i].mode |= MODE_READ;
}
@ -471,7 +471,7 @@ int _allocFPACCtoXMMreg(int xmmreg, int mode)
xmmregs[xmmreg].counter = g_xmmAllocCounter++;
if (mode & MODE_READ) {
SSE_MOVSS_M32_to_XMM(xmmreg, (uptr)&fpuRegs.ACC.f);
xMOVSSZX(xRegisterSSE(xmmreg), ptr[&fpuRegs.ACC.f]);
}
return xmmreg;
@ -598,26 +598,26 @@ void _deleteVFtoXMMreg(int reg, int vu, int flush)
if (t0reg < iREGCNT_XMM )
{
SSE_MOVHLPS_XMM_to_XMM(t0reg, i);
SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[i].reg), i);
SSE_MOVSS_XMM_to_M32(VU_VFx_ADDR(xmmregs[i].reg)+8, t0reg);
xMOVHL.PS(xRegisterSSE(t0reg), xRegisterSSE(i));
xMOVL.PS(ptr[(void*)(VU_VFx_ADDR(xmmregs[i].reg))], xRegisterSSE(i));
xMOVSS(ptr[(void*)(VU_VFx_ADDR(xmmregs[i].reg)+8)], xRegisterSSE(t0reg));
}
else
{
// no free reg
SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[i].reg), i);
SSE_SHUFPS_XMM_to_XMM(i, i, 0xc6);
SSE_MOVSS_XMM_to_M32(VU_VFx_ADDR(xmmregs[i].reg)+8, i);
SSE_SHUFPS_XMM_to_XMM(i, i, 0xc6);
xMOVL.PS(ptr[(void*)(VU_VFx_ADDR(xmmregs[i].reg))], xRegisterSSE(i));
xSHUF.PS(xRegisterSSE(i), xRegisterSSE(i), 0xc6);
xMOVSS(ptr[(void*)(VU_VFx_ADDR(xmmregs[i].reg)+8)], xRegisterSSE(i));
xSHUF.PS(xRegisterSSE(i), xRegisterSSE(i), 0xc6);
}
}
else
{
// xy
SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[i].reg), i);
xMOVL.PS(ptr[(void*)(VU_VFx_ADDR(xmmregs[i].reg))], xRegisterSSE(i));
}
}
else SSE_MOVAPS_XMM_to_M128(VU_VFx_ADDR(xmmregs[i].reg), i);
else xMOVAPS(ptr[(void*)(VU_VFx_ADDR(xmmregs[i].reg))], xRegisterSSE(i));
// get rid of MODE_WRITE since don't want to flush again
xmmregs[i].mode &= ~MODE_WRITE;
@ -661,25 +661,25 @@ void _deleteACCtoXMMreg(int vu, int flush)
}
if( t0reg < iREGCNT_XMM ) {
SSE_MOVHLPS_XMM_to_XMM(t0reg, i);
SSE_MOVLPS_XMM_to_M64(VU_ACCx_ADDR, i);
SSE_MOVSS_XMM_to_M32(VU_ACCx_ADDR+8, t0reg);
xMOVHL.PS(xRegisterSSE(t0reg), xRegisterSSE(i));
xMOVL.PS(ptr[(void*)(VU_ACCx_ADDR)], xRegisterSSE(i));
xMOVSS(ptr[(void*)(VU_ACCx_ADDR+8)], xRegisterSSE(t0reg));
}
else {
// no free reg
SSE_MOVLPS_XMM_to_M64(VU_ACCx_ADDR, i);
SSE_SHUFPS_XMM_to_XMM(i, i, 0xc6);
//SSE_MOVHLPS_XMM_to_XMM(i, i);
SSE_MOVSS_XMM_to_M32(VU_ACCx_ADDR+8, i);
SSE_SHUFPS_XMM_to_XMM(i, i, 0xc6);
xMOVL.PS(ptr[(void*)(VU_ACCx_ADDR)], xRegisterSSE(i));
xSHUF.PS(xRegisterSSE(i), xRegisterSSE(i), 0xc6);
//xMOVHL.PS(xRegisterSSE(i), xRegisterSSE(i));
xMOVSS(ptr[(void*)(VU_ACCx_ADDR+8)], xRegisterSSE(i));
xSHUF.PS(xRegisterSSE(i), xRegisterSSE(i), 0xc6);
}
}
else {
// xy
SSE_MOVLPS_XMM_to_M64(VU_ACCx_ADDR, i);
xMOVL.PS(ptr[(void*)(VU_ACCx_ADDR)], xRegisterSSE(i));
}
}
else SSE_MOVAPS_XMM_to_M128(VU_ACCx_ADDR, i);
else xMOVAPS(ptr[(void*)(VU_ACCx_ADDR)], xRegisterSSE(i));
// get rid of MODE_WRITE since don't want to flush again
xmmregs[i].mode &= ~MODE_WRITE;
@ -714,7 +714,7 @@ void _deleteGPRtoXMMreg(int reg, int flush)
pxAssert( reg != 0 );
//pxAssert( g_xmmtypes[i] == XMMT_INT );
SSEX_MOVDQA_XMM_to_M128((uptr)&cpuRegs.GPR.r[reg].UL[0], i);
xMOVDQA(ptr[&cpuRegs.GPR.r[reg].UL[0]], xRegisterSSE(i));
// get rid of MODE_WRITE since don't want to flush again
xmmregs[i].mode &= ~MODE_WRITE;
@ -743,7 +743,7 @@ void _deleteFPtoXMMreg(int reg, int flush)
case 1:
if (xmmregs[i].mode & MODE_WRITE) {
SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.fpr[reg].UL, i);
xMOVSS(ptr[&fpuRegs.fpr[reg].UL], xRegisterSSE(i));
// get rid of MODE_WRITE since don't want to flush again
xmmregs[i].mode &= ~MODE_WRITE;
xmmregs[i].mode |= MODE_READ;
@ -781,28 +781,28 @@ void _freeXMMreg(u32 xmmreg)
if( t0reg < iREGCNT_XMM )
{
SSE_MOVHLPS_XMM_to_XMM(t0reg, xmmreg);
SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[xmmreg].reg), xmmreg);
SSE_MOVSS_XMM_to_M32(VU_VFx_ADDR(xmmregs[xmmreg].reg)+8, t0reg);
xMOVHL.PS(xRegisterSSE(t0reg), xRegisterSSE(xmmreg));
xMOVL.PS(ptr[(void*)(VU_VFx_ADDR(xmmregs[xmmreg].reg))], xRegisterSSE(xmmreg));
xMOVSS(ptr[(void*)(VU_VFx_ADDR(xmmregs[xmmreg].reg)+8)], xRegisterSSE(t0reg));
}
else
{
// no free reg
SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[xmmreg].reg), xmmreg);
SSE_SHUFPS_XMM_to_XMM(xmmreg, xmmreg, 0xc6);
//SSE_MOVHLPS_XMM_to_XMM(xmmreg, xmmreg);
SSE_MOVSS_XMM_to_M32(VU_VFx_ADDR(xmmregs[xmmreg].reg)+8, xmmreg);
SSE_SHUFPS_XMM_to_XMM(xmmreg, xmmreg, 0xc6);
xMOVL.PS(ptr[(void*)(VU_VFx_ADDR(xmmregs[xmmreg].reg))], xRegisterSSE(xmmreg));
xSHUF.PS(xRegisterSSE(xmmreg), xRegisterSSE(xmmreg), 0xc6);
//xMOVHL.PS(xRegisterSSE(xmmreg), xRegisterSSE(xmmreg));
xMOVSS(ptr[(void*)(VU_VFx_ADDR(xmmregs[xmmreg].reg)+8)], xRegisterSSE(xmmreg));
xSHUF.PS(xRegisterSSE(xmmreg), xRegisterSSE(xmmreg), 0xc6);
}
}
else
{
SSE_MOVLPS_XMM_to_M64(VU_VFx_ADDR(xmmregs[xmmreg].reg), xmmreg);
xMOVL.PS(ptr[(void*)(VU_VFx_ADDR(xmmregs[xmmreg].reg))], xRegisterSSE(xmmreg));
}
}
else
{
SSE_MOVAPS_XMM_to_M128(VU_VFx_ADDR(xmmregs[xmmreg].reg), xmmreg);
xMOVAPS(ptr[(void*)(VU_VFx_ADDR(xmmregs[xmmreg].reg))], xRegisterSSE(xmmreg));
}
}
break;
@ -823,28 +823,28 @@ void _freeXMMreg(u32 xmmreg)
if( t0reg < iREGCNT_XMM )
{
SSE_MOVHLPS_XMM_to_XMM(t0reg, xmmreg);
SSE_MOVLPS_XMM_to_M64(VU_ACCx_ADDR, xmmreg);
SSE_MOVSS_XMM_to_M32(VU_ACCx_ADDR+8, t0reg);
xMOVHL.PS(xRegisterSSE(t0reg), xRegisterSSE(xmmreg));
xMOVL.PS(ptr[(void*)(VU_ACCx_ADDR)], xRegisterSSE(xmmreg));
xMOVSS(ptr[(void*)(VU_ACCx_ADDR+8)], xRegisterSSE(t0reg));
}
else
{
// no free reg
SSE_MOVLPS_XMM_to_M64(VU_ACCx_ADDR, xmmreg);
SSE_SHUFPS_XMM_to_XMM(xmmreg, xmmreg, 0xc6);
//SSE_MOVHLPS_XMM_to_XMM(xmmreg, xmmreg);
SSE_MOVSS_XMM_to_M32(VU_ACCx_ADDR+8, xmmreg);
SSE_SHUFPS_XMM_to_XMM(xmmreg, xmmreg, 0xc6);
xMOVL.PS(ptr[(void*)(VU_ACCx_ADDR)], xRegisterSSE(xmmreg));
xSHUF.PS(xRegisterSSE(xmmreg), xRegisterSSE(xmmreg), 0xc6);
//xMOVHL.PS(xRegisterSSE(xmmreg), xRegisterSSE(xmmreg));
xMOVSS(ptr[(void*)(VU_ACCx_ADDR+8)], xRegisterSSE(xmmreg));
xSHUF.PS(xRegisterSSE(xmmreg), xRegisterSSE(xmmreg), 0xc6);
}
}
else
{
SSE_MOVLPS_XMM_to_M64(VU_ACCx_ADDR, xmmreg);
xMOVL.PS(ptr[(void*)(VU_ACCx_ADDR)], xRegisterSSE(xmmreg));
}
}
else
{
SSE_MOVAPS_XMM_to_M128(VU_ACCx_ADDR, xmmreg);
xMOVAPS(ptr[(void*)(VU_ACCx_ADDR)], xRegisterSSE(xmmreg));
}
}
break;
@ -852,15 +852,15 @@ void _freeXMMreg(u32 xmmreg)
case XMMTYPE_GPRREG:
pxAssert( xmmregs[xmmreg].reg != 0 );
//pxAssert( g_xmmtypes[xmmreg] == XMMT_INT );
SSEX_MOVDQA_XMM_to_M128((uptr)&cpuRegs.GPR.r[xmmregs[xmmreg].reg].UL[0], xmmreg);
xMOVDQA(ptr[&cpuRegs.GPR.r[xmmregs[xmmreg].reg].UL[0]], xRegisterSSE(xmmreg));
break;
case XMMTYPE_FPREG:
SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.fpr[xmmregs[xmmreg].reg], xmmreg);
xMOVSS(ptr[&fpuRegs.fpr[xmmregs[xmmreg].reg]], xRegisterSSE(xmmreg));
break;
case XMMTYPE_FPACC:
SSE_MOVSS_XMM_to_M32((uptr)&fpuRegs.ACC.f, xmmreg);
xMOVSS(ptr[&fpuRegs.ACC.f], xRegisterSSE(xmmreg));
break;
default:
@ -929,7 +929,7 @@ void _moveXMMreg(int xmmreg)
// move
xmmregs[i] = xmmregs[xmmreg];
xmmregs[xmmreg].inuse = 0;
SSEX_MOVDQA_XMM_to_XMM(i, xmmreg);
xMOVDQA(xRegisterSSE(i), xRegisterSSE(xmmreg));
}
void _flushXMMregs()
@ -968,11 +968,11 @@ int _signExtendXMMtoM(u32 to, x86SSERegType from, int candestroy)
int t0reg;
g_xmmtypes[from] = XMMT_INT;
if( candestroy ) {
if( g_xmmtypes[from] == XMMT_FPS ) SSE_MOVSS_XMM_to_M32(to, from);
else SSE2_MOVD_XMM_to_M32(to, from);
if( g_xmmtypes[from] == XMMT_FPS ) xMOVSS(ptr[(void*)(to)], xRegisterSSE(from));
else xMOVD(ptr[(void*)(to)], xRegisterSSE(from));
SSE2_PSRAD_I8_to_XMM(from, 31);
SSE2_MOVD_XMM_to_M32(to+4, from);
xPSRA.D(xRegisterSSE(from), 31);
xMOVD(ptr[(void*)(to+4)], xRegisterSSE(from));
return 1;
}
else {
@ -983,19 +983,19 @@ int _signExtendXMMtoM(u32 to, x86SSERegType from, int candestroy)
if( _hasFreeXMMreg() ) {
xmmregs[from].needed = 1;
t0reg = _allocTempXMMreg(XMMT_INT, -1);
SSEX_MOVDQA_XMM_to_XMM(t0reg, from);
SSE2_PSRAD_I8_to_XMM(from, 31);
SSE2_MOVD_XMM_to_M32(to, t0reg);
SSE2_MOVD_XMM_to_M32(to+4, from);
xMOVDQA(xRegisterSSE(t0reg), xRegisterSSE(from));
xPSRA.D(xRegisterSSE(from), 31);
xMOVD(ptr[(void*)(to)], xRegisterSSE(t0reg));
xMOVD(ptr[(void*)(to+4)], xRegisterSSE(from));
// swap xmm regs.. don't ask
xmmregs[t0reg] = xmmregs[from];
xmmregs[from].inuse = 0;
}
else {
SSE2_MOVD_XMM_to_M32(to+4, from);
SSE2_MOVD_XMM_to_M32(to, from);
SAR32ItoM(to+4, 31);
xMOVD(ptr[(void*)(to+4)], xRegisterSSE(from));
xMOVD(ptr[(void*)(to)], xRegisterSSE(from));
xSAR(ptr32[(u32*)(to+4)], 31);
}
return 0;

662
pcsx2/x86/iFPU.cpp
View File

File diff suppressed because it is too large Load Diff

320
pcsx2/x86/iFPUd.cpp
View File

@ -93,7 +93,7 @@ namespace DOUBLE {
void f(); \
void rec##f() { \
iFlushCall(FLUSH_INTERPRETER); \
CALLFunc((uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \
xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \
branch = 2; \
}
@ -101,7 +101,7 @@ namespace DOUBLE {
void f(); \
void rec##f() { \
iFlushCall(FLUSH_INTERPRETER); \
CALLFunc((uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \
xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \
}
//------------------------------------------------------------------
@ -161,21 +161,21 @@ static const __aligned(32) FPUd_Globals s_const =
void ToDouble(int reg)
{
SSE_UCOMISS_M32_to_XMM(reg, (uptr)s_const.pos_inf); // Sets ZF if reg is equal or incomparable to pos_inf
xUCOMI.SS(xRegisterSSE(reg), ptr[s_const.pos_inf]); // Sets ZF if reg is equal or incomparable to pos_inf
u8 *to_complex = JE8(0); // Complex conversion if positive infinity or NaN
SSE_UCOMISS_M32_to_XMM(reg, (uptr)s_const.neg_inf);
xUCOMI.SS(xRegisterSSE(reg), ptr[s_const.neg_inf]);
u8 *to_complex2 = JE8(0); // Complex conversion if negative infinity
SSE2_CVTSS2SD_XMM_to_XMM(reg, reg); // Simply convert
xCVTSS2SD(xRegisterSSE(reg), xRegisterSSE(reg)); // Simply convert
u8 *end = JMP8(0);
x86SetJ8(to_complex);
x86SetJ8(to_complex2);
// Special conversion for when IEEE sees the value in reg as an INF/NaN
SSE2_PSUBD_M128_to_XMM(reg, (uptr)s_const.one_exp); // Lower exponent by one
SSE2_CVTSS2SD_XMM_to_XMM(reg, reg);
SSE2_PADDQ_M128_to_XMM(reg, (uptr)s_const.dbl_one_exp); // Raise exponent by one
xPSUB.D(xRegisterSSE(reg), ptr[s_const.one_exp]); // Lower exponent by one
xCVTSS2SD(xRegisterSSE(reg), xRegisterSSE(reg));
xPADD.Q(xRegisterSSE(reg), ptr[s_const.dbl_one_exp]); // Raise exponent by one
x86SetJ8(end);
}
@ -202,67 +202,67 @@ void ToDouble(int reg)
void ToPS2FPU_Full(int reg, bool flags, int absreg, bool acc, bool addsub)
{
if (flags)
AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO | FPUflagU));
xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagO | FPUflagU));
if (flags && acc)
AND32ItoM((uptr)&fpuRegs.ACCflag, ~1);
xAND(ptr32[&fpuRegs.ACCflag], ~1);
SSE_MOVAPS_XMM_to_XMM(absreg, reg);
SSE2_ANDPD_M128_to_XMM(absreg, (uptr)&s_const.dbl_s_pos);
xMOVAPS(xRegisterSSE(absreg), xRegisterSSE(reg));
xAND.PD(xRegisterSSE(absreg), ptr[&s_const.dbl_s_pos]);
SSE2_UCOMISD_M64_to_XMM(absreg, (uptr)&s_const.dbl_cvt_overflow);
xUCOMI.SD(xRegisterSSE(absreg), ptr[&s_const.dbl_cvt_overflow]);
u8 *to_complex = JAE8(0);
SSE2_UCOMISD_M64_to_XMM(absreg, (uptr)&s_const.dbl_underflow);
xUCOMI.SD(xRegisterSSE(absreg), ptr[&s_const.dbl_underflow]);
u8 *to_underflow = JB8(0);
SSE2_CVTSD2SS_XMM_to_XMM(reg, reg); //simply convert
xCVTSD2SS(xRegisterSSE(reg), xRegisterSSE(reg)); //simply convert
u8 *end = JMP8(0);
x86SetJ8(to_complex);
SSE2_UCOMISD_M64_to_XMM(absreg, (uptr)&s_const.dbl_ps2_overflow);
xUCOMI.SD(xRegisterSSE(absreg), ptr[&s_const.dbl_ps2_overflow]);
u8 *to_overflow = JAE8(0);
SSE2_PSUBQ_M128_to_XMM(reg, (uptr)&s_const.dbl_one_exp); //lower exponent
SSE2_CVTSD2SS_XMM_to_XMM(reg, reg); //convert
SSE2_PADDD_M128_to_XMM(reg, (uptr)s_const.one_exp); //raise exponent
xPSUB.Q(xRegisterSSE(reg), ptr[&s_const.dbl_one_exp]); //lower exponent
xCVTSD2SS(xRegisterSSE(reg), xRegisterSSE(reg)); //convert
xPADD.D(xRegisterSSE(reg), ptr[s_const.one_exp]); //raise exponent
u8 *end2 = JMP8(0);
x86SetJ8(to_overflow);
SSE2_CVTSD2SS_XMM_to_XMM(reg, reg);
SSE_ORPS_M128_to_XMM(reg, (uptr)&s_const.pos); //clamp
xCVTSD2SS(xRegisterSSE(reg), xRegisterSSE(reg));
xOR.PS(xRegisterSSE(reg), ptr[&s_const.pos]); //clamp
if (flags && FPU_FLAGS_OVERFLOW)
OR32ItoM((uptr)&fpuRegs.fprc[31], (FPUflagO | FPUflagSO));
xOR(ptr32[&fpuRegs.fprc[31]], (FPUflagO | FPUflagSO));
if (flags && FPU_FLAGS_OVERFLOW && acc)
OR32ItoM((uptr)&fpuRegs.ACCflag, 1);
xOR(ptr32[&fpuRegs.ACCflag], 1);
u8 *end3 = JMP8(0);
x86SetJ8(to_underflow);
u8 *end4;
if (flags && FPU_FLAGS_UNDERFLOW) //set underflow flags if not zero
{
SSE2_XORPD_XMM_to_XMM(absreg, absreg);
SSE2_UCOMISD_XMM_to_XMM(reg, absreg);
xXOR.PD(xRegisterSSE(absreg), xRegisterSSE(absreg));
xUCOMI.SD(xRegisterSSE(reg), xRegisterSSE(absreg));
u8 *is_zero = JE8(0);
OR32ItoM((uptr)&fpuRegs.fprc[31], (FPUflagU | FPUflagSU));
xOR(ptr32[&fpuRegs.fprc[31]], (FPUflagU | FPUflagSU));
if (addsub)
{
//On ADD/SUB, the PS2 simply leaves the mantissa bits as they are (after normalization)
//IEEE either clears them (FtZ) or returns the denormalized result.
//not thoroughly tested : other operations such as MUL and DIV seem to clear all mantissa bits?
SSE_MOVAPS_XMM_to_XMM(absreg, reg);
SSE2_PSLLQ_I8_to_XMM(reg, 12); //mantissa bits
SSE2_PSRLQ_I8_to_XMM(reg, 41);
SSE2_PSRLQ_I8_to_XMM(absreg, 63); //sign bit
SSE2_PSLLQ_I8_to_XMM(absreg, 31);
SSE2_POR_XMM_to_XMM(reg, absreg);
xMOVAPS(xRegisterSSE(absreg), xRegisterSSE(reg));
xPSLL.Q(xRegisterSSE(reg), 12); //mantissa bits
xPSRL.Q(xRegisterSSE(reg), 41);
xPSRL.Q(xRegisterSSE(absreg), 63); //sign bit
xPSLL.Q(xRegisterSSE(absreg), 31);
xPOR(xRegisterSSE(reg), xRegisterSSE(absreg));
end4 = JMP8(0);
}
x86SetJ8(is_zero);
}
SSE2_CVTSD2SS_XMM_to_XMM(reg, reg);
SSE_ANDPS_M128_to_XMM(reg, (uptr)s_const.neg); //flush to zero
xCVTSD2SS(xRegisterSSE(reg), xRegisterSSE(reg));
xAND.PS(xRegisterSSE(reg), ptr[s_const.neg]); //flush to zero
x86SetJ8(end);
x86SetJ8(end2);
@ -277,9 +277,9 @@ void ToPS2FPU(int reg, bool flags, int absreg, bool acc, bool addsub = false)
ToPS2FPU_Full(reg, flags, absreg, acc, addsub);
else
{
SSE2_CVTSD2SS_XMM_to_XMM(reg, reg); //clamp
SSE_MINSS_M32_to_XMM(reg, (uptr)&g_maxvals[0]);
SSE_MAXSS_M32_to_XMM(reg, (uptr)&g_minvals[0]);
xCVTSD2SS(xRegisterSSE(reg), xRegisterSSE(reg)); //clamp
xMIN.SS(xRegisterSSE(reg), ptr[&g_maxvals[0]]);
xMAX.SS(xRegisterSSE(reg), ptr[&g_minvals[0]]);
}
}
@ -287,33 +287,33 @@ void ToPS2FPU(int reg, bool flags, int absreg, bool acc, bool addsub = false)
void SetMaxValue(int regd)
{
if (FPU_RESULT)
SSE_ORPS_M128_to_XMM(regd, (uptr)&s_const.pos[0]); // set regd to maximum
xOR.PS(xRegisterSSE(regd), ptr[&s_const.pos[0]]); // set regd to maximum
else
{
SSE_ANDPS_M128_to_XMM(regd, (uptr)&s_const.neg[0]); // Get the sign bit
SSE_ORPS_M128_to_XMM(regd, (uptr)&g_maxvals[0]); // regd = +/- Maximum (CLAMP)!
xAND.PS(xRegisterSSE(regd), ptr[&s_const.neg[0]]); // Get the sign bit
xOR.PS(xRegisterSSE(regd), ptr[&g_maxvals[0]]); // regd = +/- Maximum (CLAMP)!
}
}
#define GET_S(sreg) { \
if( info & PROCESS_EE_S ) SSE_MOVSS_XMM_to_XMM(sreg, EEREC_S); \
else SSE_MOVSS_M32_to_XMM(sreg, (uptr)&fpuRegs.fpr[_Fs_]); }
if( info & PROCESS_EE_S ) xMOVSS(xRegisterSSE(sreg), xRegisterSSE(EEREC_S)); \
else xMOVSSZX(xRegisterSSE(sreg), ptr[&fpuRegs.fpr[_Fs_]]); }
#define ALLOC_S(sreg) { sreg = _allocTempXMMreg(XMMT_FPS, -1); GET_S(sreg); }
#define GET_T(treg) { \
if( info & PROCESS_EE_T ) SSE_MOVSS_XMM_to_XMM(treg, EEREC_T); \
else SSE_MOVSS_M32_to_XMM(treg, (uptr)&fpuRegs.fpr[_Ft_]); }
if( info & PROCESS_EE_T ) xMOVSS(xRegisterSSE(treg), xRegisterSSE(EEREC_T)); \
else xMOVSSZX(xRegisterSSE(treg), ptr[&fpuRegs.fpr[_Ft_]]); }
#define ALLOC_T(treg) { treg = _allocTempXMMreg(XMMT_FPS, -1); GET_T(treg); }
#define GET_ACC(areg) { \
if( info & PROCESS_EE_ACC ) SSE_MOVSS_XMM_to_XMM(areg, EEREC_ACC); \
else SSE_MOVSS_M32_to_XMM(areg, (uptr)&fpuRegs.ACC); }
if( info & PROCESS_EE_ACC ) xMOVSS(xRegisterSSE(areg), xRegisterSSE(EEREC_ACC)); \
else xMOVSSZX(xRegisterSSE(areg), ptr[&fpuRegs.ACC]); }
#define ALLOC_ACC(areg) { areg = _allocTempXMMreg(XMMT_FPS, -1); GET_ACC(areg); }
#define CLEAR_OU_FLAGS { AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO | FPUflagU)); }
#define CLEAR_OU_FLAGS { xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagO | FPUflagU)); }
//------------------------------------------------------------------
@ -325,7 +325,7 @@ void recABS_S_xmm(int info)
CLEAR_OU_FLAGS;
SSE_ANDPS_M128_to_XMM(EEREC_D, (uptr)s_const.pos);
xAND.PS(xRegisterSSE(EEREC_D), ptr[s_const.pos]);
}
FPURECOMPILE_CONSTCODE(ABS_S, XMMINFO_WRITED|XMMINFO_READS);
@ -351,50 +351,50 @@ void FPU_ADD_SUB(int tempd, int tempt) //tempd and tempt are overwritten, they a
if (tempecx != ECX) { Console.Error("FPU: ADD/SUB Allocation Error!"); tempecx = ECX;}
if (temp2 == -1) { Console.Error("FPU: ADD/SUB Allocation Error!"); temp2 = EAX;}
SSE2_MOVD_XMM_to_R(tempecx, tempd);
SSE2_MOVD_XMM_to_R(temp2, tempt);
xMOVD(xRegister32(tempecx), xRegisterSSE(tempd));
xMOVD(xRegister32(temp2), xRegisterSSE(tempt));
//mask the exponents
SHR32ItoR(tempecx, 23);
SHR32ItoR(temp2, 23);
AND32ItoR(tempecx, 0xff);
AND32ItoR(temp2, 0xff);
xSHR(xRegister32(tempecx), 23);
xSHR(xRegister32(temp2), 23);
xAND(xRegister32(tempecx), 0xff);
xAND(xRegister32(temp2), 0xff);
SUB32RtoR(tempecx, temp2); //tempecx = exponent difference
CMP32ItoR(tempecx, 25);
xSUB(xRegister32(tempecx), xRegister32(temp2)); //tempecx = exponent difference
xCMP(xRegister32(tempecx), 25);
j8Ptr[0] = JGE8(0);
CMP32ItoR(tempecx, 0);
xCMP(xRegister32(tempecx), 0);
j8Ptr[1] = JG8(0);
j8Ptr[2] = JE8(0);
CMP32ItoR(tempecx, -25);
xCMP(xRegister32(tempecx), -25);
j8Ptr[3] = JLE8(0);
//diff = -24 .. -1 , expd < expt
NEG32R(tempecx);
DEC32R(tempecx);
MOV32ItoR(temp2, 0xffffffff);
SHL32CLtoR(temp2); //temp2 = 0xffffffff << tempecx
SSE2_MOVD_R_to_XMM(xmmtemp, temp2);
SSE_ANDPS_XMM_to_XMM(tempd, xmmtemp);
xNEG(xRegister32(tempecx));
xDEC(xRegister32(tempecx));
xMOV(xRegister32(temp2), 0xffffffff);
xSHL(xRegister32(temp2), cl); //temp2 = 0xffffffff << tempecx
xMOVDZX(xRegisterSSE(xmmtemp), xRegister32(temp2));
xAND.PS(xRegisterSSE(tempd), xRegisterSSE(xmmtemp));
j8Ptr[4] = JMP8(0);
x86SetJ8(j8Ptr[0]);
//diff = 25 .. 255 , expt < expd
SSE_ANDPS_M128_to_XMM(tempt, (uptr)s_const.neg);
xAND.PS(xRegisterSSE(tempt), ptr[s_const.neg]);
j8Ptr[5] = JMP8(0);
x86SetJ8(j8Ptr[1]);
//diff = 1 .. 24, expt < expd
DEC32R(tempecx);
MOV32ItoR(temp2, 0xffffffff);
SHL32CLtoR(temp2); //temp2 = 0xffffffff << tempecx
SSE2_MOVD_R_to_XMM(xmmtemp, temp2);
SSE_ANDPS_XMM_to_XMM(tempt, xmmtemp);
xDEC(xRegister32(tempecx));
xMOV(xRegister32(temp2), 0xffffffff);
xSHL(xRegister32(temp2), cl); //temp2 = 0xffffffff << tempecx
xMOVDZX(xRegisterSSE(xmmtemp), xRegister32(temp2));
xAND.PS(xRegisterSSE(tempt), xRegisterSSE(xmmtemp));
j8Ptr[6] = JMP8(0);
x86SetJ8(j8Ptr[3]);
//diff = -255 .. -25, expd < expt
SSE_ANDPS_M128_to_XMM(tempd, (uptr)s_const.neg);
xAND.PS(xRegisterSSE(tempd), ptr[s_const.neg]);
j8Ptr[7] = JMP8(0);
x86SetJ8(j8Ptr[2]);
@ -417,20 +417,20 @@ void FPU_MUL(int info, int regd, int sreg, int treg, bool acc)
if (CHECK_FPUMULHACK)
{
SSE2_MOVD_XMM_to_R(ECX, sreg);
SSE2_MOVD_XMM_to_R(EDX, treg);
CALLFunc( (uptr)&FPU_MUL_HACK ); //returns the hacked result or 0
TEST32RtoR(EAX, EAX);
xMOVD(ecx, xRegisterSSE(sreg));
xMOVD(edx, xRegisterSSE(treg));
xCALL((void*)(uptr)&FPU_MUL_HACK ); //returns the hacked result or 0
xTEST(eax, eax);
noHack = JZ8(0);
SSE2_MOVD_R_to_XMM(regd, EAX);
xMOVDZX(xRegisterSSE(regd), eax);
endMul = JMP32(0);
x86SetJ8(noHack);
}
ToDouble(sreg); ToDouble(treg);
SSE2_MULSD_XMM_to_XMM(sreg, treg);
xMUL.SD(xRegisterSSE(sreg), xRegisterSSE(treg));
ToPS2FPU(sreg, true, treg, acc);
SSE_MOVSS_XMM_to_XMM(regd, sreg);
xMOVSS(xRegisterSSE(regd), xRegisterSSE(sreg));
if (CHECK_FPUMULHACK)
x86SetJ32(endMul);
@ -455,7 +455,7 @@ void recFPUOp(int info, int regd, int op, bool acc)
recFPUOpXMM_to_XMM[op](sreg, treg);
ToPS2FPU(sreg, true, treg, acc, true);
SSE_MOVSS_XMM_to_XMM(regd, sreg);
xMOVSS(xRegisterSSE(regd), xRegisterSSE(sreg));
_freeXMMreg(sreg); _freeXMMreg(treg);
}
@ -486,7 +486,7 @@ void recCMP(int info)
ALLOC_S(sreg); ALLOC_T(treg);
ToDouble(sreg); ToDouble(treg);
SSE2_UCOMISD_XMM_to_XMM(sreg, treg);
xUCOMI.SD(xRegisterSSE(sreg), xRegisterSSE(treg));
_freeXMMreg(sreg); _freeXMMreg(treg);
}
@ -499,10 +499,10 @@ void recC_EQ_xmm(int info)
recCMP(info);
j8Ptr[0] = JZ8(0);
AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC );
j8Ptr[1] = JMP8(0);
x86SetJ8(j8Ptr[0]);
OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC);
x86SetJ8(j8Ptr[1]);
}
@ -513,10 +513,10 @@ void recC_LE_xmm(int info )
recCMP(info);
j8Ptr[0] = JBE8(0);
AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC );
j8Ptr[1] = JMP8(0);
x86SetJ8(j8Ptr[0]);
OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC);
x86SetJ8(j8Ptr[1]);
}
@ -527,10 +527,10 @@ void recC_LT_xmm(int info)
recCMP(info);
j8Ptr[0] = JB8(0);
AND32ItoM( (uptr)&fpuRegs.fprc[31], ~FPUflagC );
xAND(ptr32[&fpuRegs.fprc[31]], ~FPUflagC );
j8Ptr[1] = JMP8(0);
x86SetJ8(j8Ptr[0]);
OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagC);
xOR(ptr32[&fpuRegs.fprc[31]], FPUflagC);
x86SetJ8(j8Ptr[1]);
}
@ -544,10 +544,10 @@ FPURECOMPILE_CONSTCODE(C_LT, XMMINFO_READS|XMMINFO_READT);
void recCVT_S_xmm(int info)
{
if( !(info&PROCESS_EE_S) || (EEREC_D != EEREC_S && !(info&PROCESS_EE_MODEWRITES)) ) {
SSE_CVTSI2SS_M32_to_XMM(EEREC_D, (uptr)&fpuRegs.fpr[_Fs_]);
xCVTSI2SS(xRegisterSSE(EEREC_D), ptr32[&fpuRegs.fpr[_Fs_]]);
}
else {
SSE2_CVTDQ2PS_XMM_to_XMM(EEREC_D, EEREC_S);
xCVTDQ2PS(xRegisterSSE(EEREC_D), xRegisterSSE(EEREC_S));
}
}
@ -559,27 +559,27 @@ void recCVT_W() //called from iFPU.cpp's recCVT_W
if( regs >= 0 )
{
SSE_CVTTSS2SI_XMM_to_R32(EAX, regs);
SSE_MOVMSKPS_XMM_to_R32(EDX, regs); //extract the signs
AND32ItoR(EDX,1); //keep only LSB
xCVTTSS2SI(eax, xRegisterSSE(regs));
xMOVMSKPS(edx, xRegisterSSE(regs)); //extract the signs
xAND(edx, 1); //keep only LSB
}
else
{
SSE_CVTTSS2SI_M32_to_R32(EAX, (uptr)&fpuRegs.fpr[ _Fs_ ]);
MOV32MtoR(EDX, (uptr)&fpuRegs.fpr[ _Fs_ ]);
SHR32ItoR(EDX, 31); //mov sign to lsb
xCVTTSS2SI(eax, ptr32[&fpuRegs.fpr[ _Fs_ ]]);
xMOV(edx, ptr[&fpuRegs.fpr[ _Fs_ ]]);
xSHR(edx, 31); //mov sign to lsb
}
//kill register allocation for dst because we write directly to fpuRegs.fpr[_Fd_]
_deleteFPtoXMMreg(_Fd_, 2);
ADD32ItoR(EDX, 0x7FFFFFFF); //0x7FFFFFFF if positive, 0x8000 0000 if negative
xADD(edx, 0x7FFFFFFF); //0x7FFFFFFF if positive, 0x8000 0000 if negative
CMP32ItoR(EAX, 0x80000000); //If the result is indefinitive
CMOVE32RtoR(EAX, EDX); //Saturate it
xCMP(eax, 0x80000000); //If the result is indefinitive
xCMOVE(eax, edx); //Saturate it
//Write the result
MOV32RtoM((uptr)&fpuRegs.fpr[_Fd_], EAX);
xMOV(ptr[&fpuRegs.fpr[_Fd_]], eax);
}
//------------------------------------------------------------------
@ -596,29 +596,29 @@ void recDIVhelper1(int regd, int regt) // Sets flags
if (t1reg == -1) {Console.Error("FPU: DIV Allocation Error!"); return;}
if (tempReg == -1) {Console.Error("FPU: DIV Allocation Error!"); tempReg = EAX;}
AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagI|FPUflagD)); // Clear I and D flags
xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagI|FPUflagD)); // Clear I and D flags
//--- Check for divide by zero ---
SSE_XORPS_XMM_to_XMM(t1reg, t1reg);
SSE_CMPEQSS_XMM_to_XMM(t1reg, regt);
SSE_MOVMSKPS_XMM_to_R32(tempReg, t1reg);
AND32ItoR(tempReg, 1); //Check sign (if regt == zero, sign will be set)
xXOR.PS(xRegisterSSE(t1reg), xRegisterSSE(t1reg));
xCMPEQ.SS(xRegisterSSE(t1reg), xRegisterSSE(regt));
xMOVMSKPS(xRegister32(tempReg), xRegisterSSE(t1reg));
xAND(xRegister32(tempReg), 1); //Check sign (if regt == zero, sign will be set)
ajmp32 = JZ32(0); //Skip if not set
//--- Check for 0/0 ---
SSE_XORPS_XMM_to_XMM(t1reg, t1reg);
SSE_CMPEQSS_XMM_to_XMM(t1reg, regd);
SSE_MOVMSKPS_XMM_to_R32(tempReg, t1reg);
AND32ItoR(tempReg, 1); //Check sign (if regd == zero, sign will be set)
xXOR.PS(xRegisterSSE(t1reg), xRegisterSSE(t1reg));
xCMPEQ.SS(xRegisterSSE(t1reg), xRegisterSSE(regd));
xMOVMSKPS(xRegister32(tempReg), xRegisterSSE(t1reg));
xAND(xRegister32(tempReg), 1); //Check sign (if regd == zero, sign will be set)
pjmp1 = JZ8(0); //Skip if not set
OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagI|FPUflagSI); // Set I and SI flags ( 0/0 )
xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI|FPUflagSI); // Set I and SI flags ( 0/0 )
pjmp2 = JMP8(0);
x86SetJ8(pjmp1); //x/0 but not 0/0
OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagD|FPUflagSD); // Set D and SD flags ( x/0 )
xOR(ptr32[&fpuRegs.fprc[31]], FPUflagD|FPUflagSD); // Set D and SD flags ( x/0 )
x86SetJ8(pjmp2);
//--- Make regd +/- Maximum ---
SSE_XORPS_XMM_to_XMM(regd, regt); // Make regd Positive or Negative
xXOR.PS(xRegisterSSE(regd), xRegisterSSE(regt)); // Make regd Positive or Negative
SetMaxValue(regd); //clamp to max
bjmp32 = JMP32(0);
@ -627,7 +627,7 @@ void recDIVhelper1(int regd, int regt) // Sets flags
//--- Normal Divide ---
ToDouble(regd); ToDouble(regt);
SSE2_DIVSD_XMM_to_XMM(regd, regt);
xDIV.SD(xRegisterSSE(regd), xRegisterSSE(regt));
ToPS2FPU(regd, false, regt, false);
@ -641,7 +641,7 @@ void recDIVhelper2(int regd, int regt) // Doesn't sets flags
{
ToDouble(regd); ToDouble(regt);
SSE2_DIVSD_XMM_to_XMM(regd, regt);
xDIV.SD(xRegisterSSE(regd), xRegisterSSE(regt));
ToPS2FPU(regd, false, regt, false);
}
@ -690,7 +690,7 @@ void recDIV_S_xmm(int info)
else
recDIVhelper2(sreg, treg);
SSE_MOVSS_XMM_to_XMM(EEREC_D, sreg);
xMOVSS(xRegisterSSE(EEREC_D), xRegisterSSE(sreg));
if (roundmodeFlag) xLDMXCSR (g_sseMXCSR);
_freeXMMreg(sreg); _freeXMMreg(treg);
@ -724,41 +724,41 @@ void recMaddsub(int info, int regd, int op, bool acc)
// TEST FOR ACC/MUL OVERFLOWS, PROPOGATE THEM IF THEY OCCUR
TEST32ItoM((uptr)&fpuRegs.fprc[31], FPUflagO);
xTEST(ptr32[&fpuRegs.fprc[31]], FPUflagO);
u8 *mulovf = JNZ8(0);
ToDouble(sreg); //else, convert
TEST32ItoM((uptr)&fpuRegs.ACCflag, 1);
xTEST(ptr32[&fpuRegs.ACCflag], 1);
u8 *accovf = JNZ8(0);
ToDouble(treg); //else, convert
u8 *operation = JMP8(0);
x86SetJ8(mulovf);
if (op == 1) //sub
SSE_XORPS_M128_to_XMM(sreg, (uptr)s_const.neg);
SSE_MOVAPS_XMM_to_XMM(treg, sreg); //fall through below
xXOR.PS(xRegisterSSE(sreg), ptr[s_const.neg]);
xMOVAPS(xRegisterSSE(treg), xRegisterSSE(sreg)); //fall through below
x86SetJ8(accovf);
SetMaxValue(treg); //just in case... I think it has to be a MaxValue already here
CLEAR_OU_FLAGS; //clear U flag
if (FPU_FLAGS_OVERFLOW)
OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagO | FPUflagSO);
xOR(ptr32[&fpuRegs.fprc[31]], FPUflagO | FPUflagSO);
if (FPU_FLAGS_OVERFLOW && acc)
OR32ItoM((uptr)&fpuRegs.ACCflag, 1);
xOR(ptr32[&fpuRegs.ACCflag], 1);
u32 *skipall = JMP32(0);
// PERFORM THE ACCUMULATION AND TEST RESULT. CONVERT TO SINGLE
x86SetJ8(operation);
if (op == 1)
SSE2_SUBSD_XMM_to_XMM(treg, sreg);
xSUB.SD(xRegisterSSE(treg), xRegisterSSE(sreg));
else
SSE2_ADDSD_XMM_to_XMM(treg, sreg);
xADD.SD(xRegisterSSE(treg), xRegisterSSE(sreg));
ToPS2FPU(treg, true, sreg, acc, true);
x86SetJ32(skipall);
SSE_MOVSS_XMM_to_XMM(regd, treg);
xMOVSS(xRegisterSSE(regd), xRegisterSSE(treg));
_freeXMMreg(sreg); _freeXMMreg(treg);
}
@ -796,18 +796,18 @@ void recMINMAX(int info, bool ismin)
CLEAR_OU_FLAGS;
SSE2_PSHUFD_XMM_to_XMM(sreg, sreg, 0x00);
SSE2_PAND_M128_to_XMM(sreg, (uptr)minmax_mask);
SSE2_POR_M128_to_XMM(sreg, (uptr)&minmax_mask[4]);
SSE2_PSHUFD_XMM_to_XMM(treg, treg, 0x00);
SSE2_PAND_M128_to_XMM(treg, (uptr)minmax_mask);
SSE2_POR_M128_to_XMM(treg, (uptr)&minmax_mask[4]);
xPSHUF.D(xRegisterSSE(sreg), xRegisterSSE(sreg), 0x00);
xPAND(xRegisterSSE(sreg), ptr[minmax_mask]);
xPOR(xRegisterSSE(sreg), ptr[&minmax_mask[4]]);
xPSHUF.D(xRegisterSSE(treg), xRegisterSSE(treg), 0x00);
xPAND(xRegisterSSE(treg), ptr[minmax_mask]);
xPOR(xRegisterSSE(treg), ptr[&minmax_mask[4]]);
if (ismin)
SSE2_MINSD_XMM_to_XMM(sreg, treg);
xMIN.SD(xRegisterSSE(sreg), xRegisterSSE(treg));
else
SSE2_MAXSD_XMM_to_XMM(sreg, treg);
xMAX.SD(xRegisterSSE(sreg), xRegisterSSE(treg));
SSE_MOVSS_XMM_to_XMM(EEREC_D, sreg);
xMOVSS(xRegisterSSE(EEREC_D), xRegisterSSE(sreg));
_freeXMMreg(sreg); _freeXMMreg(treg);
}
@ -895,7 +895,7 @@ void recNEG_S_xmm(int info) {
CLEAR_OU_FLAGS;
SSE_XORPS_M128_to_XMM(EEREC_D, (uptr)&s_const.neg[0]);
xXOR.PS(xRegisterSSE(EEREC_D), ptr[&s_const.neg[0]]);
}
FPURECOMPILE_CONSTCODE(NEG_S, XMMINFO_WRITED|XMMINFO_READS);
@ -949,25 +949,25 @@ void recSQRT_S_xmm(int info)
GET_T(EEREC_D);
if (FPU_FLAGS_ID) {
AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagI|FPUflagD)); // Clear I and D flags
xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagI|FPUflagD)); // Clear I and D flags
//--- Check for negative SQRT --- (sqrt(-0) = 0, unlike what the docs say)
SSE_MOVMSKPS_XMM_to_R32(tempReg, EEREC_D);
AND32ItoR(tempReg, 1); //Check sign
xMOVMSKPS(xRegister32(tempReg), xRegisterSSE(EEREC_D));
xAND(xRegister32(tempReg), 1); //Check sign
pjmp = JZ8(0); //Skip if none are
OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagI|FPUflagSI); // Set I and SI flags
SSE_ANDPS_M128_to_XMM(EEREC_D, (uptr)&s_const.pos[0]); // Make EEREC_D Positive
xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI|FPUflagSI); // Set I and SI flags
xAND.PS(xRegisterSSE(EEREC_D), ptr[&s_const.pos[0]]); // Make EEREC_D Positive
x86SetJ8(pjmp);
}
else
{
SSE_ANDPS_M128_to_XMM(EEREC_D, (uptr)&s_const.pos[0]); // Make EEREC_D Positive
xAND.PS(xRegisterSSE(EEREC_D), ptr[&s_const.pos[0]]); // Make EEREC_D Positive
}
ToDouble(EEREC_D);
SSE2_SQRTSD_XMM_to_XMM(EEREC_D, EEREC_D);
xSQRT.SD(xRegisterSSE(EEREC_D), xRegisterSSE(EEREC_D));
ToPS2FPU(EEREC_D, false, t1reg, false);
@ -996,33 +996,33 @@ void recRSQRThelper1(int regd, int regt) // Preforms the RSQRT function when reg
if (t1reg == -1) {Console.Error("FPU: RSQRT Allocation Error!"); return;}
if (tempReg == -1) {Console.Error("FPU: RSQRT Allocation Error!"); tempReg = EAX;}
AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagI|FPUflagD)); // Clear I and D flags
xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagI|FPUflagD)); // Clear I and D flags
//--- (first) Check for negative SQRT ---
SSE_MOVMSKPS_XMM_to_R32(tempReg, regt);
AND32ItoR(tempReg, 1); //Check sign
xMOVMSKPS(xRegister32(tempReg), xRegisterSSE(regt));
xAND(xRegister32(tempReg), 1); //Check sign
pjmp2 = JZ8(0); //Skip if not set
OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagI|FPUflagSI); // Set I and SI flags
SSE_ANDPS_M128_to_XMM(regt, (uptr)&s_const.pos[0]); // Make regt Positive
xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI|FPUflagSI); // Set I and SI flags
xAND.PS(xRegisterSSE(regt), ptr[&s_const.pos[0]]); // Make regt Positive
x86SetJ8(pjmp2);
//--- Check for zero ---
SSE_XORPS_XMM_to_XMM(t1reg, t1reg);
SSE_CMPEQSS_XMM_to_XMM(t1reg, regt);
SSE_MOVMSKPS_XMM_to_R32(tempReg, t1reg);
AND32ItoR(tempReg, 1); //Check sign (if regt == zero, sign will be set)
xXOR.PS(xRegisterSSE(t1reg), xRegisterSSE(t1reg));
xCMPEQ.SS(xRegisterSSE(t1reg), xRegisterSSE(regt));
xMOVMSKPS(xRegister32(tempReg), xRegisterSSE(t1reg));
xAND(xRegister32(tempReg), 1); //Check sign (if regt == zero, sign will be set)
pjmp1 = JZ8(0); //Skip if not set
//--- Check for 0/0 ---
SSE_XORPS_XMM_to_XMM(t1reg, t1reg);
SSE_CMPEQSS_XMM_to_XMM(t1reg, regd);
SSE_MOVMSKPS_XMM_to_R32(tempReg, t1reg);
AND32ItoR(tempReg, 1); //Check sign (if regd == zero, sign will be set)
xXOR.PS(xRegisterSSE(t1reg), xRegisterSSE(t1reg));
xCMPEQ.SS(xRegisterSSE(t1reg), xRegisterSSE(regd));
xMOVMSKPS(xRegister32(tempReg), xRegisterSSE(t1reg));
xAND(xRegister32(tempReg), 1); //Check sign (if regd == zero, sign will be set)
qjmp1 = JZ8(0); //Skip if not set
OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagI|FPUflagSI); // Set I and SI flags ( 0/0 )
xOR(ptr32[&fpuRegs.fprc[31]], FPUflagI|FPUflagSI); // Set I and SI flags ( 0/0 )
qjmp2 = JMP8(0);
x86SetJ8(qjmp1); //x/0 but not 0/0
OR32ItoM((uptr)&fpuRegs.fprc[31], FPUflagD|FPUflagSD); // Set D and SD flags ( x/0 )
xOR(ptr32[&fpuRegs.fprc[31]], FPUflagD|FPUflagSD); // Set D and SD flags ( x/0 )
x86SetJ8(qjmp2);
SetMaxValue(regd); //clamp to max
@ -1031,8 +1031,8 @@ void recRSQRThelper1(int regd, int regt) // Preforms the RSQRT function when reg
ToDouble(regt); ToDouble(regd);
SSE2_SQRTSD_XMM_to_XMM(regt, regt);
SSE2_DIVSD_XMM_to_XMM(regd, regt);
xSQRT.SD(xRegisterSSE(regt), xRegisterSSE(regt));
xDIV.SD(xRegisterSSE(regd), xRegisterSSE(regt));
ToPS2FPU(regd, false, regt, false);
x86SetJ32(pjmp32);
@ -1043,12 +1043,12 @@ void recRSQRThelper1(int regd, int regt) // Preforms the RSQRT function when reg
void recRSQRThelper2(int regd, int regt) // Preforms the RSQRT function when regd <- Fs and regt <- Ft (Doesn't set flags)
{
SSE_ANDPS_M128_to_XMM(regt, (uptr)&s_const.pos[0]); // Make regt Positive
xAND.PS(xRegisterSSE(regt), ptr[&s_const.pos[0]]); // Make regt Positive
ToDouble(regt); ToDouble(regd);
SSE2_SQRTSD_XMM_to_XMM(regt, regt);
SSE2_DIVSD_XMM_to_XMM(regd, regt);
xSQRT.SD(xRegisterSSE(regt), xRegisterSSE(regt));
xDIV.SD(xRegisterSSE(regd), xRegisterSSE(regt));
ToPS2FPU(regd, false, regt, false);
}
@ -1079,7 +1079,7 @@ void recRSQRT_S_xmm(int info)
else
recRSQRThelper2(sreg, treg);
SSE_MOVSS_XMM_to_XMM(EEREC_D, sreg);
xMOVSS(xRegisterSSE(EEREC_D), xRegisterSSE(sreg));
_freeXMMreg(treg); _freeXMMreg(sreg);

1584
pcsx2/x86/iMMI.cpp
View File

File diff suppressed because it is too large Load Diff

136
pcsx2/x86/iPsxMem.cpp
View File

@ -109,10 +109,10 @@ int psxRecMemConstRead8(u32 x86reg, u32 mem, u32 sign)
return psxHw4ConstRead8(x86reg, mem&0x1fffffff, sign);
case 0x1000:
PUSH32I(mem&0x1fffffff);
CALLFunc((uptr)DEV9read8);
if( sign ) MOVSX32R8toR(x86reg, EAX);
else MOVZX32R8toR(x86reg, EAX);
xPUSH(mem&0x1fffffff);
xCALL((void*)(uptr)DEV9read8);
if( sign ) xMOVSX(xRegister32(x86reg), al);
else xMOVZX(xRegister32(x86reg), al);
return 0;
default:
@ -201,10 +201,10 @@ int psxRecMemConstRead16(u32 x86reg, u32 mem, u32 sign)
{
case 0x40:
_eeReadConstMem16(x86reg, (u32)PS2MEM_HW+0xF240, sign);
OR32ItoR(x86reg, 0x0002);
xOR(xRegister32(x86reg), 0x0002);
break;
case 0x60:
XOR32RtoR(x86reg, x86reg);
xXOR(xRegister32(x86reg), xRegister32(x86reg));
break;
default:
_eeReadConstMem16(x86reg, (u32)PS2MEM_HW+0xf200+(mem&0xf0), sign);
@ -213,17 +213,17 @@ int psxRecMemConstRead16(u32 x86reg, u32 mem, u32 sign)
return 0;
case 0x1f90:
PUSH32I(mem&0x1fffffff);
CALLFunc((uptr)SPU2read);
if( sign ) MOVSX32R16toR(x86reg, EAX);
else MOVZX32R16toR(x86reg, EAX);
xPUSH(mem&0x1fffffff);
xCALL((void*)(uptr)SPU2read);
if( sign ) xMOVSX(xRegister32(x86reg), ax);
else xMOVZX(xRegister32(x86reg), ax);
return 0;
case 0x1000:
PUSH32I(mem&0x1fffffff);
CALLFunc((uptr)DEV9read16);
if( sign ) MOVSX32R16toR(x86reg, EAX);
else MOVZX32R16toR(x86reg, EAX);
xPUSH(mem&0x1fffffff);
xCALL((void*)(uptr)DEV9read16);
if( sign ) xMOVSX(xRegister32(x86reg), ax);
else xMOVZX(xRegister32(x86reg), ax);
return 0;
default:
@ -311,10 +311,10 @@ int psxRecMemConstRead32(u32 x86reg, u32 mem)
{
case 0x40:
_eeReadConstMem32(x86reg, (u32)PS2MEM_HW+0xF240);
OR32ItoR(x86reg, 0xf0000002);
xOR(xRegister32(x86reg), 0xf0000002);
break;
case 0x60:
XOR32RtoR(x86reg, x86reg);
xXOR(xRegister32(x86reg), xRegister32(x86reg));
break;
default:
_eeReadConstMem32(x86reg, (u32)PS2MEM_HW+0xf200+(mem&0xf0));
@ -323,16 +323,16 @@ int psxRecMemConstRead32(u32 x86reg, u32 mem)
return 0;
case 0x1000:
PUSH32I(mem&0x1fffffff);
CALLFunc((uptr)DEV9read32);
xPUSH(mem&0x1fffffff);
xCALL((void*)(uptr)DEV9read32);
return 1;
default:
if( mem == 0xfffe0130 )
MOV32MtoR(x86reg, (uptr)&writectrl);
xMOV(xRegister32(x86reg), ptr[&writectrl]);
else {
XOR32RtoR(x86reg, x86reg);
CMP32ItoM((uptr)&g_psxWriteOk, 0);
xXOR(xRegister32(x86reg), xRegister32(x86reg));
xCMP(ptr32[&g_psxWriteOk], 0);
CMOVNE32MtoR(x86reg, (u32)PSXM(mem));
}
@ -406,8 +406,8 @@ int psxRecMemConstWrite8(u32 mem, int mmreg)
case 0x1000:
_recPushReg(mmreg);
PUSH32I(mem&0x1fffffff);
CALLFunc((uptr)DEV9write8);
xPUSH(mem&0x1fffffff);
xCALL((void*)(uptr)DEV9write8);
return 0;
default:
@ -533,34 +533,34 @@ int psxRecMemConstWrite16(u32 mem, int mmreg)
_eeMoveMMREGtoR(EAX, mmreg);
assert( mmreg != EBX );
MOV16MtoR(EBX, (u32)PS2MEM_HW+0xf240);
TEST16ItoR(EAX, 0xa0);
xMOV(bx, ptr[(void*)((u32)PS2MEM_HW+0xf240)]);
xTEST(ax, 0xa0);
j8Ptr[0] = JZ8(0);
AND16ItoR(EBX, 0x0fff);
OR16ItoR(EBX, 0x2000);
xAND(bx, 0x0fff);
xOR(bx, 0x2000);
x86SetJ8(j8Ptr[0]);
AND16ItoR(EAX, 0xf0);
TEST16RtoR(EAX, 0xf0);
xAND(ax, 0xf0);
xTEST(ax, xRegister16(0xf0));
j8Ptr[0] = JZ8(0);
NOT32R(EAX);
AND16RtoR(EBX, EAX);
xNOT(eax);
xAND(bx, ax);
j8Ptr[1] = JMP8(0);
x86SetJ8(j8Ptr[0]);
OR16RtoR(EBX, EAX);
xOR(bx, ax);
x86SetJ8(j8Ptr[1]);
MOV16RtoM((u32)PS2MEM_HW+0xf240, EBX);
xMOV(ptr[(void*)((u32)PS2MEM_HW+0xf240)], bx);
return 0;
}
case 0x60:
MOV32ItoM((u32)(PS2MEM_HW+0xf260), 0);
xMOV(ptr32[(u32*)((u32)(PS2MEM_HW+0xf260))], 0);
return 0;
default:
assert(0);
@ -569,14 +569,14 @@ int psxRecMemConstWrite16(u32 mem, int mmreg)
case 0x1f90:
_recPushReg(mmreg);
PUSH32I(mem&0x1fffffff);
CALLFunc((uptr)SPU2write);
xPUSH(mem&0x1fffffff);
xCALL((void*)(uptr)SPU2write);
return 0;
case 0x1000:
_recPushReg(mmreg);
PUSH32I(mem&0x1fffffff);
CALLFunc((uptr)DEV9write16);
xPUSH(mem&0x1fffffff);
xCALL((void*)(uptr)DEV9write16);
return 0;
default:
@ -735,11 +735,11 @@ int psxRecMemConstWrite32(u32 mem, int mmreg)
// write to ps2 mem
// delete x86reg
if( IS_PSXCONSTREG(mmreg) ) {
AND32ItoM((u32)PS2MEM_HW+0xf220, ~g_psxConstRegs[(mmreg>>16)&0x1f]);
xAND(ptr32[(u32*)((u32)PS2MEM_HW+0xf220)], ~g_psxConstRegs[(mmreg>>16)&0x1f]);
}
else {
NOT32R(mmreg);
AND32RtoM((u32)PS2MEM_HW+0xf220, mmreg);
xNOT(xRegister32(mmreg));
xAND(ptr[(void*)((u32)PS2MEM_HW+0xf220)], xRegister32(mmreg));
}
return 0;
case 0x30:
@ -753,34 +753,34 @@ int psxRecMemConstWrite32(u32 mem, int mmreg)
_eeMoveMMREGtoR(EAX, mmreg);
MOV16MtoR(EBX, (u32)PS2MEM_HW+0xf240);
TEST16ItoR(EAX, 0xa0);
xMOV(bx, ptr[(void*)((u32)PS2MEM_HW+0xf240)]);
xTEST(ax, 0xa0);
j8Ptr[0] = JZ8(0);
AND16ItoR(EBX, 0x0fff);
OR16ItoR(EBX, 0x2000);
xAND(bx, 0x0fff);
xOR(bx, 0x2000);
x86SetJ8(j8Ptr[0]);
AND16ItoR(EAX, 0xf0);
TEST16RtoR(EAX, 0xf0);
xAND(ax, 0xf0);
xTEST(ax, xRegister16(0xf0));
j8Ptr[0] = JZ8(0);
NOT32R(EAX);
AND16RtoR(EBX, EAX);
xNOT(eax);
xAND(bx, ax);
j8Ptr[1] = JMP8(0);
x86SetJ8(j8Ptr[0]);
OR16RtoR(EBX, EAX);
xOR(bx, ax);
x86SetJ8(j8Ptr[1]);
MOV16RtoM((u32)PS2MEM_HW+0xf240, EBX);
xMOV(ptr[(void*)((u32)PS2MEM_HW+0xf240)], bx);
return 0;
}
case 0x60:
MOV32ItoM((u32)(PS2MEM_HW+0xf260), 0);
xMOV(ptr32[(u32*)((u32)(PS2MEM_HW+0xf260))], 0);
return 0;
default:
assert(0);
@ -789,8 +789,8 @@ int psxRecMemConstWrite32(u32 mem, int mmreg)
case 0x1000:
_recPushReg(mmreg);
PUSH32I(mem&0x1fffffff);
CALLFunc((uptr)DEV9write32);
xPUSH(mem&0x1fffffff);
xCALL((void*)(uptr)DEV9write32);
return 0;
case 0x1ffe:
@ -805,11 +805,11 @@ int psxRecMemConstWrite32(u32 mem, int mmreg)
case 0xc00: case 0xc04:
case 0xcc0: case 0xcc4:
case 0x0c4:
MOV32ItoM((uptr)&g_psxWriteOk, 0);
xMOV(ptr32[&g_psxWriteOk], 0);
break;
case 0x1e988:
case 0x1edd8:
MOV32ItoM((uptr)&g_psxWriteOk, 1);
xMOV(ptr32[&g_psxWriteOk], 1);
break;
default:
assert(0);
@ -817,25 +817,25 @@ int psxRecMemConstWrite32(u32 mem, int mmreg)
}
else {
// not ok
CMP32ItoR(mmreg, 0x800);
xCMP(xRegister32(mmreg), 0x800);
ptrs[0] = JE8(0);
CMP32ItoR(mmreg, 0x804);
xCMP(xRegister32(mmreg), 0x804);
ptrs[1] = JE8(0);
CMP32ItoR(mmreg, 0xc00);
xCMP(xRegister32(mmreg), 0xc00);
ptrs[2] = JE8(0);
CMP32ItoR(mmreg, 0xc04);
xCMP(xRegister32(mmreg), 0xc04);
ptrs[3] = JE8(0);
CMP32ItoR(mmreg, 0xcc0);
xCMP(xRegister32(mmreg), 0xcc0);
ptrs[4] = JE8(0);
CMP32ItoR(mmreg, 0xcc4);
xCMP(xRegister32(mmreg), 0xcc4);
ptrs[5] = JE8(0);
CMP32ItoR(mmreg, 0x0c4);
xCMP(xRegister32(mmreg), 0x0c4);
ptrs[6] = JE8(0);
// ok
CMP32ItoR(mmreg, 0x1e988);
xCMP(xRegister32(mmreg), 0x1e988);
ptrs[7] = JE8(0);
CMP32ItoR(mmreg, 0x1edd8);
xCMP(xRegister32(mmreg), 0x1edd8);
ptrs[8] = JE8(0);
x86SetJ8(ptrs[0]);
@ -845,12 +845,12 @@ int psxRecMemConstWrite32(u32 mem, int mmreg)
x86SetJ8(ptrs[4]);
x86SetJ8(ptrs[5]);
x86SetJ8(ptrs[6]);
MOV32ItoM((uptr)&g_psxWriteOk, 0);
xMOV(ptr32[&g_psxWriteOk], 0);
ptrs[0] = JMP8(0);
x86SetJ8(ptrs[7]);
x86SetJ8(ptrs[8]);
MOV32ItoM((uptr)&g_psxWriteOk, 1);
xMOV(ptr32[&g_psxWriteOk], 1);
x86SetJ8(ptrs[0]);
}
@ -858,7 +858,7 @@ int psxRecMemConstWrite32(u32 mem, int mmreg)
return 0;
default:
TEST8ItoM((uptr)&g_psxWriteOk, 1);
xTEST(ptr8[(u8*)((uptr)&g_psxWriteOk)], 1);
j8Ptr[0] = JZ8(0);
_eeWriteConstMem32((u32)PSXM(mem), mmreg);
x86SetJ8(j8Ptr[0]);

62
pcsx2/x86/iR3000A.cpp
View File

@ -485,7 +485,7 @@ int _psxFlushUnusedConstReg()
!_recIsRegWritten(g_pCurInstInfo+1, (s_nEndBlock-psxpc)/4, XMMTYPE_GPRREG, i) ) {
// check if will be written in the future
MOV32ItoM((uptr)&psxRegs.GPR.r[i], g_psxConstRegs[i]);
xMOV(ptr32[&psxRegs.GPR.r[i]], g_psxConstRegs[i]);
g_psxFlushedConstReg |= 1<<i;
return 1;
}
@ -502,7 +502,7 @@ void _psxFlushCachedRegs()
void _psxFlushConstReg(int reg)
{
if( PSX_IS_CONST1( reg ) && !(g_psxFlushedConstReg&(1<<reg)) ) {
MOV32ItoM((uptr)&psxRegs.GPR.r[reg], g_psxConstRegs[reg]);
xMOV(ptr32[&psxRegs.GPR.r[reg]], g_psxConstRegs[reg]);
g_psxFlushedConstReg |= (1<<reg);
}
}
@ -518,7 +518,7 @@ void _psxFlushConstRegs()
if( g_psxHasConstReg & (1<<i) ) {
if( !(g_psxFlushedConstReg&(1<<i)) ) {
MOV32ItoM((uptr)&psxRegs.GPR.r[i], g_psxConstRegs[i]);
xMOV(ptr32[&psxRegs.GPR.r[i]], g_psxConstRegs[i]);
g_psxFlushedConstReg |= 1<<i;
}
@ -542,32 +542,32 @@ void _psxDeleteReg(int reg, int flush)
void _psxMoveGPRtoR(x86IntRegType to, int fromgpr)
{
if( PSX_IS_CONST1(fromgpr) )
MOV32ItoR( to, g_psxConstRegs[fromgpr] );
xMOV(xRegister32(to), g_psxConstRegs[fromgpr] );
else {
// check x86
MOV32MtoR(to, (uptr)&psxRegs.GPR.r[ fromgpr ] );
xMOV(xRegister32(to), ptr[&psxRegs.GPR.r[ fromgpr ] ]);
}
}
void _psxMoveGPRtoM(u32 to, int fromgpr)
{
if( PSX_IS_CONST1(fromgpr) )
MOV32ItoM( to, g_psxConstRegs[fromgpr] );
xMOV(ptr32[(u32*)(to)], g_psxConstRegs[fromgpr] );
else {
// check x86
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[ fromgpr ] );
MOV32RtoM(to, EAX );
xMOV(eax, ptr[&psxRegs.GPR.r[ fromgpr ] ]);
xMOV(ptr[(void*)(to)], eax);
}
}
void _psxMoveGPRtoRm(x86IntRegType to, int fromgpr)
{
if( PSX_IS_CONST1(fromgpr) )
MOV32ItoRm( to, g_psxConstRegs[fromgpr] );
xMOV(ptr32[xAddressReg(to)], g_psxConstRegs[fromgpr] );
else {
// check x86
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[ fromgpr ] );
MOV32RtoRm(to, EAX );
xMOV(eax, ptr[&psxRegs.GPR.r[ fromgpr ] ]);
xMOV(ptr[xAddressReg(to)], eax);
}
}
@ -655,8 +655,8 @@ void psxRecompileCodeConst1(R3000AFNPTR constcode, R3000AFNPTR_INFO noconstcode)
if ( ! _Rt_ ) {
// check for iop module import table magic
if (psxRegs.code >> 16 == 0x2400) {
MOV32ItoM( (uptr)&psxRegs.code, psxRegs.code );
MOV32ItoM( (uptr)&psxRegs.pc, psxpc );
xMOV(ptr32[&psxRegs.code], psxRegs.code );
xMOV(ptr32[&psxRegs.pc], psxpc );
_psxFlushCall(FLUSH_NODESTROY);
const char *libname = irxImportLibname(psxpc);
@ -986,15 +986,15 @@ void psxSetBranchReg(u32 reg)
if( x86regs[ESI].inuse ) {
pxAssert( x86regs[ESI].type == X86TYPE_PCWRITEBACK );
MOV32RtoM((uptr)&psxRegs.pc, ESI);
xMOV(ptr[&psxRegs.pc], esi);
x86regs[ESI].inuse = 0;
#ifdef PCSX2_DEBUG
xOR( esi, esi );
#endif
}
else {
MOV32MtoR(EAX, (uptr)&g_recWriteback);
MOV32RtoM((uptr)&psxRegs.pc, EAX);
xMOV(eax, ptr[&g_recWriteback]);
xMOV(ptr[&psxRegs.pc], eax);
#ifdef PCSX2_DEBUG
xOR( eax, eax );
@ -1020,7 +1020,7 @@ void psxSetBranchImm( u32 imm )
pxAssert( imm );
// end the current block
MOV32ItoM( (uptr)&psxRegs.pc, imm );
xMOV(ptr32[&psxRegs.pc], imm );
_psxFlushCall(FLUSH_EVERYTHING);
iPsxBranchTest(imm, imm <= psxpc);
@ -1105,19 +1105,19 @@ static void checkcodefn()
void rpsxSYSCALL()
{
MOV32ItoM( (uptr)&psxRegs.code, psxRegs.code );
MOV32ItoM((uptr)&psxRegs.pc, psxpc - 4);
xMOV(ptr32[&psxRegs.code], psxRegs.code );
xMOV(ptr32[&psxRegs.pc], psxpc - 4);
_psxFlushCall(FLUSH_NODESTROY);
xMOV( ecx, 0x20 ); // exception code
xMOV( edx, psxbranch==1 ); // branch delay slot?
xCALL( psxException );
CMP32ItoM((uptr)&psxRegs.pc, psxpc-4);
xCMP(ptr32[&psxRegs.pc], psxpc-4);
j8Ptr[0] = JE8(0);
ADD32ItoM((uptr)&psxRegs.cycle, psxScaleBlockCycles() );
SUB32ItoM((uptr)&iopCycleEE, psxScaleBlockCycles()*8 );
xADD(ptr32[&psxRegs.cycle], psxScaleBlockCycles() );
xSUB(ptr32[&iopCycleEE], psxScaleBlockCycles()*8 );
JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr + 5 ));
// jump target for skipping blockCycle updates
@ -1128,18 +1128,18 @@ void rpsxSYSCALL()
void rpsxBREAK()
{
MOV32ItoM( (uptr)&psxRegs.code, psxRegs.code );
MOV32ItoM((uptr)&psxRegs.pc, psxpc - 4);
xMOV(ptr32[&psxRegs.code], psxRegs.code );
xMOV(ptr32[&psxRegs.pc], psxpc - 4);
_psxFlushCall(FLUSH_NODESTROY);
xMOV( ecx, 0x24 ); // exception code
xMOV( edx, psxbranch==1 ); // branch delay slot?
xCALL( psxException );
CMP32ItoM((uptr)&psxRegs.pc, psxpc-4);
xCMP(ptr32[&psxRegs.pc], psxpc-4);
j8Ptr[0] = JE8(0);
ADD32ItoM((uptr)&psxRegs.cycle, psxScaleBlockCycles() );
SUB32ItoM((uptr)&iopCycleEE, psxScaleBlockCycles()*8 );
xADD(ptr32[&psxRegs.cycle], psxScaleBlockCycles() );
xSUB(ptr32[&iopCycleEE], psxScaleBlockCycles()*8 );
JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr + 5 ));
x86SetJ8(j8Ptr[0]);
@ -1154,7 +1154,7 @@ void psxRecompileNextInstruction(int delayslot)
//BASEBLOCK* pblock = PSX_GETBLOCK(psxpc);
if( IsDebugBuild )
MOV32ItoR(EAX, psxpc);
xMOV(eax, psxpc);
psxRegs.code = iopMemRead32( psxpc );
s_psxBlockCycles++;
@ -1393,14 +1393,14 @@ StartRecomp:
if( psxbranch ) pxAssert( !willbranch3 );
else
{
ADD32ItoM((uptr)&psxRegs.cycle, psxScaleBlockCycles() );
SUB32ItoM((uptr)&iopCycleEE, psxScaleBlockCycles()*8 );
xADD(ptr32[&psxRegs.cycle], psxScaleBlockCycles() );
xSUB(ptr32[&iopCycleEE], psxScaleBlockCycles()*8 );
}
if (willbranch3 || !psxbranch) {
pxAssert( psxpc == s_nEndBlock );
_psxFlushCall(FLUSH_EVERYTHING);
MOV32ItoM((uptr)&psxRegs.pc, psxpc);
xMOV(ptr32[&psxRegs.pc], psxpc);
recBlocks.Link(HWADDR(s_nEndBlock), xJcc32() );
psxbranch = 3;
}

454
pcsx2/x86/iR3000Atables.cpp
View File

@ -30,9 +30,9 @@ extern u32 g_psxMaxRecMem;
// R3000A instruction implementation
#define REC_FUNC(f) \
static void rpsx##f() { \
MOV32ItoM((uptr)&psxRegs.code, (u32)psxRegs.code); \
xMOV(ptr32[&psxRegs.code], (u32)psxRegs.code); \
_psxFlushCall(FLUSH_EVERYTHING); \
CALLFunc((uptr)psx##f); \
xCALL((void*)(uptr)psx##f); \
PSX_DEL_CONST(_Rt_); \
/* branch = 2; */\
}
@ -53,15 +53,15 @@ void rpsxADDconst(int dreg, int sreg, u32 off, int info)
{
if (sreg) {
if (sreg == dreg) {
ADD32ItoM((uptr)&psxRegs.GPR.r[dreg], off);
xADD(ptr32[&psxRegs.GPR.r[dreg]], off);
} else {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[sreg]);
if (off) ADD32ItoR(EAX, off);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[sreg]]);
if (off) xADD(eax, off);
xMOV(ptr[&psxRegs.GPR.r[dreg]], eax);
}
}
else {
MOV32ItoM((uptr)&psxRegs.GPR.r[dreg], off);
xMOV(ptr32[&psxRegs.GPR.r[dreg]], off);
}
}
@ -84,10 +84,10 @@ void rpsxSLTI_const()
void rpsxSLTconst(int info, int dreg, int sreg, int imm)
{
XOR32RtoR(EAX, EAX);
CMP32ItoM((uptr)&psxRegs.GPR.r[sreg], imm);
SETL8R(EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], EAX);
xXOR(eax, eax);
xCMP(ptr32[&psxRegs.GPR.r[sreg]], imm);
xSETL(al);
xMOV(ptr[&psxRegs.GPR.r[dreg]], eax);
}
void rpsxSLTI_(int info) { rpsxSLTconst(info, _Rt_, _Rs_, _Imm_); }
@ -102,10 +102,10 @@ void rpsxSLTIU_const()
void rpsxSLTUconst(int info, int dreg, int sreg, int imm)
{
XOR32RtoR(EAX, EAX);
CMP32ItoM((uptr)&psxRegs.GPR.r[sreg], imm);
SETB8R(EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], EAX);
xXOR(eax, eax);
xCMP(ptr32[&psxRegs.GPR.r[sreg]], imm);
xSETB(al);
xMOV(ptr[&psxRegs.GPR.r[dreg]], eax);
}
void rpsxSLTIU_(int info) { rpsxSLTUconst(info, _Rt_, _Rs_, (s32)_Imm_); }
@ -122,14 +122,14 @@ void rpsxANDconst(int info, int dreg, int sreg, u32 imm)
{
if (imm) {
if (sreg == dreg) {
AND32ItoM((uptr)&psxRegs.GPR.r[dreg], imm);
xAND(ptr32[&psxRegs.GPR.r[dreg]], imm);
} else {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[sreg]);
AND32ItoR(EAX, imm);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[sreg]]);
xAND(eax, imm);
xMOV(ptr[&psxRegs.GPR.r[dreg]], eax);
}
} else {
MOV32ItoM((uptr)&psxRegs.GPR.r[dreg], 0);
xMOV(ptr32[&psxRegs.GPR.r[dreg]], 0);
}
}
@ -147,18 +147,18 @@ void rpsxORconst(int info, int dreg, int sreg, u32 imm)
{
if (imm) {
if (sreg == dreg) {
OR32ItoM((uptr)&psxRegs.GPR.r[dreg], imm);
xOR(ptr32[&psxRegs.GPR.r[dreg]], imm);
}
else {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[sreg]);
OR32ItoR (EAX, imm);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[sreg]]);
xOR(eax, imm);
xMOV(ptr[&psxRegs.GPR.r[dreg]], eax);
}
}
else {
if( dreg != sreg ) {
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[sreg]);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], ECX);
xMOV(ecx, ptr[&psxRegs.GPR.r[sreg]]);
xMOV(ptr[&psxRegs.GPR.r[dreg]], ecx);
}
}
}
@ -176,29 +176,29 @@ void rpsxXORconst(int info, int dreg, int sreg, u32 imm)
{
if( imm == 0xffffffff ) {
if( dreg == sreg ) {
NOT32M((uptr)&psxRegs.GPR.r[dreg]);
xNOT(ptr32[&psxRegs.GPR.r[dreg]]);
}
else {
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[sreg]);
NOT32R(ECX);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], ECX);
xMOV(ecx, ptr[&psxRegs.GPR.r[sreg]]);
xNOT(ecx);
xMOV(ptr[&psxRegs.GPR.r[dreg]], ecx);
}
}
else if (imm) {
if (sreg == dreg) {
XOR32ItoM((uptr)&psxRegs.GPR.r[dreg], imm);
xXOR(ptr32[&psxRegs.GPR.r[dreg]], imm);
}
else {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[sreg]);
XOR32ItoR(EAX, imm);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[sreg]]);
xXOR(eax, imm);
xMOV(ptr[&psxRegs.GPR.r[dreg]], eax);
}
}
else {
if( dreg != sreg ) {
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[sreg]);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], ECX);
xMOV(ecx, ptr[&psxRegs.GPR.r[sreg]]);
xMOV(ptr[&psxRegs.GPR.r[dreg]], ecx);
}
}
}
@ -231,16 +231,16 @@ void rpsxADDU_constt(int info)
void rpsxADDU_(int info)
{
if (_Rs_ && _Rt_) {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rs_]);
ADD32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
xADD(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
} else if (_Rs_) {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rs_]);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
} else if (_Rt_) {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
} else {
XOR32RtoR(EAX, EAX);
xXOR(eax, eax);
}
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
PSXRECOMPILE_CONSTCODE0(ADDU);
@ -255,9 +255,9 @@ void rpsxSUBU_const()
void rpsxSUBU_consts(int info)
{
MOV32ItoR(EAX, g_psxConstRegs[_Rs_]);
SUB32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(eax, g_psxConstRegs[_Rs_]);
xSUB(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
void rpsxSUBU_constt(int info) { rpsxADDconst(_Rd_, _Rs_, -(int)g_psxConstRegs[_Rt_], info); }
@ -268,13 +268,13 @@ void rpsxSUBU_(int info)
if (!_Rd_) return;
if( _Rd_ == _Rs_ ) {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
SUB32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
xSUB(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
else {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rs_]);
SUB32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
xSUB(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
}
@ -286,17 +286,17 @@ void rpsxLogicalOp(int info, int op)
{
if( _Rd_ == _Rs_ || _Rd_ == _Rt_ ) {
int vreg = _Rd_ == _Rs_ ? _Rt_ : _Rs_;
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[vreg]);
xMOV(ecx, ptr[&psxRegs.GPR.r[vreg]]);
LogicalOp32RtoM((uptr)&psxRegs.GPR.r[_Rd_], ECX, op);
if( op == 3 )
NOT32M((uptr)&psxRegs.GPR.r[_Rd_]);
xNOT(ptr32[&psxRegs.GPR.r[_Rd_]]);
}
else {
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
LogicalOp32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rt_], op);
if( op == 3 )
NOT32R(ECX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], ECX);
xNOT(ecx);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], ecx);
}
}
@ -344,24 +344,24 @@ void rpsxNORconst(int info, int dreg, int sreg, u32 imm)
{
if( imm ) {
if( dreg == sreg ) {
OR32ItoM((uptr)&psxRegs.GPR.r[dreg], imm);
NOT32M((uptr)&psxRegs.GPR.r[dreg]);
xOR(ptr32[&psxRegs.GPR.r[dreg]], imm);
xNOT(ptr32[&psxRegs.GPR.r[dreg]]);
}
else {
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[sreg]);
OR32ItoR(ECX, imm);
NOT32R(ECX);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], ECX);
xMOV(ecx, ptr[&psxRegs.GPR.r[sreg]]);
xOR(ecx, imm);
xNOT(ecx);
xMOV(ptr[&psxRegs.GPR.r[dreg]], ecx);
}
}
else {
if( dreg == sreg ) {
NOT32M((uptr)&psxRegs.GPR.r[dreg]);
xNOT(ptr32[&psxRegs.GPR.r[dreg]]);
}
else {
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[sreg]);
NOT32R(ECX);
MOV32RtoM((uptr)&psxRegs.GPR.r[dreg], ECX);
xMOV(ecx, ptr[&psxRegs.GPR.r[sreg]]);
xNOT(ecx);
xMOV(ptr[&psxRegs.GPR.r[dreg]], ecx);
}
}
}
@ -380,20 +380,20 @@ void rpsxSLT_const()
void rpsxSLT_consts(int info)
{
XOR32RtoR(EAX, EAX);
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rt_], g_psxConstRegs[_Rs_]);
SETG8R(EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xXOR(eax, eax);
xCMP(ptr32[&psxRegs.GPR.r[_Rt_]], g_psxConstRegs[_Rs_]);
xSETG(al);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
void rpsxSLT_constt(int info) { rpsxSLTconst(info, _Rd_, _Rs_, g_psxConstRegs[_Rt_]); }
void rpsxSLT_(int info)
{
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rs_]);
CMP32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
SETL8R (EAX);
AND32ItoR(EAX, 0xff);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
xCMP(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
xSETL(al);
xAND(eax, 0xff);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
PSXRECOMPILE_CONSTCODE0(SLT);
@ -406,10 +406,10 @@ void rpsxSLTU_const()
void rpsxSLTU_consts(int info)
{
XOR32RtoR(EAX, EAX);
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rt_], g_psxConstRegs[_Rs_]);
SETA8R(EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xXOR(eax, eax);
xCMP(ptr32[&psxRegs.GPR.r[_Rt_]], g_psxConstRegs[_Rs_]);
xSETA(al);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
void rpsxSLTU_constt(int info) { rpsxSLTUconst(info, _Rd_, _Rs_, g_psxConstRegs[_Rt_]); }
@ -418,11 +418,11 @@ void rpsxSLTU_(int info)
// Rd = Rs < Rt (unsigned)
if (!_Rd_) return;
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rs_]);
CMP32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
SBB32RtoR(EAX, EAX);
NEG32R (EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
xCMP(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
xSBB(eax, eax);
xNEG(eax);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
PSXRECOMPILE_CONSTCODE0(SLTU);
@ -432,28 +432,28 @@ void rpsxMULT_const()
{
u64 res = (s64)((s64)*(int*)&g_psxConstRegs[_Rs_] * (s64)*(int*)&g_psxConstRegs[_Rt_]);
MOV32ItoM((uptr)&psxRegs.GPR.n.hi, (u32)((res >> 32) & 0xffffffff));
MOV32ItoM((uptr)&psxRegs.GPR.n.lo, (u32)(res & 0xffffffff));
xMOV(ptr32[&psxRegs.GPR.n.hi], (u32)((res >> 32) & 0xffffffff));
xMOV(ptr32[&psxRegs.GPR.n.lo], (u32)(res & 0xffffffff));
}
void rpsxMULTsuperconst(int info, int sreg, int imm, int sign)
{
// Lo/Hi = Rs * Rt (signed)
MOV32ItoR(EAX, imm);
if( sign ) IMUL32M ((uptr)&psxRegs.GPR.r[sreg]);
else MUL32M ((uptr)&psxRegs.GPR.r[sreg]);
MOV32RtoM((uptr)&psxRegs.GPR.n.lo, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.n.hi, EDX);
xMOV(eax, imm);
if( sign ) xMUL(ptr32[&psxRegs.GPR.r[sreg]]);
else xUMUL(ptr32[&psxRegs.GPR.r[sreg]]);
xMOV(ptr[&psxRegs.GPR.n.lo], eax);
xMOV(ptr[&psxRegs.GPR.n.hi], edx);
}
void rpsxMULTsuper(int info, int sign)
{
// Lo/Hi = Rs * Rt (signed)
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rs_]);
if( sign ) IMUL32M ((uptr)&psxRegs.GPR.r[_Rt_]);
else MUL32M ((uptr)&psxRegs.GPR.r[_Rt_]);
MOV32RtoM((uptr)&psxRegs.GPR.n.lo, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.n.hi, EDX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
if( sign ) xMUL(ptr32[&psxRegs.GPR.r[_Rt_]]);
else xUMUL(ptr32[&psxRegs.GPR.r[_Rt_]]);
xMOV(ptr[&psxRegs.GPR.n.lo], eax);
xMOV(ptr[&psxRegs.GPR.n.hi], edx);
}
void rpsxMULT_consts(int info) { rpsxMULTsuperconst(info, _Rt_, g_psxConstRegs[_Rs_], 1); }
@ -467,8 +467,8 @@ void rpsxMULTU_const()
{
u64 res = (u64)((u64)g_psxConstRegs[_Rs_] * (u64)g_psxConstRegs[_Rt_]);
MOV32ItoM((uptr)&psxRegs.GPR.n.hi, (u32)((res >> 32) & 0xffffffff));
MOV32ItoM((uptr)&psxRegs.GPR.n.lo, (u32)(res & 0xffffffff));
xMOV(ptr32[&psxRegs.GPR.n.hi], (u32)((res >> 32) & 0xffffffff));
xMOV(ptr32[&psxRegs.GPR.n.lo], (u32)(res & 0xffffffff));
}
void rpsxMULTU_consts(int info) { rpsxMULTsuperconst(info, _Rt_, g_psxConstRegs[_Rs_], 0); }
@ -485,8 +485,8 @@ void rpsxDIV_const()
if (g_psxConstRegs[_Rt_] != 0) {
lo = *(int*)&g_psxConstRegs[_Rs_] / *(int*)&g_psxConstRegs[_Rt_];
hi = *(int*)&g_psxConstRegs[_Rs_] % *(int*)&g_psxConstRegs[_Rt_];
MOV32ItoM((uptr)&psxRegs.GPR.n.hi, hi);
MOV32ItoM((uptr)&psxRegs.GPR.n.lo, lo);
xMOV(ptr32[&psxRegs.GPR.n.hi], hi);
xMOV(ptr32[&psxRegs.GPR.n.lo], lo);
}
}
@ -496,30 +496,30 @@ void rpsxDIVsuperconsts(int info, int sign)
if( imm ) {
// Lo/Hi = Rs / Rt (signed)
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rt_]);
CMP32ItoR(ECX, 0);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rt_]]);
xCMP(ecx, 0);
j8Ptr[0] = JE8(0);
MOV32ItoR(EAX, imm);
xMOV(eax, imm);
if( sign ) {
CDQ();
IDIV32R (ECX);
xCDQ();
xDIV(ecx);
}
else {
XOR32RtoR( EDX, EDX );
DIV32R(ECX);
xXOR(edx, edx);
xUDIV(ecx);
}
MOV32RtoM((uptr)&psxRegs.GPR.n.lo, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.n.hi, EDX);
xMOV(ptr[&psxRegs.GPR.n.lo], eax);
xMOV(ptr[&psxRegs.GPR.n.hi], edx);
x86SetJ8(j8Ptr[0]);
}
else {
XOR32RtoR(EAX, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.n.hi, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.n.lo, EAX);
xXOR(eax, eax);
xMOV(ptr[&psxRegs.GPR.n.hi], eax);
xMOV(ptr[&psxRegs.GPR.n.lo], eax);
}
}
@ -528,44 +528,44 @@ void rpsxDIVsuperconstt(int info, int sign)
u32 imm = g_psxConstRegs[_Rt_];
if( imm ) {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rs_]);
MOV32ItoR(ECX, imm);
//CDQ();
xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
xMOV(ecx, imm);
//xCDQ();
if( sign ) {
CDQ();
IDIV32R (ECX);
xCDQ();
xDIV(ecx);
}
else {
XOR32RtoR( EDX, EDX );
DIV32R(ECX);
xXOR(edx, edx);
xUDIV(ecx);
}
MOV32RtoM((uptr)&psxRegs.GPR.n.lo, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.n.hi, EDX);
xMOV(ptr[&psxRegs.GPR.n.lo], eax);
xMOV(ptr[&psxRegs.GPR.n.hi], edx);
}
}
void rpsxDIVsuper(int info, int sign)
{
// Lo/Hi = Rs / Rt (signed)
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rt_]);
CMP32ItoR(ECX, 0);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rt_]]);
xCMP(ecx, 0);
j8Ptr[0] = JE8(0);
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rs_]);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
if( sign ) {
CDQ();
IDIV32R (ECX);
xCDQ();
xDIV(ecx);
}
else {
XOR32RtoR( EDX, EDX );
DIV32R(ECX);
xXOR(edx, edx);
xUDIV(ecx);
}
MOV32RtoM((uptr)&psxRegs.GPR.n.lo, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.n.hi, EDX);
xMOV(ptr[&psxRegs.GPR.n.lo], eax);
xMOV(ptr[&psxRegs.GPR.n.hi], edx);
x86SetJ8(j8Ptr[0]);
}
@ -583,8 +583,8 @@ void rpsxDIVU_const()
if (g_psxConstRegs[_Rt_] != 0) {
lo = g_psxConstRegs[_Rs_] / g_psxConstRegs[_Rt_];
hi = g_psxConstRegs[_Rs_] % g_psxConstRegs[_Rt_];
MOV32ItoM((uptr)&psxRegs.GPR.n.hi, hi);
MOV32ItoM((uptr)&psxRegs.GPR.n.lo, lo);
xMOV(ptr32[&psxRegs.GPR.n.hi], hi);
xMOV(ptr32[&psxRegs.GPR.n.lo], lo);
}
}
@ -608,12 +608,12 @@ static void rpsxLB()
_psxOnWriteReg(_Rt_);
_psxDeleteReg(_Rt_, 0);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
if (_Imm_) ADD32ItoR(ECX, _Imm_);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
if (_Imm_) xADD(ecx, _Imm_);
xCALL( iopMemRead8 ); // returns value in EAX
if (_Rt_) {
MOVSX32R8toR(EAX, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rt_], EAX);
xMOVSX(eax, al);
xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
}
PSX_DEL_CONST(_Rt_);
}
@ -624,12 +624,12 @@ static void rpsxLBU()
_psxOnWriteReg(_Rt_);
_psxDeleteReg(_Rt_, 0);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
if (_Imm_) ADD32ItoR(ECX, _Imm_);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
if (_Imm_) xADD(ecx, _Imm_);
xCALL( iopMemRead8 ); // returns value in EAX
if (_Rt_) {
MOVZX32R8toR(EAX, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rt_], EAX);
xMOVZX(eax, al);
xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
}
PSX_DEL_CONST(_Rt_);
}
@ -640,12 +640,12 @@ static void rpsxLH()
_psxOnWriteReg(_Rt_);
_psxDeleteReg(_Rt_, 0);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
if (_Imm_) ADD32ItoR(ECX, _Imm_);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
if (_Imm_) xADD(ecx, _Imm_);
xCALL( iopMemRead16 ); // returns value in EAX
if (_Rt_) {
MOVSX32R16toR(EAX, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rt_], EAX);
xMOVSX(eax, ax);
xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
}
PSX_DEL_CONST(_Rt_);
}
@ -656,12 +656,12 @@ static void rpsxLHU()
_psxOnWriteReg(_Rt_);
_psxDeleteReg(_Rt_, 0);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
if (_Imm_) ADD32ItoR(ECX, _Imm_);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
if (_Imm_) xADD(ecx, _Imm_);
xCALL( iopMemRead16 ); // returns value in EAX
if (_Rt_) {
MOVZX32R16toR(EAX, EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rt_], EAX);
xMOVZX(eax, ax);
xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
}
PSX_DEL_CONST(_Rt_);
}
@ -673,25 +673,25 @@ static void rpsxLW()
_psxDeleteReg(_Rt_, 0);
_psxFlushCall(FLUSH_EVERYTHING);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
if (_Imm_) ADD32ItoR(ECX, _Imm_);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
if (_Imm_) xADD(ecx, _Imm_);
TEST32ItoR(ECX, 0x10000000);
xTEST(ecx, 0x10000000);
j8Ptr[0] = JZ8(0);
xCALL( iopMemRead32 ); // returns value in EAX
if (_Rt_) {
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rt_], EAX);
xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
}
j8Ptr[1] = JMP8(0);
x86SetJ8(j8Ptr[0]);
// read from psM directly
AND32ItoR(ECX, 0x1fffff);
ADD32ItoR(ECX, (uptr)iopMem->Main);
xAND(ecx, 0x1fffff);
xADD(ecx, (uptr)iopMem->Main);
MOV32RmtoR( ECX, ECX );
MOV32RtoM( (uptr)&psxRegs.GPR.r[_Rt_], ECX);
xMOV(ecx, ptr[xAddressReg(ECX )]);
xMOV(ptr[&psxRegs.GPR.r[_Rt_]], ecx);
x86SetJ8(j8Ptr[1]);
PSX_DEL_CONST(_Rt_);
@ -702,8 +702,8 @@ static void rpsxSB()
_psxDeleteReg(_Rs_, 1);
_psxDeleteReg(_Rt_, 1);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
if (_Imm_) ADD32ItoR(ECX, _Imm_);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
if (_Imm_) xADD(ecx, _Imm_);
xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] );
xCALL( iopMemWrite8 );
}
@ -713,8 +713,8 @@ static void rpsxSH()
_psxDeleteReg(_Rs_, 1);
_psxDeleteReg(_Rt_, 1);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
if (_Imm_) ADD32ItoR(ECX, _Imm_);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
if (_Imm_) xADD(ecx, _Imm_);
xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] );
xCALL( iopMemWrite16 );
}
@ -724,8 +724,8 @@ static void rpsxSW()
_psxDeleteReg(_Rs_, 1);
_psxDeleteReg(_Rt_, 1);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
if (_Imm_) ADD32ItoR(ECX, _Imm_);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
if (_Imm_) xADD(ecx, _Imm_);
xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] );
xCALL( iopMemWrite32 );
}
@ -743,25 +743,25 @@ void rpsxShiftConst(int info, int rdreg, int rtreg, int imm, int shifttype)
if (imm) {
if( rdreg == rtreg ) {
switch(shifttype) {
case 0: SHL32ItoM((uptr)&psxRegs.GPR.r[rdreg], imm); break;
case 1: SHR32ItoM((uptr)&psxRegs.GPR.r[rdreg], imm); break;
case 2: SAR32ItoM((uptr)&psxRegs.GPR.r[rdreg], imm); break;
case 0: xSHL(ptr32[&psxRegs.GPR.r[rdreg]], imm); break;
case 1: xSHR(ptr32[&psxRegs.GPR.r[rdreg]], imm); break;
case 2: xSAR(ptr32[&psxRegs.GPR.r[rdreg]], imm); break;
}
}
else {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[rtreg]);
xMOV(eax, ptr[&psxRegs.GPR.r[rtreg]]);
switch(shifttype) {
case 0: SHL32ItoR(EAX, imm); break;
case 1: SHR32ItoR(EAX, imm); break;
case 2: SAR32ItoR(EAX, imm); break;
case 0: xSHL(eax, imm); break;
case 1: xSHR(eax, imm); break;
case 2: xSAR(eax, imm); break;
}
MOV32RtoM((uptr)&psxRegs.GPR.r[rdreg], EAX);
xMOV(ptr[&psxRegs.GPR.r[rdreg]], eax);
}
}
else {
if( rdreg != rtreg ) {
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[rtreg]);
MOV32RtoM((uptr)&psxRegs.GPR.r[rdreg], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[rtreg]]);
xMOV(ptr[&psxRegs.GPR.r[rdreg]], eax);
}
}
}
@ -800,24 +800,24 @@ void rpsxShiftVconsts(int info, int shifttype)
void rpsxShiftVconstt(int info, int shifttype)
{
MOV32ItoR(EAX, g_psxConstRegs[_Rt_]);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
xMOV(eax, g_psxConstRegs[_Rt_]);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
switch(shifttype) {
case 0: SHL32CLtoR(EAX); break;
case 1: SHR32CLtoR(EAX); break;
case 2: SAR32CLtoR(EAX); break;
case 0: xSHL(eax, cl); break;
case 1: xSHR(eax, cl); break;
case 2: xSAR(eax, cl); break;
}
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
void rpsxSLLV_consts(int info) { rpsxShiftVconsts(info, 0); }
void rpsxSLLV_constt(int info) { rpsxShiftVconstt(info, 0); }
void rpsxSLLV_(int info)
{
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
SHL32CLtoR(EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
xSHL(eax, cl);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
PSXRECOMPILE_CONSTCODE0(SLLV);
@ -832,10 +832,10 @@ void rpsxSRLV_consts(int info) { rpsxShiftVconsts(info, 1); }
void rpsxSRLV_constt(int info) { rpsxShiftVconstt(info, 1); }
void rpsxSRLV_(int info)
{
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
SHR32CLtoR(EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
xSHR(eax, cl);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
PSXRECOMPILE_CONSTCODE0(SRLV);
@ -850,10 +850,10 @@ void rpsxSRAV_consts(int info) { rpsxShiftVconsts(info, 2); }
void rpsxSRAV_constt(int info) { rpsxShiftVconstt(info, 2); }
void rpsxSRAV_(int info)
{
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
MOV32MtoR(ECX, (uptr)&psxRegs.GPR.r[_Rs_]);
SAR32CLtoR(EAX);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
xSAR(eax, cl);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
PSXRECOMPILE_CONSTCODE0(SRAV);
@ -867,19 +867,19 @@ void rpsxMFHI()
_psxOnWriteReg(_Rd_);
_psxDeleteReg(_Rd_, 0);
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.n.hi);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(eax, ptr[&psxRegs.GPR.n.hi]);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
void rpsxMTHI()
{
if( PSX_IS_CONST1(_Rs_) ) {
MOV32ItoM((uptr)&psxRegs.GPR.n.hi, g_psxConstRegs[_Rs_]);
xMOV(ptr32[&psxRegs.GPR.n.hi], g_psxConstRegs[_Rs_]);
}
else {
_psxDeleteReg(_Rs_, 1);
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rs_]);
MOV32RtoM((uptr)&psxRegs.GPR.n.hi, EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
xMOV(ptr[&psxRegs.GPR.n.hi], eax);
}
}
@ -889,19 +889,19 @@ void rpsxMFLO()
_psxOnWriteReg(_Rd_);
_psxDeleteReg(_Rd_, 0);
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.n.lo);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rd_], EAX);
xMOV(eax, ptr[&psxRegs.GPR.n.lo]);
xMOV(ptr[&psxRegs.GPR.r[_Rd_]], eax);
}
void rpsxMTLO()
{
if( PSX_IS_CONST1(_Rs_) ) {
MOV32ItoM((uptr)&psxRegs.GPR.n.hi, g_psxConstRegs[_Rs_]);
xMOV(ptr32[&psxRegs.GPR.n.hi], g_psxConstRegs[_Rs_]);
}
else {
_psxDeleteReg(_Rs_, 1);
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rs_]);
MOV32RtoM((uptr)&psxRegs.GPR.n.lo, EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rs_]]);
xMOV(ptr[&psxRegs.GPR.n.lo], eax);
}
}
@ -946,7 +946,7 @@ void rpsxJALR()
if( x86regs[ESI].inuse ) {
pxAssert( x86regs[ESI].type == X86TYPE_PCWRITEBACK );
MOV32RtoM((uptr)&psxRegs.pc, ESI);
xMOV(ptr[&psxRegs.pc], esi);
x86regs[ESI].inuse = 0;
#ifdef PCSX2_DEBUG
xOR( esi, esi );
@ -954,8 +954,8 @@ void rpsxJALR()
}
else {
MOV32MtoR(EAX, (uptr)&g_recWriteback);
MOV32RtoM((uptr)&psxRegs.pc, EAX);
xMOV(eax, ptr[&g_recWriteback]);
xMOV(ptr[&psxRegs.pc], eax);
#ifdef PCSX2_DEBUG
xOR( eax, eax );
#endif
@ -975,16 +975,16 @@ static u32* s_pbranchjmp;
void rpsxSetBranchEQ(int info, int process)
{
if( process & PROCESS_CONSTS ) {
CMP32ItoM( (uptr)&psxRegs.GPR.r[ _Rt_ ], g_psxConstRegs[_Rs_] );
xCMP(ptr32[&psxRegs.GPR.r[ _Rt_ ]], g_psxConstRegs[_Rs_] );
s_pbranchjmp = JNE32( 0 );
}
else if( process & PROCESS_CONSTT ) {
CMP32ItoM( (uptr)&psxRegs.GPR.r[ _Rs_ ], g_psxConstRegs[_Rt_] );
xCMP(ptr32[&psxRegs.GPR.r[ _Rs_ ]], g_psxConstRegs[_Rt_] );
s_pbranchjmp = JNE32( 0 );
}
else {
MOV32MtoR( EAX, (uptr)&psxRegs.GPR.r[ _Rs_ ] );
CMP32MtoR( EAX, (uptr)&psxRegs.GPR.r[ _Rt_ ] );
xMOV(eax, ptr[&psxRegs.GPR.r[ _Rs_ ] ]);
xCMP(eax, ptr[&psxRegs.GPR.r[ _Rt_ ] ]);
s_pbranchjmp = JNE32( 0 );
}
}
@ -1101,7 +1101,7 @@ void rpsxBLTZ()
return;
}
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
xCMP(ptr32[&psxRegs.GPR.r[_Rs_]], 0);
u32* pjmp = JL32(0);
psxSaveBranchState();
@ -1135,7 +1135,7 @@ void rpsxBGEZ()
return;
}
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
xCMP(ptr32[&psxRegs.GPR.r[_Rs_]], 0);
u32* pjmp = JGE32(0);
psxSaveBranchState();
@ -1175,7 +1175,7 @@ void rpsxBLTZAL()
return;
}
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
xCMP(ptr32[&psxRegs.GPR.r[_Rs_]], 0);
u32* pjmp = JL32(0);
psxSaveBranchState();
@ -1215,7 +1215,7 @@ void rpsxBGEZAL()
return;
}
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
xCMP(ptr32[&psxRegs.GPR.r[_Rs_]], 0);
u32* pjmp = JGE32(0);
psxSaveBranchState();
@ -1253,7 +1253,7 @@ void rpsxBLEZ()
_psxDeleteReg(_Rs_, 1);
_clearNeededX86regs();
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
xCMP(ptr32[&psxRegs.GPR.r[_Rs_]], 0);
u32* pjmp = JLE32(0);
psxSaveBranchState();
@ -1288,7 +1288,7 @@ void rpsxBGTZ()
_psxDeleteReg(_Rs_, 1);
_clearNeededX86regs();
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
xCMP(ptr32[&psxRegs.GPR.r[_Rs_]], 0);
u32* pjmp = JG32(0);
psxSaveBranchState();
@ -1309,8 +1309,8 @@ void rpsxMFC0()
if (!_Rt_) return;
_psxOnWriteReg(_Rt_);
MOV32MtoR(EAX, (uptr)&psxRegs.CP0.r[_Rd_]);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rt_], EAX);
xMOV(eax, ptr[&psxRegs.CP0.r[_Rd_]]);
xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
}
void rpsxCFC0()
@ -1319,20 +1319,20 @@ void rpsxCFC0()
if (!_Rt_) return;
_psxOnWriteReg(_Rt_);
MOV32MtoR(EAX, (uptr)&psxRegs.CP0.r[_Rd_]);
MOV32RtoM((uptr)&psxRegs.GPR.r[_Rt_], EAX);
xMOV(eax, ptr[&psxRegs.CP0.r[_Rd_]]);
xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
}
void rpsxMTC0()
{
// Cop0->Rd = Rt
if( PSX_IS_CONST1(_Rt_) ) {
MOV32ItoM((uptr)&psxRegs.CP0.r[_Rd_], g_psxConstRegs[_Rt_]);
xMOV(ptr32[&psxRegs.CP0.r[_Rd_]], g_psxConstRegs[_Rt_]);
}
else {
_psxDeleteReg(_Rt_, 1);
MOV32MtoR(EAX, (uptr)&psxRegs.GPR.r[_Rt_]);
MOV32RtoM((uptr)&psxRegs.CP0.r[_Rd_], EAX);
xMOV(eax, ptr[&psxRegs.GPR.r[_Rt_]]);
xMOV(ptr[&psxRegs.CP0.r[_Rd_]], eax);
}
}
@ -1344,18 +1344,18 @@ void rpsxCTC0()
void rpsxRFE()
{
MOV32MtoR(EAX, (uptr)&psxRegs.CP0.n.Status);
MOV32RtoR(ECX, EAX);
AND32ItoR(EAX, 0xfffffff0);
AND32ItoR(ECX, 0x3c);
SHR32ItoR(ECX, 2);
OR32RtoR (EAX, ECX);
MOV32RtoM((uptr)&psxRegs.CP0.n.Status, EAX);
xMOV(eax, ptr[&psxRegs.CP0.n.Status]);
xMOV(ecx, eax);
xAND(eax, 0xfffffff0);
xAND(ecx, 0x3c);
xSHR(ecx, 2);
xOR(eax, ecx);
xMOV(ptr[&psxRegs.CP0.n.Status], eax);
// Test the IOP's INTC status, so that any pending ints get raised.
_psxFlushCall(0);
CALLFunc( (uptr)&iopTestIntc );
xCALL((void*)(uptr)&iopTestIntc );
}
// R3000A tables

56
pcsx2/x86/iR5900Misc.cpp
View File

@ -68,15 +68,15 @@ namespace OpcodeImpl {
////////////////////////////////////////////////////
//static void recCACHE() {
// MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code );
// MOV32ItoM( (uptr)&cpuRegs.pc, pc );
// xMOV(ptr32[&cpuRegs.code], cpuRegs.code );
// xMOV(ptr32[&cpuRegs.pc], pc );
// iFlushCall(FLUSH_EVERYTHING);
// CALLFunc( (uptr)CACHE );
// xCALL((void*)(uptr)CACHE );
// //branch = 2;
//
// CMP32ItoM((int)&cpuRegs.pc, pc);
// xCMP(ptr32[(u32*)((int)&cpuRegs.pc)], pc);
// j8Ptr[0] = JE8(0);
// RET();
// xRET();
// x86SetJ8(j8Ptr[0]);
//}
@ -96,17 +96,17 @@ void recMFSA()
mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_WRITE);
if( mmreg >= 0 ) {
SSE_MOVLPS_M64_to_XMM(mmreg, (uptr)&cpuRegs.sa);
xMOVL.PS(xRegisterSSE(mmreg), ptr[&cpuRegs.sa]);
}
else if( (mmreg = _checkMMXreg(MMX_GPR+_Rd_, MODE_WRITE)) >= 0 ) {
MOVDMtoMMX(mmreg, (uptr)&cpuRegs.sa);
xMOVDZX(xRegisterMMX(mmreg), ptr[&cpuRegs.sa]);
SetMMXstate();
}
else {
MOV32MtoR(EAX, (uptr)&cpuRegs.sa);
xMOV(eax, ptr[&cpuRegs.sa]);
_deleteEEreg(_Rd_, 0);
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rd_].UL[0], EAX);
MOV32ItoM((uptr)&cpuRegs.GPR.r[_Rd_].UL[1], 0);
xMOV(ptr[&cpuRegs.GPR.r[_Rd_].UL[0]], eax);
xMOV(ptr32[&cpuRegs.GPR.r[_Rd_].UL[1]], 0);
}
}
@ -114,50 +114,50 @@ void recMFSA()
void recMTSA()
{
if( GPR_IS_CONST1(_Rs_) ) {
MOV32ItoM((uptr)&cpuRegs.sa, g_cpuConstRegs[_Rs_].UL[0] & 0xf );
xMOV(ptr32[&cpuRegs.sa], g_cpuConstRegs[_Rs_].UL[0] & 0xf );
}
else {
int mmreg;
if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ)) >= 0 ) {
SSE_MOVSS_XMM_to_M32((uptr)&cpuRegs.sa, mmreg);
xMOVSS(ptr[&cpuRegs.sa], xRegisterSSE(mmreg));
}
else if( (mmreg = _checkMMXreg(MMX_GPR+_Rs_, MODE_READ)) >= 0 ) {
MOVDMMXtoM((uptr)&cpuRegs.sa, mmreg);
xMOVD(ptr[&cpuRegs.sa], xRegisterMMX(mmreg));
SetMMXstate();
}
else {
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[_Rs_].UL[0]);
MOV32RtoM((uptr)&cpuRegs.sa, EAX);
xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
xMOV(ptr[&cpuRegs.sa], eax);
}
AND32ItoM((uptr)&cpuRegs.sa, 0xf);
xAND(ptr32[&cpuRegs.sa], 0xf);
}
}
void recMTSAB()
{
if( GPR_IS_CONST1(_Rs_) ) {
MOV32ItoM((uptr)&cpuRegs.sa, ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) );
xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) );
}
else {
_eeMoveGPRtoR(EAX, _Rs_);
AND32ItoR(EAX, 0xF);
XOR32ItoR(EAX, _Imm_&0xf);
MOV32RtoM((uptr)&cpuRegs.sa, EAX);
xAND(eax, 0xF);
xXOR(eax, _Imm_&0xf);
xMOV(ptr[&cpuRegs.sa], eax);
}
}
void recMTSAH()
{
if( GPR_IS_CONST1(_Rs_) ) {
MOV32ItoM((uptr)&cpuRegs.sa, ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1);
xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1);
}
else {
_eeMoveGPRtoR(EAX, _Rs_);
AND32ItoR(EAX, 0x7);
XOR32ItoR(EAX, _Imm_&0x7);
SHL32ItoR(EAX, 1);
MOV32RtoM((uptr)&cpuRegs.sa, EAX);
xAND(eax, 0x7);
xXOR(eax, _Imm_&0x7);
xSHL(eax, 1);
xMOV(ptr[&cpuRegs.sa], eax);
}
}
@ -200,10 +200,10 @@ void recMTSAH()
// Suikoden 3 uses it a lot
void recCACHE() //Interpreter only!
{
//MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code );
//MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc );
//xMOV(ptr32[&cpuRegs.code], (u32)cpuRegs.code );
//xMOV(ptr32[&cpuRegs.pc], (u32)pc );
//iFlushCall(FLUSH_EVERYTHING);
//CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::CACHE );
//xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::CACHE );
//branch = 2;
}

168
pcsx2/x86/ix86-32/iCore-32.cpp
View File

@ -169,8 +169,8 @@ void _flushCachedRegs()
void _flushConstReg(int reg)
{
if( GPR_IS_CONST1( reg ) && !(g_cpuFlushedConstReg&(1<<reg)) ) {
MOV32ItoM((uptr)&cpuRegs.GPR.r[reg].UL[0], g_cpuConstRegs[reg].UL[0]);
MOV32ItoM((uptr)&cpuRegs.GPR.r[reg].UL[1], g_cpuConstRegs[reg].UL[1]);
xMOV(ptr32[&cpuRegs.GPR.r[reg].UL[0]], g_cpuConstRegs[reg].UL[0]);
xMOV(ptr32[&cpuRegs.GPR.r[reg].UL[1]], g_cpuConstRegs[reg].UL[1]);
g_cpuFlushedConstReg |= (1<<reg);
if (reg == 0) DevCon.Warning("Flushing r0!");
}
@ -192,11 +192,11 @@ void _flushConstRegs()
if (g_cpuConstRegs[i].SL[j] != 0) continue;
if (eaxval != 0) {
XOR32RtoR(EAX, EAX);
xXOR(eax, eax);
eaxval = 0;
}
MOV32RtoM((uptr)&cpuRegs.GPR.r[i].SL[j], EAX);
xMOV(ptr[&cpuRegs.GPR.r[i].SL[j]], eax);
done[j] |= 1<<i;
zero_cnt++;
}
@ -208,15 +208,15 @@ void _flushConstRegs()
if (g_cpuConstRegs[i].SL[j] != -1) continue;
if (eaxval > 0) {
XOR32RtoR(EAX, EAX);
xXOR(eax, eax);
eaxval = 0;
}
if (eaxval == 0) {
NOT32R(EAX);
xNOT(eax);
eaxval = -1;
}
MOV32RtoM((uptr)&cpuRegs.GPR.r[i].SL[j], EAX);
xMOV(ptr[&cpuRegs.GPR.r[i].SL[j]], eax);
done[j + 2] |= 1<<i;
minusone_cnt++;
}
@ -232,9 +232,9 @@ void _flushConstRegs()
if (GPR_IS_CONST1(i)) {
if (!(g_cpuFlushedConstReg&(1<<i))) {
if (!(done[0] & (1<<i)))
MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[0], g_cpuConstRegs[i].UL[0]);
xMOV(ptr32[&cpuRegs.GPR.r[i].UL[0]], g_cpuConstRegs[i].UL[0]);
if (!(done[1] & (1<<i)))
MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[1], g_cpuConstRegs[i].UL[1]);
xMOV(ptr32[&cpuRegs.GPR.r[i].UL[1]], g_cpuConstRegs[i].UL[1]);
g_cpuFlushedConstReg |= 1<<i;
}
@ -302,9 +302,9 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
if( type == X86TYPE_GPR ) _flushConstReg(reg);
if( X86_ISVI(type) && reg < 16 )
MOVZX32M16toR(i, _x86GetAddr(type, reg));
xMOVZX(xRegister32(i), ptr16[(u16*)(_x86GetAddr(type, reg))]);
else
MOV32MtoR(i, _x86GetAddr(type, reg));
xMOV(xRegister32(i), ptr[(void*)(_x86GetAddr(type, reg))]);
x86regs[i].mode |= MODE_READ;
}
@ -328,12 +328,12 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
if( mode & MODE_READ ) {
if( readfromreg >= 0 )
MOV32RtoR(x86reg, readfromreg);
xMOV(xRegister32(x86reg), xRegister32(readfromreg));
else {
if( type == X86TYPE_GPR ) {
if( reg == 0 ) {
XOR32RtoR(x86reg, x86reg);
xXOR(xRegister32(x86reg), xRegister32(x86reg));
}
else {
_flushConstReg(reg);
@ -349,11 +349,11 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
else {
if( X86_ISVI(type) && reg < 16 ) {
if( reg == 0 )
XOR32RtoR(x86reg, x86reg);
xXOR(xRegister32(x86reg), xRegister32(x86reg));
else
MOVZX32M16toR(x86reg, _x86GetAddr(type, reg));
xMOVZX(xRegister32(x86reg), ptr16[(u16*)(_x86GetAddr(type, reg))]);
}
else MOV32MtoR(x86reg, _x86GetAddr(type, reg));
else xMOV(xRegister32(x86reg), ptr[(void*)(_x86GetAddr(type, reg))]);
}
}
}
@ -370,9 +370,9 @@ int _checkX86reg(int type, int reg, int mode)
if( !(x86regs[i].mode & MODE_READ) && (mode&MODE_READ) ) {
if( X86_ISVI(type) )
MOVZX32M16toR(i, _x86GetAddr(type, reg));
xMOVZX(xRegister32(i), ptr16[(u16*)(_x86GetAddr(type, reg))]);
else
MOV32MtoR(i, _x86GetAddr(type, reg));
xMOV(xRegister32(i), ptr[(void*)(_x86GetAddr(type, reg))]);
}
x86regs[i].mode |= mode;
@ -424,9 +424,9 @@ void _deleteX86reg(int type, int reg, int flush)
if( x86regs[i].mode & MODE_WRITE) {
if( X86_ISVI(type) && x86regs[i].reg < 16 )
MOV16RtoM(_x86GetAddr(type, x86regs[i].reg), i);
xMOV(ptr[(void*)(_x86GetAddr(type, x86regs[i].reg))], xRegister16(i));
else
MOV32RtoM(_x86GetAddr(type, x86regs[i].reg), i);
xMOV(ptr[(void*)(_x86GetAddr(type, x86regs[i].reg))], xRegister32(i));
// get rid of MODE_WRITE since don't want to flush again
x86regs[i].mode &= ~MODE_WRITE;
@ -450,10 +450,10 @@ void _freeX86reg(int x86reg)
x86regs[x86reg].mode &= ~MODE_WRITE;
if( X86_ISVI(x86regs[x86reg].type) && x86regs[x86reg].reg < 16 ) {
MOV16RtoM(_x86GetAddr(x86regs[x86reg].type, x86regs[x86reg].reg), x86reg);
xMOV(ptr[(void*)(_x86GetAddr(x86regs[x86reg].type, x86regs[x86reg].reg))], xRegister16(x86reg));
}
else
MOV32RtoM(_x86GetAddr(x86regs[x86reg].type, x86regs[x86reg].reg), x86reg);
xMOV(ptr[(void*)(_x86GetAddr(x86regs[x86reg].type, x86regs[x86reg].reg))], xRegister32(x86reg));
}
x86regs[x86reg].inuse = 0;
@ -573,14 +573,14 @@ int _allocMMXreg(int mmxreg, int reg, int mode)
SetMMXstate();
if( reg == MMX_GPR ) {
// moving in 0s
PXORRtoR(i, i);
xPXOR(xRegisterMMX(i), xRegisterMMX(i));
}
else {
if( MMX_ISGPR(reg) ) _flushConstReg(reg-MMX_GPR);
if( (mode & MODE_READHALF) || (MMX_IS32BITS(reg)&&(mode&MODE_READ)) )
MOVDMtoMMX(i, (uptr)_MMXGetAddr(reg));
xMOVDZX(xRegisterMMX(i), ptr[(_MMXGetAddr(reg))]);
else
MOVQMtoR(i, (uptr)_MMXGetAddr(reg));
xMOVQ(xRegisterMMX(i), ptr[(_MMXGetAddr(reg))]);
}
mmxregs[i].mode |= MODE_READ;
@ -604,14 +604,14 @@ int _allocMMXreg(int mmxreg, int reg, int mode)
SetMMXstate();
if( reg == MMX_GPR ) {
// moving in 0s
PXORRtoR(mmxreg, mmxreg);
xPXOR(xRegisterMMX(mmxreg), xRegisterMMX(mmxreg));
}
else {
int xmmreg;
if( MMX_ISGPR(reg) && (xmmreg = _checkXMMreg(XMMTYPE_GPRREG, reg-MMX_GPR, 0)) >= 0 ) {
SSE_MOVHPS_XMM_to_M64((uptr)_MMXGetAddr(reg)+8, xmmreg);
xMOVH.PS(ptr[(void*)((uptr)_MMXGetAddr(reg)+8)], xRegisterSSE(xmmreg));
if( mode & MODE_READ )
SSE2_MOVDQ2Q_XMM_to_MM(mmxreg, xmmreg);
xMOVQ(xRegisterMMX(mmxreg), xRegisterSSE(xmmreg));
if( xmmregs[xmmreg].mode & MODE_WRITE )
mmxregs[mmxreg].mode |= MODE_WRITE;
@ -625,10 +625,10 @@ int _allocMMXreg(int mmxreg, int reg, int mode)
}
if( (mode & MODE_READHALF) || (MMX_IS32BITS(reg)&&(mode&MODE_READ)) ) {
MOVDMtoMMX(mmxreg, (uptr)_MMXGetAddr(reg));
xMOVDZX(xRegisterMMX(mmxreg), ptr[(_MMXGetAddr(reg))]);
}
else if( mode & MODE_READ ) {
MOVQMtoR(mmxreg, (uptr)_MMXGetAddr(reg));
xMOVQ(xRegisterMMX(mmxreg), ptr[(_MMXGetAddr(reg))]);
}
}
}
@ -646,14 +646,14 @@ int _checkMMXreg(int reg, int mode)
if( reg == MMX_GPR ) {
// moving in 0s
PXORRtoR(i, i);
xPXOR(xRegisterMMX(i), xRegisterMMX(i));
}
else {
if (MMX_ISGPR(reg) && (mode&(MODE_READHALF|MODE_READ))) _flushConstReg(reg-MMX_GPR);
if( (mode & MODE_READHALF) || (MMX_IS32BITS(reg)&&(mode&MODE_READ)) )
MOVDMtoMMX(i, (uptr)_MMXGetAddr(reg));
xMOVDZX(xRegisterMMX(i), ptr[(_MMXGetAddr(reg))]);
else
MOVQMtoR(i, (uptr)_MMXGetAddr(reg));
xMOVQ(xRegisterMMX(i), ptr[(_MMXGetAddr(reg))]);
}
SetMMXstate();
}
@ -711,9 +711,9 @@ void _deleteMMXreg(int reg, int flush)
pxAssert( mmxregs[i].reg != MMX_GPR );
if( MMX_IS32BITS(reg) )
MOVDMMXtoM((uptr)_MMXGetAddr(mmxregs[i].reg), i);
xMOVD(ptr[(_MMXGetAddr(mmxregs[i].reg))], xRegisterMMX(i));
else
MOVQRtoM((uptr)_MMXGetAddr(mmxregs[i].reg), i);
xMOVQ(ptr[(_MMXGetAddr(mmxregs[i].reg))], xRegisterMMX(i));
SetMMXstate();
// get rid of MODE_WRITE since don't want to flush again
@ -783,9 +783,9 @@ void _freeMMXreg(u32 mmxreg)
pxAssert( mmxregs[mmxreg].reg != MMX_GPR );
if( MMX_IS32BITS(mmxregs[mmxreg].reg) )
MOVDMMXtoM((uptr)_MMXGetAddr(mmxregs[mmxreg].reg), mmxreg);
xMOVD(ptr[(_MMXGetAddr(mmxregs[mmxreg].reg))], xRegisterMMX(mmxreg));
else
MOVQRtoM((uptr)_MMXGetAddr(mmxregs[mmxreg].reg), mmxreg);
xMOVQ(ptr[(_MMXGetAddr(mmxregs[mmxreg].reg))], xRegisterMMX(mmxreg));
SetMMXstate();
}
@ -812,7 +812,7 @@ void _moveMMXreg(int mmxreg)
// move
mmxregs[i] = mmxregs[mmxreg];
mmxregs[mmxreg].inuse = 0;
MOVQRtoR(i, mmxreg);
xMOVQ(xRegisterMMX(i), xRegisterMMX(mmxreg));
}
// write all active regs
@ -830,9 +830,9 @@ void _flushMMXregs()
pxAssert( mmxregs[i].reg != MMX_GPR );
if( MMX_IS32BITS(mmxregs[i].reg) )
MOVDMMXtoM((uptr)_MMXGetAddr(mmxregs[i].reg), i);
xMOVD(ptr[(_MMXGetAddr(mmxregs[i].reg))], xRegisterMMX(i));
else
MOVQRtoM((uptr)_MMXGetAddr(mmxregs[i].reg), i);
xMOVQ(ptr[(_MMXGetAddr(mmxregs[i].reg))], xRegisterMMX(i));
SetMMXstate();
mmxregs[i].mode &= ~MODE_WRITE;
@ -859,27 +859,27 @@ void SetFPUstate() {
_freeMMXreg(7);
if (x86FpuState == MMX_STATE) {
EMMS();
xEMMS();
x86FpuState = FPU_STATE;
}
}
void _signExtendSFtoM(u32 mem)
{
LAHF();
SAR16ItoR(EAX, 15);
CWDE();
MOV32RtoM(mem, EAX );
xLAHF();
xSAR(ax, 15);
xCWDE();
xMOV(ptr[(void*)(mem)], eax);
}
int _signExtendMtoMMX(x86MMXRegType to, u32 mem)
{
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
MOVDMtoMMX(t0reg, mem);
MOVQRtoR(to, t0reg);
PSRADItoR(t0reg, 31);
PUNPCKLDQRtoR(to, t0reg);
xMOVDZX(xRegisterMMX(t0reg), ptr[(void*)(mem)]);
xMOVQ(xRegisterMMX(to), xRegisterMMX(t0reg));
xPSRA.D(xRegisterMMX(t0reg), 31);
xPUNPCK.LDQ(xRegisterMMX(to), xRegisterMMX(t0reg));
_freeMMXreg(t0reg);
return to;
@ -892,7 +892,7 @@ int _signExtendGPRMMXtoMMX(x86MMXRegType to, u32 gprreg, x86MMXRegType from, u32
if( to == from ) return _signExtendGPRtoMMX(to, gprreg, 0);
if( !(g_pCurInstInfo->regs[gprfromreg]&EEINST_LASTUSE) ) {
if( EEINST_ISLIVE64(gprfromreg) ) {
MOVQRtoR(to, from);
xMOVQ(xRegisterMMX(to), xRegisterMMX(from));
return _signExtendGPRtoMMX(to, gprreg, 0);
}
}
@ -900,10 +900,10 @@ int _signExtendGPRMMXtoMMX(x86MMXRegType to, u32 gprreg, x86MMXRegType from, u32
// from is free for use
SetMMXstate();
MOVQRtoR(to, from);
MOVDMMXtoM((uptr)&cpuRegs.GPR.r[gprreg].UL[0], from);
PSRADItoR(from, 31);
MOVDMMXtoM((uptr)&cpuRegs.GPR.r[gprreg].UL[1], from);
xMOVQ(xRegisterMMX(to), xRegisterMMX(from));
xMOVD(ptr[&cpuRegs.GPR.r[gprreg].UL[0]], xRegisterMMX(from));
xPSRA.D(xRegisterMMX(from), 31);
xMOVD(ptr[&cpuRegs.GPR.r[gprreg].UL[1]], xRegisterMMX(from));
mmxregs[to].inuse = 0;
return -1;
@ -915,10 +915,10 @@ int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift)
SetMMXstate();
if( shift > 0 ) PSRADItoR(to, shift);
MOVDMMXtoM((uptr)&cpuRegs.GPR.r[gprreg].UL[0], to);
PSRADItoR(to, 31);
MOVDMMXtoM((uptr)&cpuRegs.GPR.r[gprreg].UL[1], to);
if( shift > 0 ) xPSRA.D(xRegisterMMX(to), shift);
xMOVD(ptr[&cpuRegs.GPR.r[gprreg].UL[0]], xRegisterMMX(to));
xPSRA.D(xRegisterMMX(to), 31);
xMOVD(ptr[&cpuRegs.GPR.r[gprreg].UL[1]], xRegisterMMX(to));
mmxregs[to].inuse = 0;
return -1;
@ -934,12 +934,12 @@ static const __aligned16 u32 s_ones[2] = {0xffffffff, 0xffffffff};
void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op)
{
switch(op) {
case 0: PANDRtoR(to, from); break;
case 1: PORRtoR(to, from); break;
case 2: PXORRtoR(to, from); break;
case 0: xPAND(xRegisterMMX(to), xRegisterMMX(from)); break;
case 1: xPOR(xRegisterMMX(to), xRegisterMMX(from)); break;
case 2: xPXOR(xRegisterMMX(to), xRegisterMMX(from)); break;
case 3:
PORRtoR(to, from);
PXORMtoR(to, (uptr)&s_ones[0]);
xPOR(xRegisterMMX(to), xRegisterMMX(from));
xPXOR(xRegisterMMX(to), ptr[&s_ones[0]]);
break;
}
}
@ -947,12 +947,12 @@ void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op)
void LogicalOpMtoR(x86MMXRegType to, uptr from, int op)
{
switch(op) {
case 0: PANDMtoR(to, from); break;
case 1: PORMtoR(to, from); break;
case 2: PXORMtoR(to, from); break;
case 0: xPAND(xRegisterMMX(to), ptr[(void*)(from)]); break;
case 1: xPOR(xRegisterMMX(to), ptr[(void*)(from)]); break;
case 2: xPXOR(xRegisterMMX(to), ptr[(void*)(from)]); break;
case 3:
PORRtoR(to, from);
PXORMtoR(to, (uptr)&s_ones[0]);
xPOR(xRegisterMMX(to), xRegisterMMX(from));
xPXOR(xRegisterMMX(to), ptr[&s_ones[0]]);
break;
}
}
@ -960,39 +960,39 @@ void LogicalOpMtoR(x86MMXRegType to, uptr from, int op)
void LogicalOp32RtoM(uptr to, x86IntRegType from, int op)
{
switch(op) {
case 0: AND32RtoM(to, from); break;
case 1: OR32RtoM(to, from); break;
case 2: XOR32RtoM(to, from); break;
case 3: OR32RtoM(to, from); break;
case 0: xAND(ptr[(void*)(to)], xRegister32(from)); break;
case 1: xOR(ptr[(void*)(to)], xRegister32(from)); break;
case 2: xXOR(ptr[(void*)(to)], xRegister32(from)); break;
case 3: xOR(ptr[(void*)(to)], xRegister32(from)); break;
}
}
void LogicalOp32MtoR(x86IntRegType to, uptr from, int op)
{
switch(op) {
case 0: AND32MtoR(to, from); break;
case 1: OR32MtoR(to, from); break;
case 2: XOR32MtoR(to, from); break;
case 3: OR32MtoR(to, from); break;
case 0: xAND(xRegister32(to), ptr[(void*)(from)]); break;
case 1: xOR(xRegister32(to), ptr[(void*)(from)]); break;
case 2: xXOR(xRegister32(to), ptr[(void*)(from)]); break;
case 3: xOR(xRegister32(to), ptr[(void*)(from)]); break;
}
}
void LogicalOp32ItoR(x86IntRegType to, u32 from, int op)
{
switch(op) {
case 0: AND32ItoR(to, from); break;
case 1: OR32ItoR(to, from); break;
case 2: XOR32ItoR(to, from); break;
case 3: OR32ItoR(to, from); break;
case 0: xAND(xRegister32(to), from); break;
case 1: xOR(xRegister32(to), from); break;
case 2: xXOR(xRegister32(to), from); break;
case 3: xOR(xRegister32(to), from); break;
}
}
void LogicalOp32ItoM(uptr to, u32 from, int op)
{
switch(op) {
case 0: AND32ItoM(to, from); break;
case 1: OR32ItoM(to, from); break;
case 2: XOR32ItoM(to, from); break;
case 3: OR32ItoM(to, from); break;
case 0: xAND(ptr32[(u32*)(to)], from); break;
case 1: xOR(ptr32[(u32*)(to)], from); break;
case 2: xXOR(ptr32[(u32*)(to)], from); break;
case 3: xOR(ptr32[(u32*)(to)], from); break;
}
}

72
pcsx2/x86/ix86-32/iR5900-32.cpp
View File

@ -155,21 +155,21 @@ u32* _eeGetConstReg(int reg)
void _eeMoveGPRtoR(x86IntRegType to, int fromgpr)
{
if( fromgpr == 0 )
XOR32RtoR( to, to ); // zero register should use xor, thanks --air
xXOR(xRegister32(to), xRegister32(to )); // zero register should use xor, thanks --air
else if( GPR_IS_CONST1(fromgpr) )
MOV32ItoR( to, g_cpuConstRegs[fromgpr].UL[0] );
xMOV(xRegister32(to), g_cpuConstRegs[fromgpr].UL[0] );
else {
int mmreg;
if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, fromgpr, MODE_READ)) >= 0 && (xmmregs[mmreg].mode&MODE_WRITE)) {
SSE2_MOVD_XMM_to_R(to, mmreg);
xMOVD(xRegister32(to), xRegisterSSE(mmreg));
}
else if( (mmreg = _checkMMXreg(MMX_GPR+fromgpr, MODE_READ)) >= 0 && (mmxregs[mmreg].mode&MODE_WRITE) ) {
MOVD32MMXtoR(to, mmreg);
xMOVD(xRegister32(to), xRegisterMMX(mmreg));
SetMMXstate();
}
else {
MOV32MtoR(to, (uptr)&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] );
xMOV(xRegister32(to), ptr[&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] ]);
}
}
}
@ -177,20 +177,20 @@ void _eeMoveGPRtoR(x86IntRegType to, int fromgpr)
void _eeMoveGPRtoM(u32 to, int fromgpr)
{
if( GPR_IS_CONST1(fromgpr) )
MOV32ItoM( to, g_cpuConstRegs[fromgpr].UL[0] );
xMOV(ptr32[(u32*)(to)], g_cpuConstRegs[fromgpr].UL[0] );
else {
int mmreg;
if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, fromgpr, MODE_READ)) >= 0 ) {
SSEX_MOVD_XMM_to_M32(to, mmreg);
xMOVSS(ptr[(void*)(to)], xRegisterSSE(mmreg));
}
else if( (mmreg = _checkMMXreg(MMX_GPR+fromgpr, MODE_READ)) >= 0 ) {
MOVDMMXtoM(to, mmreg);
xMOVD(ptr[(void*)(to)], xRegisterMMX(mmreg));
SetMMXstate();
}
else {
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] );
MOV32RtoM(to, EAX );
xMOV(eax, ptr[&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] ]);
xMOV(ptr[(void*)(to)], eax);
}
}
}
@ -198,20 +198,20 @@ void _eeMoveGPRtoM(u32 to, int fromgpr)
void _eeMoveGPRtoRm(x86IntRegType to, int fromgpr)
{
if( GPR_IS_CONST1(fromgpr) )
MOV32ItoRm( to, g_cpuConstRegs[fromgpr].UL[0] );
xMOV(ptr32[xAddressReg(to)], g_cpuConstRegs[fromgpr].UL[0] );
else {
int mmreg;
if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, fromgpr, MODE_READ)) >= 0 ) {
SSEX_MOVD_XMM_to_Rm(to, mmreg);
xMOVSS(ptr[xAddressReg(to)], xRegisterSSE(mmreg));
}
else if( (mmreg = _checkMMXreg(MMX_GPR+fromgpr, MODE_READ)) >= 0 ) {
MOVD32MMXtoRm(to, mmreg);
xMOVD(ptr[xAddressReg(to)], xRegisterMMX(mmreg));
SetMMXstate();
}
else {
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] );
MOV32RtoRm( to, EAX );
xMOV(eax, ptr[&cpuRegs.GPR.r[ fromgpr ].UL[ 0 ] ]);
xMOV(ptr[xAddressReg(to)], eax);
}
}
}
@ -270,8 +270,8 @@ int _flushUnusedConstReg()
!_recIsRegWritten(g_pCurInstInfo+1, (s_nEndBlock-pc)/4, XMMTYPE_GPRREG, i) ) {
// check if will be written in the future
MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[0], g_cpuConstRegs[i].UL[0]);
MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[1], g_cpuConstRegs[i].UL[1]);
xMOV(ptr32[&cpuRegs.GPR.r[i].UL[0]], g_cpuConstRegs[i].UL[0]);
xMOV(ptr32[&cpuRegs.GPR.r[i].UL[1]], g_cpuConstRegs[i].UL[1]);
g_cpuFlushedConstReg |= 1<<i;
return 1;
}
@ -328,8 +328,8 @@ void recBranchCall( void (*func)() )
// In order to make sure a branch test is performed, the nextBranchCycle is set
// to the current cpu cycle.
MOV32MtoR( EAX, (uptr)&cpuRegs.cycle );
MOV32RtoM( (uptr)&g_nextEventCycle, EAX );
xMOV(eax, ptr[&cpuRegs.cycle ]);
xMOV(ptr[&g_nextEventCycle], eax);
recCall(func);
g_branch = 2;
@ -845,9 +845,9 @@ void R5900::Dynarec::OpcodeImpl::recSYSCALL()
{
recCall(R5900::Interpreter::OpcodeImpl::SYSCALL);
CMP32ItoM((uptr)&cpuRegs.pc, pc);
xCMP(ptr32[&cpuRegs.pc], pc);
j8Ptr[0] = JE8(0);
ADD32ItoM((uptr)&cpuRegs.cycle, scaleblockcycles());
xADD(ptr32[&cpuRegs.cycle], ScaleBlockCycles());
// Note: technically the address is 0x8000_0180 (or 0x180)
// (if CPU is booted)
xJMP( DispatcherReg );
@ -860,9 +860,9 @@ void R5900::Dynarec::OpcodeImpl::recBREAK()
{
recCall(R5900::Interpreter::OpcodeImpl::BREAK);
CMP32ItoM((uptr)&cpuRegs.pc, pc);
xCMP(ptr32[&cpuRegs.pc], pc);
j8Ptr[0] = JE8(0);
ADD32ItoM((uptr)&cpuRegs.cycle, scaleblockcycles());
xADD(ptr32[&cpuRegs.cycle], ScaleBlockCycles());
xJMP( DispatcherEvent );
x86SetJ8(j8Ptr[0]);
//g_branch = 2;
@ -947,20 +947,20 @@ void SetBranchReg( u32 reg )
if( reg != 0xffffffff ) {
// if( GPR_IS_CONST1(reg) )
// MOV32ItoM( (uptr)&cpuRegs.pc, g_cpuConstRegs[reg].UL[0] );
// xMOV(ptr32[&cpuRegs.pc], g_cpuConstRegs[reg].UL[0] );
// else {
// int mmreg;
//
// if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, reg, MODE_READ)) >= 0 ) {
// SSE_MOVSS_XMM_to_M32((u32)&cpuRegs.pc, mmreg);
// xMOVSS(ptr[&cpuRegs.pc], xRegisterSSE(mmreg));
// }
// else if( (mmreg = _checkMMXreg(MMX_GPR+reg, MODE_READ)) >= 0 ) {
// MOVDMMXtoM((u32)&cpuRegs.pc, mmreg);
// xMOVD(ptr[&cpuRegs.pc], xRegisterMMX(mmreg));
// SetMMXstate();
// }
// else {
// MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ reg ].UL[ 0 ] );
// MOV32RtoM((u32)&cpuRegs.pc, EAX);
// xMOV(eax, ptr[(void*)((int)&cpuRegs.GPR.r[ reg ].UL[ 0 ] )]);
// xMOV(ptr[&cpuRegs.pc], eax);
// }
// }
_allocX86reg(ESI, X86TYPE_PCWRITEBACK, 0, MODE_WRITE);
@ -976,18 +976,18 @@ void SetBranchReg( u32 reg )
if( x86regs[ESI].inuse ) {
pxAssert( x86regs[ESI].type == X86TYPE_PCWRITEBACK );
MOV32RtoM((uptr)&cpuRegs.pc, ESI);
xMOV(ptr[&cpuRegs.pc], esi);
x86regs[ESI].inuse = 0;
}
else {
MOV32MtoR(EAX, (uptr)&g_recWriteback);
MOV32RtoM((uptr)&cpuRegs.pc, EAX);
xMOV(eax, ptr[&g_recWriteback]);
xMOV(ptr[&cpuRegs.pc], eax);
}
}
// CMP32ItoM((u32)&cpuRegs.pc, 0);
// xCMP(ptr32[&cpuRegs.pc], 0);
// j8Ptr[5] = JNE8(0);
// CALLFunc((uptr)tempfn);
// xCALL((void*)(uptr)tempfn);
// x86SetJ8( j8Ptr[5] );
iFlushCall(FLUSH_EVERYTHING);
@ -1073,7 +1073,7 @@ void iFlushCall(int flushtype)
_flushConstRegs();
if (x86FpuState==MMX_STATE) {
EMMS();
xEMMS();
x86FpuState=FPU_STATE;
}
}
@ -1372,7 +1372,7 @@ void recompileNextInstruction(int delayslot)
pxAssert(s_pCode);
if( IsDebugBuild )
MOV32ItoR(EAX, pc); // acts as a tag for delimiting recompiled instructions when viewing x86 disasm.
xMOV(eax, pc); // acts as a tag for delimiting recompiled instructions when viewing x86 disasm.
cpuRegs.code = *(int *)s_pCode;
@ -1796,7 +1796,7 @@ static void __fastcall recRecompile( const u32 startpc )
// Game will unmap some virtual addresses. If a constant address were hardcoded in the block, we would be in a bad situation.
AtomicExchange( eeRecNeedsReset, true );
// 0x3563b8 is the start address of the function that invalidate entry in TLB cache
MOV32MtoR(ECX, (uptr)&cpuRegs.GPR.n.a0.UL[ 0 ] );
xMOV(ecx, ptr[&cpuRegs.GPR.n.a0.UL[ 0 ] ]);
xCALL(GoemonUnloadTlb);
}
}

74
pcsx2/x86/ix86-32/iR5900AritImm.cpp
View File

@ -61,17 +61,17 @@ void recADDI_(int info)
if ( _Rt_ == _Rs_ ) {
// must perform the ADD unconditionally, to maintain flags status:
ADD32ItoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
xADD(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], _Imm_);
_signExtendSFtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]);
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
if ( _Imm_ != 0 ) ADD32ItoR( EAX, _Imm_ );
if ( _Imm_ != 0 ) xADD(eax, _Imm_ );
CDQ( );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
xCDQ( );
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], edx);
}
}
@ -94,23 +94,23 @@ void recDADDI_(int info)
pxAssert( !(info&PROCESS_EE_XMM) );
if( _Rt_ == _Rs_ ) {
ADD32ItoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
ADC32ItoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], _Imm_<0?0xffffffff:0);
xADD(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], _Imm_);
xADC(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], _Imm_<0?0xffffffff:0);
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
MOV32MtoR( EDX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
xMOV(edx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] ]);
if ( _Imm_ != 0 )
{
ADD32ItoR( EAX, _Imm_ );
ADC32ItoR( EDX, _Imm_ < 0?0xffffffff:0);
xADD(eax, _Imm_ );
xADC(edx, _Imm_ < 0?0xffffffff:0);
}
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], eax);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], edx);
}
}
@ -133,23 +133,23 @@ extern u32 s_sltone;
void recSLTIU_(int info)
{
MOV32ItoR(EAX, 1);
xMOV(eax, 1);
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]], _Imm_ >= 0 ? 0 : 0xffffffff);
j8Ptr[0] = JB8( 0 );
j8Ptr[2] = JA8( 0 );
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], (s32)_Imm_ );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]], (s32)_Imm_ );
j8Ptr[1] = JB8(0);
x86SetJ8(j8Ptr[2]);
XOR32RtoR(EAX, EAX);
xXOR(eax, eax);
x86SetJ8(j8Ptr[0]);
x86SetJ8(j8Ptr[1]);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], eax);
xMOV(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], 0 );
}
EERECOMPILE_CODEX(eeRecompileCode1, SLTIU);
@ -163,23 +163,23 @@ void recSLTI_const()
void recSLTI_(int info)
{
// test silent hill if modding
MOV32ItoR(EAX, 1);
xMOV(eax, 1);
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]], _Imm_ >= 0 ? 0 : 0xffffffff);
j8Ptr[0] = JL8( 0 );
j8Ptr[2] = JG8( 0 );
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], (s32)_Imm_ );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]], (s32)_Imm_ );
j8Ptr[1] = JB8(0);
x86SetJ8(j8Ptr[2]);
XOR32RtoR(EAX, EAX);
xXOR(eax, eax);
x86SetJ8(j8Ptr[0]);
x86SetJ8(j8Ptr[1]);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], eax);
xMOV(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], 0 );
}
EERECOMPILE_CODEX(eeRecompileCode1, SLTI);
@ -198,31 +198,31 @@ void recLogicalOpI(int info, int op)
LogicalOp32ItoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _ImmU_, op);
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
if( op != 0 )
MOV32MtoR( EDX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
xMOV(edx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] ]);
LogicalOp32ItoR( EAX, _ImmU_, op);
if( op != 0 )
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], edx);
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], eax);
}
if( op == 0 ) {
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
xMOV(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], 0 );
}
}
else
{
if( op == 0 ) {
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], 0 );
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
xMOV(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], 0 );
xMOV(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], 0 );
}
else {
if( _Rt_ != _Rs_ ) {
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MOV32MtoR(EDX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xMOV(edx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] ]);
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], edx);
}
}
}

98
pcsx2/x86/ix86-32/iR5900Branch.cpp
View File

@ -67,11 +67,11 @@ void recSetBranchEQ(int info, int bne, int process)
}
else {
t0reg = _allocTempXMMreg(XMMT_INT, -1);
SSE2_MOVQ_XMM_to_XMM(t0reg, EEREC_T);
xMOVQZX(xRegisterSSE(t0reg), xRegisterSSE(EEREC_T));
}
_flushConstReg(_Rs_);
SSE2_PCMPEQD_M128_to_XMM(t0reg, (uptr)&cpuRegs.GPR.r[_Rs_].UL[0]);
xPCMP.EQD(xRegisterSSE(t0reg), ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
if( t0reg != EEREC_T ) _freeXMMreg(t0reg);
@ -84,11 +84,11 @@ void recSetBranchEQ(int info, int bne, int process)
}
else {
t0reg = _allocTempXMMreg(XMMT_INT, -1);
SSE2_MOVQ_XMM_to_XMM(t0reg, EEREC_S);
xMOVQZX(xRegisterSSE(t0reg), xRegisterSSE(EEREC_S));
}
_flushConstReg(_Rt_);
SSE2_PCMPEQD_M128_to_XMM(t0reg, (uptr)&cpuRegs.GPR.r[_Rt_].UL[0]);
xPCMP.EQD(xRegisterSSE(t0reg), ptr[&cpuRegs.GPR.r[_Rt_].UL[0]]);
if( t0reg != EEREC_S ) _freeXMMreg(t0reg);
}
@ -98,29 +98,29 @@ void recSetBranchEQ(int info, int bne, int process)
_deleteGPRtoXMMreg(_Rs_, 1);
xmmregs[EEREC_S].inuse = 0;
t0reg = EEREC_S;
SSE2_PCMPEQD_XMM_to_XMM(t0reg, EEREC_T);
xPCMP.EQD(xRegisterSSE(t0reg), xRegisterSSE(EEREC_T));
}
else if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rt_) ) {
_deleteGPRtoXMMreg(_Rt_, 1);
xmmregs[EEREC_T].inuse = 0;
t0reg = EEREC_T;
SSE2_PCMPEQD_XMM_to_XMM(t0reg, EEREC_S);
xPCMP.EQD(xRegisterSSE(t0reg), xRegisterSSE(EEREC_S));
}
else {
t0reg = _allocTempXMMreg(XMMT_INT, -1);
SSE2_MOVQ_XMM_to_XMM(t0reg, EEREC_S);
SSE2_PCMPEQD_XMM_to_XMM(t0reg, EEREC_T);
xMOVQZX(xRegisterSSE(t0reg), xRegisterSSE(EEREC_S));
xPCMP.EQD(xRegisterSSE(t0reg), xRegisterSSE(EEREC_T));
}
if( t0reg != EEREC_S && t0reg != EEREC_T ) _freeXMMreg(t0reg);
}
SSE_MOVMSKPS_XMM_to_R32(EAX, t0reg);
xMOVMSKPS(eax, xRegisterSSE(t0reg));
_eeFlushAllUnused();
AND8ItoR(EAX, 3);
CMP8ItoR( EAX, 0x3 );
xAND(al, 3);
xCMP(al, 0x3 );
if( bne ) j32Ptr[ 1 ] = JE32( 0 );
else j32Ptr[ 0 ] = j32Ptr[ 1 ] = JNE32( 0 );
@ -131,26 +131,26 @@ void recSetBranchEQ(int info, int bne, int process)
if( bne ) {
if( process & PROCESS_CONSTS ) {
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0] );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], g_cpuConstRegs[_Rs_].UL[0] );
j8Ptr[ 0 ] = JNE8( 0 );
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1] );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], g_cpuConstRegs[_Rs_].UL[1] );
j32Ptr[ 1 ] = JE32( 0 );
}
else if( process & PROCESS_CONSTT ) {
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], g_cpuConstRegs[_Rt_].UL[0] );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]], g_cpuConstRegs[_Rt_].UL[0] );
j8Ptr[ 0 ] = JNE8( 0 );
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], g_cpuConstRegs[_Rt_].UL[1] );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]], g_cpuConstRegs[_Rt_].UL[1] );
j32Ptr[ 1 ] = JE32( 0 );
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
CMP32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xCMP(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
j8Ptr[ 0 ] = JNE8( 0 );
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
CMP32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] ]);
xCMP(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] ]);
j32Ptr[ 1 ] = JE32( 0 );
}
@ -159,26 +159,26 @@ void recSetBranchEQ(int info, int bne, int process)
else {
// beq
if( process & PROCESS_CONSTS ) {
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0] );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], g_cpuConstRegs[_Rs_].UL[0] );
j32Ptr[ 0 ] = JNE32( 0 );
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1] );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], g_cpuConstRegs[_Rs_].UL[1] );
j32Ptr[ 1 ] = JNE32( 0 );
}
else if( process & PROCESS_CONSTT ) {
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], g_cpuConstRegs[_Rt_].UL[0] );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]], g_cpuConstRegs[_Rt_].UL[0] );
j32Ptr[ 0 ] = JNE32( 0 );
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], g_cpuConstRegs[_Rt_].UL[1] );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]], g_cpuConstRegs[_Rt_].UL[1] );
j32Ptr[ 1 ] = JNE32( 0 );
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
CMP32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xCMP(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
j32Ptr[ 0 ] = JNE32( 0 );
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
CMP32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] ]);
xCMP(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] ]);
j32Ptr[ 1 ] = JNE32( 0 );
}
}
@ -193,11 +193,11 @@ void recSetBranchL(int ltz)
int regs = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ);
if( regs >= 0 ) {
SSE_MOVMSKPS_XMM_to_R32(EAX, regs);
xMOVMSKPS(eax, xRegisterSSE(regs));
_eeFlushAllUnused();
TEST8ItoR( EAX, 2 );
xTEST(al, 2 );
if( ltz ) j32Ptr[ 0 ] = JZ32( 0 );
else j32Ptr[ 0 ] = JNZ32( 0 );
@ -205,7 +205,7 @@ void recSetBranchL(int ltz)
return;
}
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]], 0 );
if( ltz ) j32Ptr[ 0 ] = JGE32( 0 );
else j32Ptr[ 0 ] = JL32( 0 );
@ -393,10 +393,10 @@ EERECOMPILE_CODE0(BNEL, XMMINFO_READS|XMMINFO_READT);
//{
// Console.WriteLn("BLTZAL");
// _eeFlushAllUnused();
// MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code );
// MOV32ItoM( (int)&cpuRegs.pc, pc );
// xMOV(ptr32[(u32*)((int)&cpuRegs.code)], cpuRegs.code );
// xMOV(ptr32[(u32*)((int)&cpuRegs.pc)], pc );
// iFlushCall(FLUSH_EVERYTHING);
// CALLFunc( (int)BLTZAL );
// xCALL((void*)(int)BLTZAL );
// branch = 2;
//}
@ -409,8 +409,8 @@ void recBLTZAL()
_eeFlushAllUnused();
_deleteEEreg(31, 0);
MOV32ItoM((uptr)&cpuRegs.GPR.r[31].UL[0], pc+4);
MOV32ItoM((uptr)&cpuRegs.GPR.r[31].UL[1], 0);
xMOV(ptr32[&cpuRegs.GPR.r[31].UL[0]], pc+4);
xMOV(ptr32[&cpuRegs.GPR.r[31].UL[1]], 0);
if( GPR_IS_CONST1(_Rs_) ) {
if( !(g_cpuConstRegs[_Rs_].SD[0] < 0) )
@ -448,8 +448,8 @@ void recBGEZAL()
_eeFlushAllUnused();
_deleteEEreg(31, 0);
MOV32ItoM((uptr)&cpuRegs.GPR.r[31].UL[0], pc+4);
MOV32ItoM((uptr)&cpuRegs.GPR.r[31].UL[1], 0);
xMOV(ptr32[&cpuRegs.GPR.r[31].UL[0]], pc+4);
xMOV(ptr32[&cpuRegs.GPR.r[31].UL[1]], 0);
if( GPR_IS_CONST1(_Rs_) ) {
if( !(g_cpuConstRegs[_Rs_].SD[0] >= 0) )
@ -487,8 +487,8 @@ void recBLTZALL()
_eeFlushAllUnused();
_deleteEEreg(31, 0);
MOV32ItoM((uptr)&cpuRegs.GPR.r[31].UL[0], pc+4);
MOV32ItoM((uptr)&cpuRegs.GPR.r[31].UL[1], 0);
xMOV(ptr32[&cpuRegs.GPR.r[31].UL[0]], pc+4);
xMOV(ptr32[&cpuRegs.GPR.r[31].UL[1]], 0);
if( GPR_IS_CONST1(_Rs_) ) {
if( !(g_cpuConstRegs[_Rs_].SD[0] < 0) )
@ -521,8 +521,8 @@ void recBGEZALL()
_eeFlushAllUnused();
_deleteEEreg(31, 0);
MOV32ItoM((uptr)&cpuRegs.GPR.r[31].UL[0], pc+4);
MOV32ItoM((uptr)&cpuRegs.GPR.r[31].UL[1], 0);
xMOV(ptr32[&cpuRegs.GPR.r[31].UL[0]], pc+4);
xMOV(ptr32[&cpuRegs.GPR.r[31].UL[1]], 0);
if( GPR_IS_CONST1(_Rs_) ) {
if( !(g_cpuConstRegs[_Rs_].SD[0] >= 0) )
@ -565,11 +565,11 @@ void recBLEZ()
_flushEEreg(_Rs_);
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]], 0 );
j8Ptr[ 0 ] = JL8( 0 );
j32Ptr[ 1 ] = JG32( 0 );
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0 );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]], 0 );
j32Ptr[ 2 ] = JNZ32( 0 );
x86SetJ8( j8Ptr[ 0 ] );
@ -611,11 +611,11 @@ void recBGTZ()
_flushEEreg(_Rs_);
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]], 0 );
j8Ptr[ 0 ] = JG8( 0 );
j32Ptr[ 1 ] = JL32( 0 );
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0 );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]], 0 );
j32Ptr[ 2 ] = JZ32( 0 );
x86SetJ8( j8Ptr[ 0 ] );
@ -793,11 +793,11 @@ void recBLEZL()
_flushEEreg(_Rs_);
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]], 0 );
j32Ptr[ 0 ] = JL32( 0 );
j32Ptr[ 1 ] = JG32( 0 );
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0 );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]], 0 );
j32Ptr[ 2 ] = JNZ32( 0 );
x86SetJ32( j32Ptr[ 0 ] );
@ -837,11 +837,11 @@ void recBGTZL()
_flushEEreg(_Rs_);
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], 0 );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]], 0 );
j32Ptr[ 0 ] = JG32( 0 );
j32Ptr[ 1 ] = JL32( 0 );
CMP32ItoM( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], 0 );
xCMP(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]], 0 );
j32Ptr[ 2 ] = JZ32( 0 );
x86SetJ32( j32Ptr[ 0 ] );

24
pcsx2/x86/ix86-32/iR5900Jump.cpp
View File

@ -69,8 +69,8 @@ void recJAL()
}
else
{
MOV32ItoM((uptr)&cpuRegs.GPR.r[31].UL[0], pc + 4);
MOV32ItoM((uptr)&cpuRegs.GPR.r[31].UL[1], 0);
xMOV(ptr32[&cpuRegs.GPR.r[31].UL[0]], pc + 4);
xMOV(ptr32[&cpuRegs.GPR.r[31].UL[1]], 0);
}
recompileNextInstruction(1);
@ -106,20 +106,20 @@ void recJALR()
// uncomment when there are NO instructions that need to call interpreter
// int mmreg;
// if( GPR_IS_CONST1(_Rs_) )
// MOV32ItoM( (u32)&cpuRegs.pc, g_cpuConstRegs[_Rs_].UL[0] );
// xMOV(ptr32[&cpuRegs.pc], g_cpuConstRegs[_Rs_].UL[0] );
// else {
// int mmreg;
//
// if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rs_, MODE_READ)) >= 0 ) {
// SSE_MOVSS_XMM_to_M32((u32)&cpuRegs.pc, mmreg);
// xMOVSS(ptr[&cpuRegs.pc], xRegisterSSE(mmreg));
// }
// else if( (mmreg = _checkMMXreg(MMX_GPR+_Rs_, MODE_READ)) >= 0 ) {
// MOVDMMXtoM((u32)&cpuRegs.pc, mmreg);
// xMOVD(ptr[&cpuRegs.pc], xRegisterMMX(mmreg));
// SetMMXstate();
// }
// else {
// MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
// MOV32RtoM((u32)&cpuRegs.pc, EAX);
// xMOV(eax, ptr[(void*)((int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] )]);
// xMOV(ptr[&cpuRegs.pc], eax);
// }
// }
@ -135,8 +135,8 @@ void recJALR()
}
else
{
MOV32ItoM((uptr)&cpuRegs.GPR.r[_Rd_].UL[0], newpc);
MOV32ItoM((uptr)&cpuRegs.GPR.r[_Rd_].UL[1], 0);
xMOV(ptr32[&cpuRegs.GPR.r[_Rd_].UL[0]], newpc);
xMOV(ptr32[&cpuRegs.GPR.r[_Rd_].UL[1]], 0);
}
}
@ -146,12 +146,12 @@ void recJALR()
if( x86regs[ESI].inuse ) {
pxAssert( x86regs[ESI].type == X86TYPE_PCWRITEBACK );
MOV32RtoM((uptr)&cpuRegs.pc, ESI);
xMOV(ptr[&cpuRegs.pc], esi);
x86regs[ESI].inuse = 0;
}
else {
MOV32MtoR(EAX, (uptr)&g_recWriteback);
MOV32RtoM((uptr)&cpuRegs.pc, EAX);
xMOV(eax, ptr[&g_recWriteback]);
xMOV(ptr[&cpuRegs.pc], eax);
}
SetBranchReg(0xffffffff);

8
pcsx2/x86/ix86-32/iR5900LoadStore.cpp
View File

@ -83,10 +83,10 @@ void _eeOnLoadWrite(u32 reg)
if( regt >= 0 ) {
if( xmmregs[regt].mode & MODE_WRITE ) {
if( reg != _Rs_ ) {
SSE2_PUNPCKHQDQ_XMM_to_XMM(regt, regt);
SSE2_MOVQ_XMM_to_M64((uptr)&cpuRegs.GPR.r[reg].UL[2], regt);
xPUNPCK.HQDQ(xRegisterSSE(regt), xRegisterSSE(regt));
xMOVQ(ptr[&cpuRegs.GPR.r[reg].UL[2]], xRegisterSSE(regt));
}
else SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[reg].UL[2], regt);
else xMOVH.PS(ptr[&cpuRegs.GPR.r[reg].UL[2]], xRegisterSSE(regt));
}
xmmregs[regt].inuse = 0;
}
@ -165,7 +165,7 @@ void recLoad32( u32 bits, bool sign )
// Load ECX with the source memory address that we're reading from.
_eeMoveGPRtoR(ECX, _Rs_);
if (_Imm_ != 0)
ADD32ItoR( ECX, _Imm_ );
xADD(ecx, _Imm_ );
_eeOnLoadWrite(_Rt_);
_deleteEEreg(_Rt_, 0);

188
pcsx2/x86/ix86-32/iR5900Move.cpp
View File

@ -66,7 +66,7 @@ void recLUI()
if( (mmreg = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_WRITE)) >= 0 ) {
if( xmmregs[mmreg].mode & MODE_WRITE ) {
SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[_Rt_].UL[2], mmreg);
xMOVH.PS(ptr[&cpuRegs.GPR.r[_Rt_].UL[2]], xRegisterSSE(mmreg));
}
xmmregs[mmreg].inuse = 0;
}
@ -80,10 +80,10 @@ void recLUI()
}
else
{
MOV32ItoR(EAX, (s32)(cpuRegs.code << 16));
CDQ();
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[0], EAX);
MOV32RtoM((uptr)&cpuRegs.GPR.r[_Rt_].UL[1], EDX);
xMOV(eax, (s32)(cpuRegs.code << 16));
xCDQ();
xMOV(ptr[&cpuRegs.GPR.r[_Rt_].UL[0]], eax);
xMOV(ptr[&cpuRegs.GPR.r[_Rt_].UL[1]], edx);
}
}
@ -107,21 +107,21 @@ void recMFHILO(int hi)
xmmregs[regd].inuse = 0;
SSE2_MOVQ_XMM_to_M64((uptr)&cpuRegs.GPR.r[_Rd_].UL[0], reghi);
xMOVQ(ptr[&cpuRegs.GPR.r[_Rd_].UL[0]], xRegisterSSE(reghi));
if( xmmregs[regd].mode & MODE_WRITE ) {
SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[_Rd_].UL[2], regd);
xMOVH.PS(ptr[&cpuRegs.GPR.r[_Rd_].UL[2]], xRegisterSSE(regd));
}
}
else {
regd = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rd_, MODE_WRITE);
if( regd >= 0 ) {
SSE2_MOVDQ2Q_XMM_to_MM(regd, reghi);
xMOVQ(xRegisterMMX(regd), xRegisterSSE(reghi));
}
else {
_deleteEEreg(_Rd_, 0);
SSE2_MOVQ_XMM_to_M64((uptr)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], reghi);
xMOVQ(ptr[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]], xRegisterSSE(reghi));
}
}
}
@ -133,14 +133,14 @@ void recMFHILO(int hi)
if( regd >= 0 ) {
if( EEINST_ISLIVE2(_Rd_) ) {
if( xmmregs[regd].mode & MODE_WRITE ) {
SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 2 ], regd);
xMOVH.PS(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 2 ]], xRegisterSSE(regd));
}
xmmregs[regd].inuse = 0;
MOVQRtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], reghi);
xMOVQ(ptr[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]], xRegisterMMX(reghi));
}
else {
SetMMXstate();
SSE2_MOVQ2DQ_MM_to_XMM(regd, reghi);
xMOVQ(xRegisterSSE(regd), xRegisterMMX(reghi));
xmmregs[regd].mode |= MODE_WRITE;
}
}
@ -149,32 +149,32 @@ void recMFHILO(int hi)
SetMMXstate();
if( regd >= 0 ) {
MOVQRtoR(regd, reghi);
xMOVQ(xRegisterMMX(regd), xRegisterMMX(reghi));
}
else {
_deleteEEreg(_Rd_, 0);
MOVQRtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], reghi);
xMOVQ(ptr[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]], xRegisterMMX(reghi));
}
}
}
else {
if( regd >= 0 ) {
if( EEINST_ISLIVE2(_Rd_) ) SSE_MOVLPS_M64_to_XMM(regd, hi ? (uptr)&cpuRegs.HI.UD[ 0 ] : (uptr)&cpuRegs.LO.UD[ 0 ]);
else SSE2_MOVQ_M64_to_XMM(regd, hi ? (uptr)&cpuRegs.HI.UD[ 0 ] : (uptr)&cpuRegs.LO.UD[ 0 ]);
if( EEINST_ISLIVE2(_Rd_) ) xMOVL.PS(xRegisterSSE(regd), ptr[(void*)(hi ? (uptr)&cpuRegs.HI.UD[ 0 ] : (uptr)&cpuRegs.LO.UD[ 0 ])]);
else xMOVQZX(xRegisterSSE(regd), ptr[(void*)(hi ? (uptr)&cpuRegs.HI.UD[ 0 ] : (uptr)&cpuRegs.LO.UD[ 0 ])]);
}
else {
regd = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rd_, MODE_WRITE);
if( regd >= 0 ) {
SetMMXstate();
MOVQMtoR(regd, hi ? (uptr)&cpuRegs.HI.UD[ 0 ] : (uptr)&cpuRegs.LO.UD[ 0 ]);
xMOVQ(xRegisterMMX(regd), ptr[(void*)(hi ? (uptr)&cpuRegs.HI.UD[ 0 ] : (uptr)&cpuRegs.LO.UD[ 0 ])]);
}
else {
_deleteEEreg(_Rd_, 0);
MOV32MtoR( EAX, hi ? (uptr)&cpuRegs.HI.UL[ 0 ] : (uptr)&cpuRegs.LO.UL[ 0 ]);
MOV32MtoR( EDX, hi ? (uptr)&cpuRegs.HI.UL[ 1 ] : (uptr)&cpuRegs.LO.UL[ 1 ]);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(eax, ptr[(void*)(hi ? (uptr)&cpuRegs.HI.UL[ 0 ] : (uptr)&cpuRegs.LO.UL[ 0 ])]);
xMOV(edx, ptr[(void*)(hi ? (uptr)&cpuRegs.HI.UL[ 1 ] : (uptr)&cpuRegs.LO.UL[ 1 ])]);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
}
}
@ -197,8 +197,8 @@ void recMTHILO(int hi)
pxAssert( reghi != regs );
_deleteGPRtoXMMreg(_Rs_, 0);
SSE2_PUNPCKHQDQ_XMM_to_XMM(reghi, reghi);
SSE2_PUNPCKLQDQ_XMM_to_XMM(regs, reghi);
xPUNPCK.HQDQ(xRegisterSSE(reghi), xRegisterSSE(reghi));
xPUNPCK.LQDQ(xRegisterSSE(regs), xRegisterSSE(reghi));
// swap regs
xmmregs[regs] = xmmregs[reghi];
@ -213,20 +213,20 @@ void recMTHILO(int hi)
if( EEINST_ISLIVE2(xmmhilo) ) {
if( xmmregs[reghi].mode & MODE_WRITE ) {
SSE_MOVHPS_XMM_to_M64(addrhilo+8, reghi);
xMOVH.PS(ptr[(void*)(addrhilo+8)], xRegisterSSE(reghi));
}
xmmregs[reghi].inuse = 0;
MOVQRtoM(addrhilo, regs);
xMOVQ(ptr[(void*)(addrhilo)], xRegisterMMX(regs));
}
else {
SetMMXstate();
SSE2_MOVQ2DQ_MM_to_XMM(reghi, regs);
xMOVQ(xRegisterSSE(reghi), xRegisterMMX(regs));
xmmregs[reghi].mode |= MODE_WRITE;
}
}
else {
_flushConstReg(_Rs_);
SSE_MOVLPS_M64_to_XMM(reghi, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ]);
xMOVL.PS(xRegisterSSE(reghi), ptr[&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ]]);
xmmregs[reghi].mode |= MODE_WRITE;
}
}
@ -237,44 +237,44 @@ void recMTHILO(int hi)
if( reghi >= 0 ) {
if( regs >= 0 ) {
//SetMMXstate();
SSE2_MOVDQ2Q_XMM_to_MM(reghi, regs);
xMOVQ(xRegisterMMX(reghi), xRegisterSSE(regs));
}
else {
regs = _checkMMXreg(MMX_GPR+_Rs_, MODE_WRITE);
if( regs >= 0 ) {
SetMMXstate();
MOVQRtoR(reghi, regs);
xMOVQ(xRegisterMMX(reghi), xRegisterMMX(regs));
}
else {
_flushConstReg(_Rs_);
MOVQMtoR(reghi, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ]);
xMOVQ(xRegisterMMX(reghi), ptr[&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ]]);
}
}
}
else {
if( regs >= 0 ) {
SSE2_MOVQ_XMM_to_M64(addrhilo, regs);
xMOVQ(ptr[(void*)(addrhilo)], xRegisterSSE(regs));
}
else {
regs = _checkMMXreg(MMX_GPR+_Rs_, MODE_WRITE);
if( regs >= 0 ) {
SetMMXstate();
MOVQRtoM(addrhilo, regs);
xMOVQ(ptr[(void*)(addrhilo)], xRegisterMMX(regs));
}
else {
if( GPR_IS_CONST1(_Rs_) ) {
MOV32ItoM(addrhilo, g_cpuConstRegs[_Rs_].UL[0] );
MOV32ItoM(addrhilo+4, g_cpuConstRegs[_Rs_].UL[1] );
xMOV(ptr32[(u32*)(addrhilo)], g_cpuConstRegs[_Rs_].UL[0] );
xMOV(ptr32[(u32*)(addrhilo+4)], g_cpuConstRegs[_Rs_].UL[1] );
}
else {
_eeMoveGPRtoR(ECX, _Rs_);
_flushEEreg(_Rs_);
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
MOV32MtoR( EDX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
MOV32RtoM( addrhilo, EAX );
MOV32RtoM( addrhilo+4, EDX );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]]);
xMOV(edx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]]);
xMOV(ptr[(void*)(addrhilo)], eax);
xMOV(ptr[(void*)(addrhilo+4)], edx);
}
}
}
@ -318,22 +318,22 @@ void recMFHILO1(int hi)
if( reghi >= 0 ) {
if( regd >= 0 ) {
SSE_MOVHLPS_XMM_to_XMM(regd, reghi);
xMOVHL.PS(xRegisterSSE(regd), xRegisterSSE(reghi));
xmmregs[regd].mode |= MODE_WRITE;
}
else {
_deleteEEreg(_Rd_, 0);
SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ], reghi);
xMOVH.PS(ptr[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]], xRegisterSSE(reghi));
}
}
else {
if( regd >= 0 ) {
if( EEINST_ISLIVE2(_Rd_) ) {
SSE2_PUNPCKHQDQ_M128_to_XMM(regd, hi ? (uptr)&cpuRegs.HI.UD[ 0 ] : (uptr)&cpuRegs.LO.UD[ 0 ]);
SSE2_PSHUFD_XMM_to_XMM(regd, regd, 0x4e);
xPUNPCK.HQDQ(xRegisterSSE(regd), ptr[(void*)(hi ? (uptr)&cpuRegs.HI.UD[ 0 ] : (uptr)&cpuRegs.LO.UD[ 0 ])]);
xPSHUF.D(xRegisterSSE(regd), xRegisterSSE(regd), 0x4e);
}
else {
SSE2_MOVQ_M64_to_XMM(regd, hi ? (uptr)&cpuRegs.HI.UD[ 1 ] : (uptr)&cpuRegs.LO.UD[ 1 ]);
xMOVQZX(xRegisterSSE(regd), ptr[(void*)(hi ? (uptr)&cpuRegs.HI.UD[ 1 ] : (uptr)&cpuRegs.LO.UD[ 1 ])]);
}
xmmregs[regd].mode |= MODE_WRITE;
@ -343,14 +343,14 @@ void recMFHILO1(int hi)
if( regd >= 0 ) {
SetMMXstate();
MOVQMtoR(regd, hi ? (uptr)&cpuRegs.HI.UD[ 1 ] : (uptr)&cpuRegs.LO.UD[ 1 ]);
xMOVQ(xRegisterMMX(regd), ptr[(void*)(hi ? (uptr)&cpuRegs.HI.UD[ 1 ] : (uptr)&cpuRegs.LO.UD[ 1 ])]);
}
else {
_deleteEEreg(_Rd_, 0);
MOV32MtoR( EAX, hi ? (uptr)&cpuRegs.HI.UL[ 2 ] : (uptr)&cpuRegs.LO.UL[ 2 ]);
MOV32MtoR( EDX, hi ? (uptr)&cpuRegs.HI.UL[ 3 ] : (uptr)&cpuRegs.LO.UL[ 3 ]);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(eax, ptr[(void*)(hi ? (uptr)&cpuRegs.HI.UL[ 2 ] : (uptr)&cpuRegs.LO.UL[ 2 ])]);
xMOV(edx, ptr[(void*)(hi ? (uptr)&cpuRegs.HI.UL[ 3 ] : (uptr)&cpuRegs.LO.UL[ 3 ])]);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
}
}
@ -369,35 +369,35 @@ void recMTHILO1(int hi)
if( reghi >= 0 ) {
if( regs >= 0 ) {
SSE2_PUNPCKLQDQ_XMM_to_XMM(reghi, regs);
xPUNPCK.LQDQ(xRegisterSSE(reghi), xRegisterSSE(regs));
}
else {
_flushEEreg(_Rs_);
SSE2_PUNPCKLQDQ_M128_to_XMM(reghi, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ]);
xPUNPCK.LQDQ(xRegisterSSE(reghi), ptr[&cpuRegs.GPR.r[ _Rs_ ].UD[ 0 ]]);
}
}
else {
if( regs >= 0 ) {
SSE2_MOVQ_XMM_to_M64(addrhilo+8, regs);
xMOVQ(ptr[(void*)(addrhilo+8)], xRegisterSSE(regs));
}
else {
regs = _checkMMXreg(MMX_GPR+_Rs_, MODE_WRITE);
if( regs >= 0 ) {
SetMMXstate();
MOVQRtoM(addrhilo+8, regs);
xMOVQ(ptr[(void*)(addrhilo+8)], xRegisterMMX(regs));
}
else {
if( GPR_IS_CONST1(_Rs_) ) {
MOV32ItoM(addrhilo+8, g_cpuConstRegs[_Rs_].UL[0] );
MOV32ItoM(addrhilo+12, g_cpuConstRegs[_Rs_].UL[1] );
xMOV(ptr32[(u32*)(addrhilo+8)], g_cpuConstRegs[_Rs_].UL[0] );
xMOV(ptr32[(u32*)(addrhilo+12)], g_cpuConstRegs[_Rs_].UL[1] );
}
else {
_flushEEreg(_Rs_);
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
MOV32MtoR( EDX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
MOV32RtoM( addrhilo+8, EAX );
MOV32RtoM( addrhilo+12, EDX );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]]);
xMOV(edx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]]);
xMOV(ptr[(void*)(addrhilo+8)], eax);
xMOV(ptr[(void*)(addrhilo+12)], edx);
}
}
}
@ -434,12 +434,12 @@ void recMOVZtemp_const()
void recMOVZtemp_consts(int info)
{
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
OR32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
xOR(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] ]);
j8Ptr[ 0 ] = JNZ8( 0 );
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0] );
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1] );
xMOV(ptr32[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], g_cpuConstRegs[_Rs_].UL[0] );
xMOV(ptr32[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], g_cpuConstRegs[_Rs_].UL[1] );
x86SetJ8( j8Ptr[ 0 ] );
}
@ -449,15 +449,15 @@ void recMOVZtemp_constt(int info)
// Fixme: MMX problem
if(0/* _hasFreeXMMreg() */) {
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
MOVQMtoR(t0reg, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
MOVQRtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], t0reg);
xMOVQ(xRegisterMMX(t0reg), ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]]);
xMOVQ(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], xRegisterMMX(t0reg));
_freeMMXreg(t0reg);
}
else {
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
MOV32MtoR(EDX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]]);
xMOV(edx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]]);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
}
@ -469,20 +469,20 @@ void recMOVZtemp_(int info)
if(0/* _hasFreeXMMreg() */)
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
OR32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
xOR(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] ]);
j8Ptr[ 0 ] = JNZ8( 0 );
if( t0reg >= 0 ) {
MOVQMtoR(t0reg, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
MOVQRtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], t0reg);
xMOVQ(xRegisterMMX(t0reg), ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]]);
xMOVQ(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], xRegisterMMX(t0reg));
_freeMMXreg(t0reg);
}
else {
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
MOV32MtoR(EDX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]]);
xMOV(edx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]]);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
x86SetJ8( j8Ptr[ 0 ] );
@ -513,12 +513,12 @@ void recMOVNtemp_const()
void recMOVNtemp_consts(int info)
{
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
OR32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
xOR(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] ]);
j8Ptr[ 0 ] = JZ8( 0 );
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0] );
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1] );
xMOV(ptr32[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], g_cpuConstRegs[_Rs_].UL[0] );
xMOV(ptr32[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], g_cpuConstRegs[_Rs_].UL[1] );
x86SetJ8( j8Ptr[ 0 ] );
}
@ -528,15 +528,15 @@ void recMOVNtemp_constt(int info)
// Fixme: MMX problem
if(0/* _hasFreeXMMreg() */) {
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
MOVQMtoR(t0reg, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
MOVQRtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], t0reg);
xMOVQ(xRegisterMMX(t0reg), ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]]);
xMOVQ(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], xRegisterMMX(t0reg));
_freeMMXreg(t0reg);
}
else {
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
MOV32MtoR(EDX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]]);
xMOV(edx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]]);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
}
@ -548,20 +548,20 @@ void recMOVNtemp_(int info)
if(0/* _hasFreeXMMreg() */)
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
OR32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
xOR(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] ]);
j8Ptr[ 0 ] = JZ8( 0 );
if( t0reg >= 0 ) {
MOVQMtoR(t0reg, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
MOVQRtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], t0reg);
xMOVQ(xRegisterMMX(t0reg), ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]]);
xMOVQ(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], xRegisterMMX(t0reg));
_freeMMXreg(t0reg);
}
else {
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
MOV32MtoR(EDX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]);
MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
MOV32RtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]]);
xMOV(edx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]]);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
x86SetJ8( j8Ptr[ 0 ] );

388
pcsx2/x86/ix86-32/iR5900MultDiv.cpp
View File

@ -61,7 +61,7 @@ void recWritebackHILO(int info, int writed, int upper)
u8 testlive = upper?EEINST_LIVE2:EEINST_LIVE0;
if( g_pCurInstInfo->regs[XMMGPR_HI] & testlive )
MOV32RtoR( ECX, EDX );
xMOV(ecx, edx);
if( g_pCurInstInfo->regs[XMMGPR_LO] & testlive ) {
@ -69,17 +69,17 @@ void recWritebackHILO(int info, int writed, int upper)
if( (reglo = _checkXMMreg(XMMTYPE_GPRREG, XMMGPR_LO, MODE_READ)) >= 0 ) {
if( xmmregs[reglo].mode & MODE_WRITE ) {
if( upper ) SSE2_MOVQ_XMM_to_M64(loaddr-8, reglo);
else SSE_MOVHPS_XMM_to_M64(loaddr+8, reglo);
if( upper ) xMOVQ(ptr[(void*)(loaddr-8)], xRegisterSSE(reglo));
else xMOVH.PS(ptr[(void*)(loaddr+8)], xRegisterSSE(reglo));
}
xmmregs[reglo].inuse = 0;
reglo = -1;
}
CDQ();
MOV32RtoM( loaddr, EAX );
MOV32RtoM( loaddr+4, EDX );
xCDQ();
xMOV(ptr[(void*)(loaddr)], eax);
xMOV(ptr[(void*)(loaddr+4)], edx);
savedlo = 1;
}
@ -92,7 +92,7 @@ void recWritebackHILO(int info, int writed, int upper)
if( savedlo ) {
regd = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_WRITE|MODE_READ);
if( regd >= 0 ) {
SSE_MOVLPS_M64_to_XMM(regd, loaddr);
xMOVL.PS(xRegisterSSE(regd), ptr[(void*)(loaddr)]);
}
}
}
@ -100,9 +100,9 @@ void recWritebackHILO(int info, int writed, int upper)
if( regd < 0 ) {
_deleteEEreg(_Rd_, 0);
if( !savedlo ) CDQ();
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
if( !savedlo ) xCDQ();
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
}
@ -111,17 +111,17 @@ void recWritebackHILO(int info, int writed, int upper)
if( (reghi = _checkXMMreg(XMMTYPE_GPRREG, XMMGPR_HI, MODE_READ)) >= 0 ) {
if( xmmregs[reghi].mode & MODE_WRITE ) {
if( upper ) SSE2_MOVQ_XMM_to_M64(hiaddr-8, reghi);
else SSE_MOVHPS_XMM_to_M64(hiaddr+8, reghi);
if( upper ) xMOVQ(ptr[(void*)(hiaddr-8)], xRegisterSSE(reghi));
else xMOVH.PS(ptr[(void*)(hiaddr+8)], xRegisterSSE(reghi));
}
xmmregs[reghi].inuse = 0;
reghi = -1;
}
MOV32RtoM(hiaddr, ECX );
SAR32ItoR(ECX, 31);
MOV32RtoM(hiaddr+4, ECX );
xMOV(ptr[(void*)(hiaddr)], ecx);
xSAR(ecx, 31);
xMOV(ptr[(void*)(hiaddr+4)], ecx);
}
}
@ -135,8 +135,8 @@ void recWritebackHILOMMX(int info, int regsource, int writed, int upper)
SetMMXstate();
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
MOVQRtoR(t0reg, regsource);
PSRADItoR(t0reg, 31); // shift in 0s
xMOVQ(xRegisterMMX(t0reg), xRegisterMMX(regsource));
xPSRA.D(xRegisterMMX(t0reg), 31); // shift in 0s
if( (g_pCurInstInfo->regs[XMMGPR_LO] & testlive) || (writed && _Rd_) ) {
if( (g_pCurInstInfo->regs[XMMGPR_HI] & testlive) )
@ -147,26 +147,26 @@ void recWritebackHILOMMX(int info, int regsource, int writed, int upper)
}
t1reg = _allocMMXreg(-1, MMX_TEMP, 0);
MOVQRtoR(t1reg, regsource);
xMOVQ(xRegisterMMX(t1reg), xRegisterMMX(regsource));
}
PUNPCKLDQRtoR(regsource, t0reg);
xPUNPCK.LDQ(xRegisterMMX(regsource), xRegisterMMX(t0reg));
}
if( g_pCurInstInfo->regs[XMMGPR_LO] & testlive ) {
int reglo;
if( !upper && (reglo = _allocCheckGPRtoMMX(g_pCurInstInfo, XMMGPR_LO, MODE_WRITE)) >= 0 ) {
MOVQRtoR(reglo, regsource);
xMOVQ(xRegisterMMX(reglo), xRegisterMMX(regsource));
}
else {
reglo = _checkXMMreg(XMMTYPE_GPRREG, XMMGPR_LO, MODE_READ);
MOVQRtoM(loaddr, regsource);
xMOVQ(ptr[(void*)(loaddr)], xRegisterMMX(regsource));
if( reglo >= 0 ) {
if( xmmregs[reglo].mode & MODE_WRITE ) {
if( upper ) SSE2_MOVQ_XMM_to_M64(loaddr-8, reglo);
else SSE_MOVHPS_XMM_to_M64(loaddr+8, reglo);
if( upper ) xMOVQ(ptr[(void*)(loaddr-8)], xRegisterSSE(reglo));
else xMOVH.PS(ptr[(void*)(loaddr+8)], xRegisterSSE(reglo));
}
xmmregs[reglo].inuse = 0;
reglo = -1;
@ -179,7 +179,7 @@ void recWritebackHILOMMX(int info, int regsource, int writed, int upper)
regd = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rd_, MODE_WRITE);
if( regd >= 0 ) {
if( regd != regsource ) MOVQRtoR(regd, regsource);
if( regd != regsource ) xMOVQ(xRegisterMMX(regd), xRegisterMMX(regsource));
}
else {
regd = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_READ);
@ -187,21 +187,21 @@ void recWritebackHILOMMX(int info, int regsource, int writed, int upper)
if( regd >= 0 ) {
if( g_pCurInstInfo->regs[XMMGPR_LO] & testlive ) {
// lo written
SSE_MOVLPS_M64_to_XMM(regd, loaddr);
xMOVL.PS(xRegisterSSE(regd), ptr[(void*)(loaddr)]);
xmmregs[regd].mode |= MODE_WRITE;
}
else {
MOVQRtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], regsource);
xMOVQ(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], xRegisterMMX(regsource));
if( xmmregs[regd].mode & MODE_WRITE ) {
SSE_MOVHPS_XMM_to_M64((uptr)&cpuRegs.GPR.r[_Rd_].UL[2], regd);
xMOVH.PS(ptr[&cpuRegs.GPR.r[_Rd_].UL[2]], xRegisterSSE(regd));
}
xmmregs[regd].inuse = 0;
}
}
else {
MOVQRtoM((uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], regsource);
xMOVQ(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], xRegisterMMX(regsource));
}
}
}
@ -211,24 +211,24 @@ void recWritebackHILOMMX(int info, int regsource, int writed, int upper)
int mmreg = -1, reghi;
if( t1reg >= 0 ) {
PUNPCKHDQRtoR(t1reg, t0reg);
xPUNPCK.HDQ(xRegisterMMX(t1reg), xRegisterMMX(t0reg));
mmreg = t1reg;
}
else {
// can't modify regsource
PUNPCKHDQRtoR(t0reg, regsource);
xPUNPCK.HDQ(xRegisterMMX(t0reg), xRegisterMMX(regsource));
mmreg = t0reg;
PSHUFWRtoR(t0reg, t0reg, 0x4e);
xPSHUF.W(xRegisterMMX(t0reg), xRegisterMMX(t0reg), 0x4e);
}
if( upper ) {
reghi = _checkXMMreg(XMMTYPE_GPRREG, XMMGPR_HI, MODE_READ);
if( reghi >= 0 ) {
if( xmmregs[reghi].mode & MODE_WRITE ) SSE2_MOVQ_XMM_to_M64(hiaddr-8, reghi);
if( xmmregs[reghi].mode & MODE_WRITE ) xMOVQ(ptr[(void*)(hiaddr-8)], xRegisterSSE(reghi));
xmmregs[reghi].inuse = 0;
}
MOVQRtoM(hiaddr, mmreg);
xMOVQ(ptr[(void*)(hiaddr)], xRegisterMMX(mmreg));
}
else {
_deleteGPRtoXMMreg(XMMGPR_HI, 2);
@ -261,12 +261,12 @@ void recWritebackConstHILO(u64 res, int writed, int upper)
if( reglo >= 0 ) {
u32* mem_ptr = recGetImm64(res & 0x80000000 ? -1 : 0, (u32)res);
if( upper ) SSE_MOVHPS_M64_to_XMM(reglo, (uptr)mem_ptr);
else SSE_MOVLPS_M64_to_XMM(reglo, (uptr)mem_ptr);
if( upper ) xMOVH.PS(xRegisterSSE(reglo), ptr[mem_ptr]);
else xMOVL.PS(xRegisterSSE(reglo), ptr[mem_ptr]);
}
else {
MOV32ItoM(loaddr, res & 0xffffffff);
MOV32ItoM(loaddr+4, (res&0x80000000)?0xffffffff:0);
xMOV(ptr32[(u32*)(loaddr)], res & 0xffffffff);
xMOV(ptr32[(u32*)(loaddr+4)], (res&0x80000000)?0xffffffff:0);
}
}
}
@ -281,13 +281,13 @@ void recWritebackConstHILO(u64 res, int writed, int upper)
if( reghi >= 0 ) {
u32* mem_ptr = recGetImm64((res >> 63) ? -1 : 0, res >> 32);
if( upper ) SSE_MOVHPS_M64_to_XMM(reghi, (uptr)mem_ptr);
else SSE_MOVLPS_M64_to_XMM(reghi, (uptr)mem_ptr);
if( upper ) xMOVH.PS(xRegisterSSE(reghi), ptr[mem_ptr]);
else xMOVL.PS(xRegisterSSE(reghi), ptr[mem_ptr]);
}
else {
_deleteEEreg(XMMGPR_HI, 0);
MOV32ItoM(hiaddr, res >> 32);
MOV32ItoM(hiaddr+4, (res>>63)?0xffffffff:0);
xMOV(ptr32[(u32*)(hiaddr)], res >> 32);
xMOV(ptr32[(u32*)(hiaddr+4)], (res>>63)?0xffffffff:0);
}
}
}
@ -308,16 +308,16 @@ void recMULTUsuper(int info, int upper, int process);
void recMULTsuper(int info, int upper, int process)
{
if( process & PROCESS_CONSTS ) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rs_].UL[0] );
IMUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rs_].UL[0] );
xMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
else if( process & PROCESS_CONSTT) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
IMUL32M( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rt_].UL[0] );
xMUL(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
IMUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
recWritebackHILO(info, 1, upper);
@ -397,16 +397,16 @@ void recMULTU_const()
void recMULTUsuper(int info, int upper, int process)
{
if( process & PROCESS_CONSTS ) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rs_].UL[0] );
MUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rs_].UL[0] );
xUMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
else if( process & PROCESS_CONSTT) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
MUL32M( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rt_].UL[0] );
xUMUL(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xUMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
recWritebackHILO(info, 1, upper);
@ -511,52 +511,52 @@ void recDIV_const()
void recDIVsuper(int info, int sign, int upper, int process)
{
if( process & PROCESS_CONSTT )
MOV32ItoR( ECX, g_cpuConstRegs[_Rt_].UL[0] );
xMOV(ecx, g_cpuConstRegs[_Rt_].UL[0] );
else
MOV32MtoR( ECX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(ecx, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
if( process & PROCESS_CONSTS )
MOV32ItoR( EAX, g_cpuConstRegs[_Rs_].UL[0] );
xMOV(eax, g_cpuConstRegs[_Rs_].UL[0] );
else
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
u8 *end1;
if (sign) //test for overflow (x86 will just throw an exception)
{
CMP32ItoR( EAX, 0x80000000 );
xCMP(eax, 0x80000000 );
u8 *cont1 = JNE8(0);
CMP32ItoR( ECX, 0xffffffff );
xCMP(ecx, 0xffffffff );
u8 *cont2 = JNE8(0);
//overflow case:
XOR32RtoR( EDX, EDX ); //EAX remains 0x80000000
xXOR(edx, edx); //EAX remains 0x80000000
end1 = JMP8(0);
x86SetJ8(cont1);
x86SetJ8(cont2);
}
CMP32ItoR( ECX, 0 );
xCMP(ecx, 0 );
u8 *cont3 = JNE8(0);
//divide by zero
MOV32RtoR( EDX, EAX );
xMOV(edx, eax);
if (sign) //set EAX to (EAX < 0)?1:-1
{
SAR32ItoR( EAX, 31 ); //(EAX < 0)?-1:0
SHL32ItoR( EAX, 1 ); //(EAX < 0)?-2:0
NOT32R( EAX ); //(EAX < 0)?1:-1
xSAR(eax, 31 ); //(EAX < 0)?-1:0
xSHL(eax, 1 ); //(EAX < 0)?-2:0
xNOT(eax); //(EAX < 0)?1:-1
}
else
MOV32ItoR( EAX, 0xffffffff );
xMOV(eax, 0xffffffff );
u8 *end2 = JMP8(0);
x86SetJ8(cont3);
if( sign ) {
CDQ();
IDIV32R( ECX );
xCDQ();
xDIV(ecx);
}
else {
XOR32RtoR( EDX, EDX );
DIV32R( ECX );
xXOR(edx, edx);
xUDIV(ecx);
}
if (sign) x86SetJ8( end1 );
@ -674,25 +674,25 @@ void recMADD()
_deleteEEreg(XMMGPR_HI, 1);
// dadd
MOV32MtoR( EAX, (uptr)&cpuRegs.LO.UL[ 0 ] );
MOV32MtoR( ECX, (uptr)&cpuRegs.HI.UL[ 0 ] );
ADD32ItoR( EAX, (u32)result&0xffffffff );
ADC32ItoR( ECX, (u32)(result>>32) );
CDQ();
xMOV(eax, ptr[&cpuRegs.LO.UL[ 0 ] ]);
xMOV(ecx, ptr[&cpuRegs.HI.UL[ 0 ] ]);
xADD(eax, (u32)result&0xffffffff );
xADC(ecx, (u32)(result>>32) );
xCDQ();
if( _Rd_) {
_eeOnWriteReg(_Rd_, 1);
_deleteEEreg(_Rd_, 0);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
MOV32RtoM( (uptr)&cpuRegs.LO.UL[0], EAX );
MOV32RtoM( (uptr)&cpuRegs.LO.UL[1], EDX );
xMOV(ptr[&cpuRegs.LO.UL[0]], eax);
xMOV(ptr[&cpuRegs.LO.UL[1]], edx);
MOV32RtoM( (uptr)&cpuRegs.HI.UL[0], ECX );
MOV32RtoR(EAX, ECX);
CDQ();
MOV32RtoM( (uptr)&cpuRegs.HI.UL[1], EDX );
xMOV(ptr[&cpuRegs.HI.UL[0]], ecx);
xMOV(eax, ecx);
xCDQ();
xMOV(ptr[&cpuRegs.HI.UL[1]], edx);
return;
}
@ -704,36 +704,36 @@ void recMADD()
_deleteMMXreg(MMX_GPR+_Rt_, 1);
if( GPR_IS_CONST1(_Rs_) ) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rs_].UL[0] );
IMUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rs_].UL[0] );
xMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
else if ( GPR_IS_CONST1(_Rt_) ) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
IMUL32M( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rt_].UL[0] );
xMUL(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
IMUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
MOV32RtoR( ECX, EDX );
ADD32MtoR( EAX, (uptr)&cpuRegs.LO.UL[0] );
ADC32MtoR( ECX, (uptr)&cpuRegs.HI.UL[0] );
CDQ();
xMOV(ecx, edx);
xADD(eax, ptr[&cpuRegs.LO.UL[0] ]);
xADC(ecx, ptr[&cpuRegs.HI.UL[0] ]);
xCDQ();
if( _Rd_ ) {
_eeOnWriteReg(_Rd_, 1);
_deleteEEreg(_Rd_, 0);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
MOV32RtoM( (uptr)&cpuRegs.LO.UL[0], EAX );
MOV32RtoM( (uptr)&cpuRegs.LO.UL[1], EDX );
xMOV(ptr[&cpuRegs.LO.UL[0]], eax);
xMOV(ptr[&cpuRegs.LO.UL[1]], edx);
MOV32RtoM( (uptr)&cpuRegs.HI.UL[0], ECX );
MOV32RtoR(EAX, ECX);
CDQ();
MOV32RtoM( (uptr)&cpuRegs.HI.UL[1], EDX );
xMOV(ptr[&cpuRegs.HI.UL[0]], ecx);
xMOV(eax, ecx);
xCDQ();
xMOV(ptr[&cpuRegs.HI.UL[1]], edx);
}
//static PCSX2_ALIGNED16(u32 s_MaddMask[]) = { 0x80000000, 0, 0x80000000, 0 };
@ -746,25 +746,25 @@ void recMADDU()
_deleteEEreg(XMMGPR_HI, 1);
// dadd
MOV32MtoR( EAX, (uptr)&cpuRegs.LO.UL[ 0 ] );
MOV32MtoR( ECX, (uptr)&cpuRegs.HI.UL[ 0 ] );
ADD32ItoR( EAX, (u32)result&0xffffffff );
ADC32ItoR( ECX, (u32)(result>>32) );
CDQ();
xMOV(eax, ptr[&cpuRegs.LO.UL[ 0 ] ]);
xMOV(ecx, ptr[&cpuRegs.HI.UL[ 0 ] ]);
xADD(eax, (u32)result&0xffffffff );
xADC(ecx, (u32)(result>>32) );
xCDQ();
if( _Rd_) {
_eeOnWriteReg(_Rd_, 1);
_deleteEEreg(_Rd_, 0);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
MOV32RtoM( (uptr)&cpuRegs.LO.UL[0], EAX );
MOV32RtoM( (uptr)&cpuRegs.LO.UL[1], EDX );
xMOV(ptr[&cpuRegs.LO.UL[0]], eax);
xMOV(ptr[&cpuRegs.LO.UL[1]], edx);
MOV32RtoM( (uptr)&cpuRegs.HI.UL[0], ECX );
MOV32RtoR(EAX, ECX);
CDQ();
MOV32RtoM( (uptr)&cpuRegs.HI.UL[1], EDX );
xMOV(ptr[&cpuRegs.HI.UL[0]], ecx);
xMOV(eax, ecx);
xCDQ();
xMOV(ptr[&cpuRegs.HI.UL[1]], edx);
return;
}
@ -776,36 +776,36 @@ void recMADDU()
_deleteMMXreg(MMX_GPR+_Rt_, 1);
if( GPR_IS_CONST1(_Rs_) ) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rs_].UL[0] );
MUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rs_].UL[0] );
xUMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
else if ( GPR_IS_CONST1(_Rt_) ) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
MUL32M( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rt_].UL[0] );
xUMUL(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xUMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
MOV32RtoR( ECX, EDX );
ADD32MtoR( EAX, (uptr)&cpuRegs.LO.UL[0] );
ADC32MtoR( ECX, (uptr)&cpuRegs.HI.UL[0] );
CDQ();
xMOV(ecx, edx);
xADD(eax, ptr[&cpuRegs.LO.UL[0] ]);
xADC(ecx, ptr[&cpuRegs.HI.UL[0] ]);
xCDQ();
if( _Rd_ ) {
_eeOnWriteReg(_Rd_, 1);
_deleteEEreg(_Rd_, 0);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
MOV32RtoM( (uptr)&cpuRegs.LO.UL[0], EAX );
MOV32RtoM( (uptr)&cpuRegs.LO.UL[1], EDX );
xMOV(ptr[&cpuRegs.LO.UL[0]], eax);
xMOV(ptr[&cpuRegs.LO.UL[1]], edx);
MOV32RtoM( (uptr)&cpuRegs.HI.UL[0], ECX );
MOV32RtoR(EAX, ECX);
CDQ();
MOV32RtoM( (uptr)&cpuRegs.HI.UL[1], EDX );
xMOV(ptr[&cpuRegs.HI.UL[0]], ecx);
xMOV(eax, ecx);
xCDQ();
xMOV(ptr[&cpuRegs.HI.UL[1]], edx);
}
void recMADD1()
@ -816,25 +816,25 @@ void recMADD1()
_deleteEEreg(XMMGPR_HI, 1);
// dadd
MOV32MtoR( EAX, (uptr)&cpuRegs.LO.UL[ 2 ] );
MOV32MtoR( ECX, (uptr)&cpuRegs.HI.UL[ 2 ] );
ADD32ItoR( EAX, (u32)result&0xffffffff );
ADC32ItoR( ECX, (u32)(result>>32) );
CDQ();
xMOV(eax, ptr[&cpuRegs.LO.UL[ 2 ] ]);
xMOV(ecx, ptr[&cpuRegs.HI.UL[ 2 ] ]);
xADD(eax, (u32)result&0xffffffff );
xADC(ecx, (u32)(result>>32) );
xCDQ();
if( _Rd_) {
_eeOnWriteReg(_Rd_, 1);
_deleteEEreg(_Rd_, 0);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
MOV32RtoM( (uptr)&cpuRegs.LO.UL[2], EAX );
MOV32RtoM( (uptr)&cpuRegs.LO.UL[3], EDX );
xMOV(ptr[&cpuRegs.LO.UL[2]], eax);
xMOV(ptr[&cpuRegs.LO.UL[3]], edx);
MOV32RtoM( (uptr)&cpuRegs.HI.UL[2], ECX );
MOV32RtoR(EAX, ECX);
CDQ();
MOV32RtoM( (uptr)&cpuRegs.HI.UL[3], EDX );
xMOV(ptr[&cpuRegs.HI.UL[2]], ecx);
xMOV(eax, ecx);
xCDQ();
xMOV(ptr[&cpuRegs.HI.UL[3]], edx);
return;
}
@ -846,36 +846,36 @@ void recMADD1()
_deleteMMXreg(MMX_GPR+_Rt_, 1);
if( GPR_IS_CONST1(_Rs_) ) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rs_].UL[0] );
IMUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rs_].UL[0] );
xMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
else if ( GPR_IS_CONST1(_Rt_) ) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
IMUL32M( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rt_].UL[0] );
xMUL(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
IMUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
MOV32RtoR( ECX, EDX );
ADD32MtoR( EAX, (uptr)&cpuRegs.LO.UL[2] );
ADC32MtoR( ECX, (uptr)&cpuRegs.HI.UL[2] );
CDQ();
xMOV(ecx, edx);
xADD(eax, ptr[&cpuRegs.LO.UL[2] ]);
xADC(ecx, ptr[&cpuRegs.HI.UL[2] ]);
xCDQ();
if( _Rd_ ) {
_eeOnWriteReg(_Rd_, 1);
_deleteEEreg(_Rd_, 0);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
MOV32RtoM( (uptr)&cpuRegs.LO.UL[2], EAX );
MOV32RtoM( (uptr)&cpuRegs.LO.UL[3], EDX );
xMOV(ptr[&cpuRegs.LO.UL[2]], eax);
xMOV(ptr[&cpuRegs.LO.UL[3]], edx);
MOV32RtoM( (uptr)&cpuRegs.HI.UL[2], ECX );
MOV32RtoR(EAX, ECX);
CDQ();
MOV32RtoM( (uptr)&cpuRegs.HI.UL[3], EDX );
xMOV(ptr[&cpuRegs.HI.UL[2]], ecx);
xMOV(eax, ecx);
xCDQ();
xMOV(ptr[&cpuRegs.HI.UL[3]], edx);
}
//static PCSX2_ALIGNED16(u32 s_MaddMask[]) = { 0x80000000, 0, 0x80000000, 0 };
@ -888,25 +888,25 @@ void recMADDU1()
_deleteEEreg(XMMGPR_HI, 1);
// dadd
MOV32MtoR( EAX, (uptr)&cpuRegs.LO.UL[ 2 ] );
MOV32MtoR( ECX, (uptr)&cpuRegs.HI.UL[ 2 ] );
ADD32ItoR( EAX, (u32)result&0xffffffff );
ADC32ItoR( ECX, (u32)(result>>32) );
CDQ();
xMOV(eax, ptr[&cpuRegs.LO.UL[ 2 ] ]);
xMOV(ecx, ptr[&cpuRegs.HI.UL[ 2 ] ]);
xADD(eax, (u32)result&0xffffffff );
xADC(ecx, (u32)(result>>32) );
xCDQ();
if( _Rd_) {
_eeOnWriteReg(_Rd_, 1);
_deleteEEreg(_Rd_, 0);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
MOV32RtoM( (uptr)&cpuRegs.LO.UL[2], EAX );
MOV32RtoM( (uptr)&cpuRegs.LO.UL[3], EDX );
xMOV(ptr[&cpuRegs.LO.UL[2]], eax);
xMOV(ptr[&cpuRegs.LO.UL[3]], edx);
MOV32RtoM( (uptr)&cpuRegs.HI.UL[2], ECX );
MOV32RtoR(EAX, ECX);
CDQ();
MOV32RtoM( (uptr)&cpuRegs.HI.UL[3], EDX );
xMOV(ptr[&cpuRegs.HI.UL[2]], ecx);
xMOV(eax, ecx);
xCDQ();
xMOV(ptr[&cpuRegs.HI.UL[3]], edx);
return;
}
@ -918,36 +918,36 @@ void recMADDU1()
_deleteMMXreg(MMX_GPR+_Rt_, 1);
if( GPR_IS_CONST1(_Rs_) ) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rs_].UL[0] );
MUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rs_].UL[0] );
xUMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
else if ( GPR_IS_CONST1(_Rt_) ) {
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
MUL32M( (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(eax, g_cpuConstRegs[_Rt_].UL[0] );
xUMUL(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
}
else {
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MUL32M( (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xUMUL(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
}
MOV32RtoR( ECX, EDX );
ADD32MtoR( EAX, (uptr)&cpuRegs.LO.UL[2] );
ADC32MtoR( ECX, (uptr)&cpuRegs.HI.UL[2] );
CDQ();
xMOV(ecx, edx);
xADD(eax, ptr[&cpuRegs.LO.UL[2] ]);
xADC(ecx, ptr[&cpuRegs.HI.UL[2] ]);
xCDQ();
if( _Rd_ ) {
_eeOnWriteReg(_Rd_, 1);
_deleteEEreg(_Rd_, 0);
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
MOV32RtoM( (uptr)&cpuRegs.LO.UL[2], EAX );
MOV32RtoM( (uptr)&cpuRegs.LO.UL[3], EDX );
xMOV(ptr[&cpuRegs.LO.UL[2]], eax);
xMOV(ptr[&cpuRegs.LO.UL[3]], edx);
MOV32RtoM( (uptr)&cpuRegs.HI.UL[2], ECX );
MOV32RtoR(EAX, ECX);
CDQ();
MOV32RtoM( (uptr)&cpuRegs.HI.UL[3], EDX );
xMOV(ptr[&cpuRegs.HI.UL[2]], ecx);
xMOV(eax, ecx);
xCDQ();
xMOV(ptr[&cpuRegs.HI.UL[3]], edx);
}

210
pcsx2/x86/ix86-32/iR5900Shift.cpp
View File

@ -64,15 +64,15 @@ void recSLLs_(int info, int sa)
{
pxAssert( !(info & PROCESS_EE_XMM) );
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
if ( sa != 0 )
{
SHL32ItoR( EAX, sa );
xSHL(eax, sa );
}
CDQ( );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xCDQ( );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
void recSLL_(int info)
@ -92,12 +92,12 @@ void recSRLs_(int info, int sa)
{
pxAssert( !(info & PROCESS_EE_XMM) );
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( sa != 0 ) SHR32ItoR( EAX, sa);
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
if ( sa != 0 ) xSHR(eax, sa);
CDQ( );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xCDQ( );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
void recSRL_(int info)
@ -117,12 +117,12 @@ void recSRAs_(int info, int sa)
{
pxAssert( !(info & PROCESS_EE_XMM) );
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( sa != 0 ) SAR32ItoR( EAX, sa);
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
if ( sa != 0 ) xSAR(eax, sa);
CDQ();
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xCDQ();
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
void recSRA_(int info)
@ -149,8 +149,8 @@ void recDSLLs_(int info, int sa)
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
PSLLQItoR(rdreg, sa);
if( rtreg != rdreg ) xMOVQ(xRegisterMMX(rdreg), xRegisterMMX(rtreg));
xPSLL.Q(xRegisterMMX(rdreg), sa);
}
void recDSLL_(int info)
@ -177,8 +177,8 @@ void recDSRLs_(int info, int sa)
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
PSRLQItoR(rdreg, sa);
if( rtreg != rdreg ) xMOVQ(xRegisterMMX(rdreg), xRegisterMMX(rtreg));
xPSRL.Q(xRegisterMMX(rdreg), sa);
}
void recDSRL_(int info)
@ -205,19 +205,19 @@ void recDSRAs_(int info, int sa)
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
if( rtreg != rdreg ) xMOVQ(xRegisterMMX(rdreg), xRegisterMMX(rtreg));
if ( sa != 0 ) {
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
MOVQRtoR(t0reg, rtreg);
xMOVQ(xRegisterMMX(t0reg), xRegisterMMX(rtreg));
// it is a signed shift
PSRADItoR(t0reg, sa);
PSRLQItoR(rdreg, sa);
xPSRA.D(xRegisterMMX(t0reg), sa);
xPSRL.Q(xRegisterMMX(rdreg), sa);
PUNPCKHDQRtoR(t0reg, t0reg); // shift to lower
xPUNPCK.HDQ(xRegisterMMX(t0reg), xRegisterMMX(t0reg)); // shift to lower
// take lower dword of rdreg and lower dword of t0reg
PUNPCKLDQRtoR(rdreg, t0reg);
xPUNPCK.LDQ(xRegisterMMX(rdreg), xRegisterMMX(t0reg));
_freeMMXreg(t0reg);
}
@ -240,13 +240,13 @@ void recDSLL32s_(int info, int sa)
{
pxAssert( !(info & PROCESS_EE_XMM) );
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
if ( sa != 0 )
{
SHL32ItoR( EAX, sa );
xSHL(eax, sa );
}
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 0 );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EAX );
xMOV(ptr32[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], 0 );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], eax);
}
@ -267,11 +267,11 @@ void recDSRL32s_(int info, int sa)
{
pxAssert( !(info & PROCESS_EE_XMM) );
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
if ( sa != 0 ) SHR32ItoR( EAX, sa );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] ]);
if ( sa != 0 ) xSHR(eax, sa );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32ItoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 0 );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr32[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], 0 );
}
void recDSRL32_(int info)
@ -291,12 +291,12 @@ void recDSRA32s_(int info, int sa)
{
pxAssert( !(info & PROCESS_EE_XMM) );
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
CDQ( );
if ( sa != 0 ) SAR32ItoR( EAX, sa );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] ]);
xCDQ( );
if ( sa != 0 ) xSAR(eax, sa );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
@ -325,12 +325,12 @@ int recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp, int
SetMMXstate();
*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[_Rs_].UL[0]);
AND32ItoR(EAX, shift64?0x3f:0x1f);
MOVD32RtoMMX(*rstemp, EAX);
xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
xAND(eax, shift64?0x3f:0x1f);
xMOVDZX(xRegisterMMX(*rstemp), eax);
*rsreg = *rstemp;
if( *rtreg != *rdreg ) MOVQRtoR(*rdreg, *rtreg);
if( *rtreg != *rdreg ) xMOVQ(xRegisterMMX(*rdreg), xRegisterMMX(*rtreg));
return 1;
}
@ -341,9 +341,9 @@ void recSetConstShiftV(int info, int* rsreg, int* rdreg, int* rstemp, int shift6
SetMMXstate();
*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
MOV32MtoR(EAX, (uptr)&cpuRegs.GPR.r[_Rs_].UL[0]);
AND32ItoR(EAX, shift64?0x3f:0x1f);
MOVD32RtoMMX(*rstemp, EAX);
xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
xAND(eax, shift64?0x3f:0x1f);
xMOVDZX(xRegisterMMX(*rstemp), eax);
*rsreg = *rstemp;
_flushConstReg(_Rt_);
@ -362,27 +362,27 @@ void recSLLV_consts(int info)
void recSLLV_constt(int info)
{
MOV32MtoR( ECX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(ecx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
AND32ItoR( ECX, 0x1f );
SHL32CLtoR( EAX );
xMOV(eax, g_cpuConstRegs[_Rt_].UL[0] );
xAND(ecx, 0x1f );
xSHL(eax, cl);
eeSignExtendTo(_Rd_);
}
void recSLLV_(int info)
{
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
if ( _Rs_ != 0 )
{
MOV32MtoR( ECX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
AND32ItoR( ECX, 0x1f );
SHL32CLtoR( EAX );
xMOV(ecx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xAND(ecx, 0x1f );
xSHL(eax, cl);
}
CDQ();
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xCDQ();
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
EERECOMPILE_CODE0(SLLV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
@ -400,27 +400,27 @@ void recSRLV_consts(int info)
void recSRLV_constt(int info)
{
MOV32MtoR( ECX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(ecx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
AND32ItoR( ECX, 0x1f );
SHR32CLtoR( EAX );
xMOV(eax, g_cpuConstRegs[_Rt_].UL[0] );
xAND(ecx, 0x1f );
xSHR(eax, cl);
eeSignExtendTo(_Rd_);
}
void recSRLV_(int info)
{
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
if ( _Rs_ != 0 )
{
MOV32MtoR( ECX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
AND32ItoR( ECX, 0x1f );
SHR32CLtoR( EAX );
xMOV(ecx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xAND(ecx, 0x1f );
xSHR(eax, cl);
}
CDQ( );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xCDQ( );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
EERECOMPILE_CODE0(SRLV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
@ -438,27 +438,27 @@ void recSRAV_consts(int info)
void recSRAV_constt(int info)
{
MOV32MtoR( ECX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
xMOV(ecx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
AND32ItoR( ECX, 0x1f );
SAR32CLtoR( EAX );
xMOV(eax, g_cpuConstRegs[_Rt_].UL[0] );
xAND(ecx, 0x1f );
xSAR(eax, cl);
eeSignExtendTo(_Rd_);
}
void recSRAV_(int info)
{
MOV32MtoR( EAX, (uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
xMOV(eax, ptr[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] ]);
if ( _Rs_ != 0 )
{
MOV32MtoR( ECX, (uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
AND32ItoR( ECX, 0x1f );
SAR32CLtoR( EAX );
xMOV(ecx, ptr[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ]);
xAND(ecx, 0x1f );
xSAR(eax, cl);
}
CDQ( );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (uptr)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
xCDQ( );
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]], eax);
xMOV(ptr[&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]], edx);
}
EERECOMPILE_CODE0(SRAV, XMMINFO_READS|XMMINFO_READT|XMMINFO_WRITED);
@ -481,8 +481,8 @@ void recDSLLV_constt(int info)
int rsreg, rdreg, rstemp = -1;
recSetConstShiftV(info, &rsreg, &rdreg, &rstemp, 1);
MOVQMtoR(rdreg, (uptr)&cpuRegs.GPR.r[_Rt_]);
PSLLQRtoR(rdreg, rsreg);
xMOVQ(xRegisterMMX(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]);
xPSLL.Q(xRegisterMMX(rdreg), xRegisterMMX(rsreg));
if( rstemp != -1 ) _freeMMXreg(rstemp);
}
@ -491,7 +491,7 @@ void recDSLLV_(int info)
int rsreg, rtreg, rdreg, rstemp = -1;
recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 1);
PSLLQRtoR(rdreg, rsreg);
xPSLL.Q(xRegisterMMX(rdreg), xRegisterMMX(rsreg));
if( rstemp != -1 ) _freeMMXreg(rstemp);
}
@ -515,8 +515,8 @@ void recDSRLV_constt(int info)
int rsreg, rdreg, rstemp = -1;
recSetConstShiftV(info, &rsreg, &rdreg, &rstemp, 1);
MOVQMtoR(rdreg, (uptr)&cpuRegs.GPR.r[_Rt_]);
PSRLQRtoR(rdreg, rsreg);
xMOVQ(xRegisterMMX(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]);
xPSRL.Q(xRegisterMMX(rdreg), xRegisterMMX(rsreg));
if( rstemp != -1 ) _freeMMXreg(rstemp);
}
@ -525,7 +525,7 @@ void recDSRLV_(int info)
int rsreg, rtreg, rdreg, rstemp = -1;
recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 1);
PSRLQRtoR(rdreg, rsreg);
xPSRL.Q(xRegisterMMX(rdreg), xRegisterMMX(rsreg));
if( rstemp != -1 ) _freeMMXreg(rstemp);
}
@ -552,24 +552,24 @@ void recDSRAV_constt(int info)
recSetConstShiftV(info, &rsreg, &rdreg, &rstemp, 1);
MOVQMtoR(rdreg, (uptr)&cpuRegs.GPR.r[_Rt_]);
PXORRtoR(t0reg, t0reg);
xMOVQ(xRegisterMMX(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]);
xPXOR(xRegisterMMX(t0reg), xRegisterMMX(t0reg));
// calc high bit
MOVQRtoR(t1reg, rdreg);
PCMPGTDRtoR(t0reg, rdreg);
PUNPCKHDQRtoR(t0reg, t0reg); // shift to lower
xMOVQ(xRegisterMMX(t1reg), xRegisterMMX(rdreg));
xPCMP.GTD(xRegisterMMX(t0reg), xRegisterMMX(rdreg));
xPUNPCK.HDQ(xRegisterMMX(t0reg), xRegisterMMX(t0reg)); // shift to lower
// shift highest bit, 64 - eax
MOV32ItoR(EAX, 64);
MOVD32RtoMMX(t1reg, EAX);
PSUBDRtoR(t1reg, rsreg);
xMOV(eax, 64);
xMOVDZX(xRegisterMMX(t1reg), eax);
xPSUB.D(xRegisterMMX(t1reg), xRegisterMMX(rsreg));
// right logical shift
PSRLQRtoR(rdreg, rsreg);
PSLLQRtoR(t0reg, t1reg); // highest bits
xPSRL.Q(xRegisterMMX(rdreg), xRegisterMMX(rsreg));
xPSLL.Q(xRegisterMMX(t0reg), xRegisterMMX(t1reg)); // highest bits
PORRtoR(rdreg, t0reg);
xPOR(xRegisterMMX(rdreg), xRegisterMMX(t0reg));
_freeMMXreg(t0reg);
_freeMMXreg(t1reg);
@ -583,23 +583,23 @@ void recDSRAV_(int info)
t1reg = _allocMMXreg(-1, MMX_TEMP, 0);
recSetShiftV(info, &rsreg, &rtreg, &rdreg, &rstemp, 1);
PXORRtoR(t0reg, t0reg);
xPXOR(xRegisterMMX(t0reg), xRegisterMMX(t0reg));
// calc high bit
MOVQRtoR(t1reg, rdreg);
PCMPGTDRtoR(t0reg, rdreg);
PUNPCKHDQRtoR(t0reg, t0reg); // shift to lower
xMOVQ(xRegisterMMX(t1reg), xRegisterMMX(rdreg));
xPCMP.GTD(xRegisterMMX(t0reg), xRegisterMMX(rdreg));
xPUNPCK.HDQ(xRegisterMMX(t0reg), xRegisterMMX(t0reg)); // shift to lower
// shift highest bit, 64 - eax
MOV32ItoR(EAX, 64);
MOVD32RtoMMX(t1reg, EAX);
PSUBDRtoR(t1reg, rsreg);
xMOV(eax, 64);
xMOVDZX(xRegisterMMX(t1reg), eax);
xPSUB.D(xRegisterMMX(t1reg), xRegisterMMX(rsreg));
// right logical shift
PSRLQRtoR(rdreg, rsreg);
PSLLQRtoR(t0reg, t1reg); // highest bits
xPSRL.Q(xRegisterMMX(rdreg), xRegisterMMX(rsreg));
xPSLL.Q(xRegisterMMX(t0reg), xRegisterMMX(t1reg)); // highest bits
PORRtoR(rdreg, t0reg);
xPOR(xRegisterMMX(rdreg), xRegisterMMX(t0reg));
_freeMMXreg(t0reg);
_freeMMXreg(t1reg);

8
pcsx2/x86/ix86-32/iR5900Templates.cpp
View File

@ -527,15 +527,15 @@ int eeRecompileCodeXMM(int xmminfo)
// flush consts
if( xmminfo & XMMINFO_READT ) {
if( GPR_IS_CONST1( _Rt_ ) && !(g_cpuFlushedConstReg&(1<<_Rt_)) ) {
MOV32ItoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], g_cpuConstRegs[_Rt_].UL[0]);
MOV32ItoM((uptr)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], g_cpuConstRegs[_Rt_].UL[1]);
xMOV(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]], g_cpuConstRegs[_Rt_].UL[0]);
xMOV(ptr32[&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]], g_cpuConstRegs[_Rt_].UL[1]);
g_cpuFlushedConstReg |= (1<<_Rt_);
}
}
if( xmminfo & XMMINFO_READS) {
if( GPR_IS_CONST1( _Rs_ ) && !(g_cpuFlushedConstReg&(1<<_Rs_)) ) {
MOV32ItoM((uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0]);
MOV32ItoM((uptr)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1]);
xMOV(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]], g_cpuConstRegs[_Rs_].UL[0]);
xMOV(ptr32[&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ]], g_cpuConstRegs[_Rs_].UL[1]);
g_cpuFlushedConstReg |= (1<<_Rs_);
}
}

2
pcsx2/x86/ix86-32/recVTLB.cpp
View File

@ -72,7 +72,7 @@ static void iMOV128_SSE( const xIndirectVoid& destRm, const xIndirectVoid& srcRm
// if neither MMX nor SSE is available to the task.
//
// Optimizations: This method uses MMX is the cpu is in MMX mode, or SSE if it's in FPU
// mode (saving on potential EMMS uses).
// mode (saving on potential xEMMS uses).
//
static void iMOV64_Smart( const xIndirectVoid& destRm, const xIndirectVoid& srcRm )
{

22
pcsx2/x86/sVU_Debug.h
View File

@ -19,8 +19,8 @@
_freeXMMregs(/*&VU*/); \
_freeMMXregs(); \
SetFPUstate();) \
MOV32ItoM((uptr)&VU.code, (u32)VU.code); \
CALLFunc((uptr)VU##MI_##f); \
xMOV(ptr32[&VU.code], (u32)VU.code); \
xCALL((void*)(uptr)VU##MI_##f); \
}
#define REC_VUOPs(VU, f) { \
@ -28,12 +28,12 @@
_freeMMXregs(); \
SetFPUstate();) \
if (VU==&VU1) { \
MOV32ItoM((uptr)&VU1.code, (u32)VU1.code); \
CALLFunc((uptr)VU1MI_##f); \
xMOV(ptr32[&VU1.code], (u32)VU1.code); \
xCALL((void*)(uptr)VU1MI_##f); \
} \
else { \
MOV32ItoM((uptr)&VU0.code, (u32)VU0.code); \
CALLFunc((uptr)VU0MI_##f); \
xMOV(ptr32[&VU0.code], (u32)VU0.code); \
xCALL((void*)(uptr)VU0MI_##f); \
} \
}
@ -41,16 +41,16 @@
_freeXMMregs(/*&VU*/); \
_freeMMXregs(); \
SetFPUstate(); \
MOV32ItoM((uptr)&VU.code, (u32)VU.code); \
CALLFunc((uptr)VU##MI_##f); \
xMOV(ptr32[&VU.code], (u32)VU.code); \
xCALL((void*)(uptr)VU##MI_##f); \
}
#define REC_VUBRANCH(VU, f) { \
_freeXMMregs(/*&VU*/); \
_freeMMXregs(); \
SetFPUstate(); \
MOV32ItoM((uptr)&VU.code, (u32)VU.code); \
MOV32ItoM((uptr)&VU.VI[REG_TPC].UL, (u32)pc); \
CALLFunc((uptr)VU##MI_##f); \
xMOV(ptr32[&VU.code], (u32)VU.code); \
xMOV(ptr32[&VU.VI[REG_TPC].UL], (u32)pc); \
xCALL((void*)(uptr)VU##MI_##f); \
branch = 1; \
}

768
pcsx2/x86/sVU_Lower.cpp
View File

File diff suppressed because it is too large Load Diff

992
pcsx2/x86/sVU_Micro.cpp
View File

File diff suppressed because it is too large Load Diff

1362
pcsx2/x86/sVU_Upper.cpp
View File

File diff suppressed because it is too large Load Diff

318
pcsx2/x86/sVU_zerorec.cpp
View File

@ -2621,36 +2621,36 @@ void SuperVUFlush(int p, int wait)
if (recwait == 0)
{
// write didn't happen this block
MOV32MtoR(EAX, p ? (uptr)&s_writeP : (uptr)&s_writeQ);
OR32RtoR(EAX, EAX);
xMOV(eax, ptr[(void*)(p ? (uptr)&s_writeP : (uptr)&s_writeQ)]);
xOR(eax, eax);
pjmp[0] = JS8(0);
if (s_pCurInst->info.cycle) SUB32ItoR(EAX, s_pCurInst->info.cycle);
if (s_pCurInst->info.cycle) xSUB(eax, s_pCurInst->info.cycle);
// if writeQ <= total+offset
if (!wait) // only write back if time is up
{
CMP32MtoR(EAX, (uptr)&s_TotalVUCycles);
xCMP(eax, ptr[&s_TotalVUCycles]);
pjmp[1] = JG8(0);
}
else
{
// add (writeQ-total-offset) to s_TotalVUCycles
// necessary?
CMP32MtoR(EAX, (uptr)&s_TotalVUCycles);
xCMP(eax, ptr[&s_TotalVUCycles]);
pjmp[2] = JLE8(0);
MOV32RtoM((uptr)&s_TotalVUCycles, EAX);
xMOV(ptr[&s_TotalVUCycles], eax);
x86SetJ8(pjmp[2]);
}
}
else if (wait && s_pCurInst->info.cycle < recwait)
{
ADD32ItoM((uptr)&s_TotalVUCycles, recwait);
xADD(ptr32[&s_TotalVUCycles], recwait);
}
MOV32MtoR(EAX, SuperVUGetVIAddr(p ? REG_P : REG_Q, 0));
MOV32ItoM(p ? (uptr)&s_writeP : (uptr)&s_writeQ, 0x80000000);
MOV32RtoM(SuperVUGetVIAddr(p ? REG_P : REG_Q, 1), EAX);
xMOV(eax, ptr[(void*)(SuperVUGetVIAddr(p ? REG_P : REG_Q, 0))]);
xMOV(ptr32[(u32*)(p ? (uptr)&s_writeP : (uptr)&s_writeQ)], 0x80000000);
xMOV(ptr[(void*)(SuperVUGetVIAddr(p ? REG_P : REG_Q, 1))], eax);
if (recwait == 0)
{
@ -2717,10 +2717,10 @@ static void SuperVURecompile()
{
pxAssert(pchild->blocks.size() == 0);
AND32ItoM((uptr)&VU0.VI[ REG_VPU_STAT ].UL, s_vu ? ~0x100 : ~0x001); // E flag
//AND32ItoM((uptr)&VU->GetVifRegs().stat, ~VIF1_STAT_VEW);
xAND(ptr32[&VU0.VI[ REG_VPU_STAT ].UL], s_vu ? ~0x100 : ~0x001); // E flag
//xAND(ptr32[(&VU->GetVifRegs().stat)], ~VIF1_STAT_VEW);
MOV32ItoM((uptr)&VU->VI[REG_TPC], pchild->endpc);
xMOV(ptr32[(&VU->VI[REG_TPC])], pchild->endpc);
JMP32((uptr)SuperVUEndProgram - ((uptr)x86Ptr + 5));
}
// only other case is when there are two branches
@ -2820,12 +2820,12 @@ void SuperVUFreeXMMregs(u32* livevars)
if (xmmregs[i].mode & MODE_VUZ)
{
SSE_MOVHPS_XMM_to_M64(addr, (x86SSERegType)i);
SSE_SHUFPS_M128_to_XMM((x86SSERegType)i, addr, 0xc4);
xMOVH.PS(ptr[(void*)(addr)], xRegisterSSE((x86SSERegType)i));
xSHUF.PS(xRegisterSSE((x86SSERegType)i), ptr[(void*)(addr)], 0xc4);
}
else
{
SSE_MOVHPS_M64_to_XMM((x86SSERegType)i, addr + 8);
xMOVH.PS(xRegisterSSE((x86SSERegType)i), ptr[(void*)(addr + 8)]);
}
xmmregs[i].mode &= ~MODE_VUXYZ;
@ -2848,16 +2848,16 @@ void SuperVUTestVU0Condition(u32 incstack)
// sometimes games spin on vu0, so be careful with
// runCycles value... woody hangs if too high
// Edit: Need to test this again, if anyone ever has a "Woody" game :p
MOV32RtoM((uptr)&backupEAX, EAX);
MOV32MtoR(EAX, (uptr)&s_TotalVUCycles);
CMP32MtoR(EAX, (uptr)&runCycles);
MOV32MtoR(EAX, (uptr)&backupEAX);
xMOV(ptr[&backupEAX], eax);
xMOV(eax, ptr[&s_TotalVUCycles]);
xCMP(eax, ptr[&runCycles]);
xMOV(eax, ptr[&backupEAX]);
if (incstack)
{
u8* jptr = JB8(0);
ADD32ItoR(ESP, incstack);
//CALLFunc((u32)timeout);
xADD(esp, incstack);
//xCALL((void*)(u32)timeout);
JMP32((uptr)SuperVUEndProgram - ((uptr)x86Ptr + 5));
x86SetJ8(jptr);
@ -2873,9 +2873,9 @@ void VuBaseBlock::Recompile()
pcode = x86Ptr;
#ifdef PCSX2_DEBUG
MOV32ItoM((uptr)&s_vufnheader, s_pFnHeader->startpc);
MOV32ItoM((uptr)&VU->VI[REG_TPC], startpc);
MOV32ItoM((uptr)&s_svulast, startpc);
xMOV(ptr32[&s_vufnheader], s_pFnHeader->startpc);
xMOV(ptr32[(&VU->VI[REG_TPC])], startpc);
xMOV(ptr32[&s_svulast], startpc);
std::list<VuBaseBlock*>::iterator itparent;
for (itparent = parents.begin(); itparent != parents.end(); ++itparent)
@ -2883,12 +2883,12 @@ void VuBaseBlock::Recompile()
if ((*itparent)->blocks.size() == 1 && (*itparent)->blocks.front()->startpc == startpc &&
((*itparent)->insts.size() < 2 || (----(*itparent)->insts.end())->regs[0].pipe != VUPIPE_BRANCH))
{
MOV32ItoM((uptr)&skipparent, (*itparent)->startpc);
xMOV(ptr32[&skipparent], (*itparent)->startpc);
break;
}
}
if (itparent == parents.end()) MOV32ItoM((uptr)&skipparent, -1);
if (itparent == parents.end()) xMOV(ptr32[&skipparent], -1);
xMOV( ecx, s_vu );
xCALL( svudispfn );
@ -2954,35 +2954,35 @@ void VuBaseBlock::Recompile()
// flush flags
if (s_PrevClipWrite != (uptr)&VU->VI[REG_CLIP_FLAG])
{
MOV32MtoR(EAX, s_PrevClipWrite);
MOV32RtoM((uptr)&VU->VI[REG_CLIP_FLAG], EAX);
xMOV(eax, ptr[(void*)(s_PrevClipWrite)]);
xMOV(ptr[(&VU->VI[REG_CLIP_FLAG])], eax);
}
if (s_PrevStatusWrite != (uptr)&VU->VI[REG_STATUS_FLAG])
{
MOV32MtoR(EAX, s_PrevStatusWrite);
MOV32RtoM((uptr)&VU->VI[REG_STATUS_FLAG], EAX);
xMOV(eax, ptr[(void*)(s_PrevStatusWrite)]);
xMOV(ptr[(&VU->VI[REG_STATUS_FLAG])], eax);
}
if (s_PrevMACWrite != (uptr)&VU->VI[REG_MAC_FLAG])
{
MOV32MtoR(EAX, s_PrevMACWrite);
MOV32RtoM((uptr)&VU->VI[REG_MAC_FLAG], EAX);
xMOV(eax, ptr[(void*)(s_PrevMACWrite)]);
xMOV(ptr[(&VU->VI[REG_MAC_FLAG])], eax);
}
// if( s_StatusRead != (uptr)&VU->VI[REG_STATUS_FLAG] ) {
// // only lower 8 bits valid!
// MOVZX32M8toR(EAX, s_StatusRead);
// MOV32RtoM((uptr)&VU->VI[REG_STATUS_FLAG], EAX);
// xMOVZX(eax, ptr8[(u8*)(s_StatusRead)]);
// xMOV(ptr[(&VU->VI[REG_STATUS_FLAG])], eax);
// }
// if( s_MACRead != (uptr)&VU->VI[REG_MAC_FLAG] ) {
// // only lower 8 bits valid!
// MOVZX32M8toR(EAX, s_MACRead);
// MOV32RtoM((uptr)&VU->VI[REG_MAC_FLAG], EAX);
// xMOVZX(eax, ptr8[(u8*)(s_MACRead)]);
// xMOV(ptr[(&VU->VI[REG_MAC_FLAG])], eax);
// }
if (s_PrevIWrite != (uptr)&VU->VI[REG_I])
{
MOV32ItoM((uptr)&VU->VI[REG_I], *(u32*)s_PrevIWrite); // never changes
xMOV(ptr32[(&VU->VI[REG_I])], *(u32*)s_PrevIWrite); // never changes
}
ADD32ItoM((uptr)&s_TotalVUCycles, cycles);
xADD(ptr32[&s_TotalVUCycles], cycles);
// compute branches, jumps, eop
if (type & BLOCKTYPE_HASEOP)
@ -2990,10 +2990,10 @@ void VuBaseBlock::Recompile()
// end
_freeXMMregs();
_freeX86regs();
AND32ItoM((uptr)&VU0.VI[ REG_VPU_STAT ].UL, s_vu ? ~0x100 : ~0x001); // E flag
//AND32ItoM((uptr)&VU->GetVifRegs().stat, ~VIF1_STAT_VEW);
xAND(ptr32[&VU0.VI[ REG_VPU_STAT ].UL], s_vu ? ~0x100 : ~0x001); // E flag
//xAND(ptr32[(&VU->GetVifRegs().stat)], ~VIF1_STAT_VEW);
if (!g_branch) MOV32ItoM((uptr)&VU->VI[REG_TPC], endpc);
if (!g_branch) xMOV(ptr32[(&VU->VI[REG_TPC])], endpc);
JMP32((uptr)SuperVUEndProgram - ((uptr)x86Ptr + 5));
}
@ -3059,7 +3059,7 @@ void VuBaseBlock::Recompile()
{
x86regs[s_JumpX86].inuse = 0;
x86regs[EAX].inuse = 1;
MOV32RtoR(EAX, s_JumpX86);
xMOV(eax, xRegister32(s_JumpX86));
s_JumpX86 = EAX;
}
@ -3104,7 +3104,7 @@ void VuBaseBlock::Recompile()
#endif
// store the last block executed
MOV32ItoM((uptr)&g_nLastBlockExecuted, s_pCurBlock->startpc);
xMOV(ptr32[&g_nLastBlockExecuted], s_pCurBlock->startpc);
switch (g_branch)
{
@ -3130,8 +3130,8 @@ void VuBaseBlock::Recompile()
SuperVUTestVU0Condition(8);
// already onto stack
CALLFunc((uptr)SuperVUGetProgram);
ADD32ItoR(ESP, 8);
xCALL((void*)(uptr)SuperVUGetProgram);
xADD(esp, 8);
JMPR(EAX);
break;
}
@ -3141,7 +3141,7 @@ void VuBaseBlock::Recompile()
// s32 delta = (s32)(VU->code & 0x400 ? 0xfffffc00 | (VU->code & 0x3ff) : VU->code & 0x3ff) << 3;
// ADD32ItoRmOffset(ESP, delta, 0);
ADD32ItoR(ESP, 8); // restore
xADD(esp, 8); // restore
pChildJumps[0] = (u32*)((uptr)JMP32(0) | 0x80000000);
break;
}
@ -3338,12 +3338,12 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
if (s_ClipRead == 0)
s_ClipRead = (uptr) & VU->VI[REG_CLIP_FLAG];
CMP32ItoM((uptr)&g_nLastBlockExecuted, nParentCheckForExecution);
xCMP(ptr32[&g_nLastBlockExecuted], nParentCheckForExecution);
u8* jptr = JNE8(0);
CMP32ItoM((uptr)&s_ClipRead, (uptr)&VU->VI[REG_CLIP_FLAG]);
xCMP(ptr32[&s_ClipRead], (uptr)&VU->VI[REG_CLIP_FLAG]);
u8* jptr2 = JE8(0);
MOV32MtoR(EAX, pparentinst->pClipWrite);
MOV32RtoM(s_ClipRead, EAX);
xMOV(eax, ptr[(void*)(pparentinst->pClipWrite)]);
xMOV(ptr[(void*)(s_ClipRead)], eax);
x86SetJ8(jptr);
x86SetJ8(jptr2);
}
@ -3376,14 +3376,14 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
if (pparentinst->pStatusWrite == 0)
{
pparentinst->pStatusWrite = (uptr)SuperVUStaticAlloc(4);
//MOV32ItoM(pparentinst->pStatusWrite, 0);
//xMOV(ptr32[(u32*)(pparentinst->pStatusWrite)], 0);
}
// if( s_pCurBlock->prevFlagsOutOfBlock && s_StatusRead != NULL ) {
// // or instead since don't now which parent we came from
// MOV32MtoR(EAX, pparentinst->pStatusWrite);
// OR32RtoM(s_StatusRead, EAX);
// MOV32ItoM(pparentinst->pStatusWrite, 0);
// xMOV(eax, ptr[(void*)(pparentinst->pStatusWrite)]);
// xOR(ptr[(void*)(s_StatusRead)], eax);
// xMOV(ptr32[(u32*)(pparentinst->pStatusWrite)], 0);
// }
if (nParentCheckForExecution >= 0)
@ -3392,27 +3392,27 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
// don't now which parent we came from, so have to check
// uptr tempstatus = (uptr)SuperVUStaticAlloc(4);
// if( s_StatusRead != NULL )
// MOV32MtoR(EAX, s_StatusRead);
// xMOV(eax, ptr[(void*)(s_StatusRead)]);
// else
// MOV32MtoR(EAX, (uptr)&VU->VI[REG_STATUS_FLAG]);
// xMOV(eax, ptr[(&VU->VI[REG_STATUS_FLAG])]);
// s_StatusRead = tempstatus;
if (s_StatusRead == 0)
s_StatusRead = (uptr) & VU->VI[REG_STATUS_FLAG];
CMP32ItoM((uptr)&g_nLastBlockExecuted, nParentCheckForExecution);
xCMP(ptr32[&g_nLastBlockExecuted], nParentCheckForExecution);
u8* jptr = JNE8(0);
MOV32MtoR(EAX, pparentinst->pStatusWrite);
MOV32ItoM(pparentinst->pStatusWrite, 0);
MOV32RtoM(s_StatusRead, EAX);
xMOV(eax, ptr[(void*)(pparentinst->pStatusWrite)]);
xMOV(ptr32[(u32*)(pparentinst->pStatusWrite)], 0);
xMOV(ptr[(void*)(s_StatusRead)], eax);
x86SetJ8(jptr);
}
else
{
uptr tempstatus = (uptr)SuperVUStaticAlloc(4);
MOV32MtoR(EAX, pparentinst->pStatusWrite);
MOV32RtoM(tempstatus, EAX);
MOV32ItoM(pparentinst->pStatusWrite, 0);
xMOV(eax, ptr[(void*)(pparentinst->pStatusWrite)]);
xMOV(ptr[(void*)(tempstatus)], eax);
xMOV(ptr32[(u32*)(pparentinst->pStatusWrite)], 0);
s_StatusRead = tempstatus;
}
@ -3428,9 +3428,9 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
// if( pc >= (u32)s_pCurBlock->endpc-8 ) {
// // towards the end, so variable might be leaded to another block (silent hill 4)
// uptr tempstatus = (uptr)SuperVUStaticAlloc(4);
// MOV32MtoR(EAX, s_StatusRead);
// MOV32RtoM(tempstatus, EAX);
// MOV32ItoM(s_StatusRead, 0);
// xMOV(eax, ptr[(void*)(s_StatusRead)]);
// xMOV(ptr[(void*)(tempstatus)], eax);
// xMOV(ptr32[(u32*)(s_StatusRead)], 0);
// s_StatusRead = tempstatus;
// }
}
@ -3451,14 +3451,14 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
if (pparentinst->pMACWrite == 0)
{
pparentinst->pMACWrite = (uptr)SuperVUStaticAlloc(4);
//MOV32ItoM(pparentinst->pMACWrite, 0);
//xMOV(ptr32[(u32*)(pparentinst->pMACWrite)], 0);
}
// if( s_pCurBlock->prevFlagsOutOfBlock && s_MACRead != NULL ) {
// // or instead since don't now which parent we came from
// MOV32MtoR(EAX, pparentinst->pMACWrite);
// OR32RtoM(s_MACRead, EAX);
// MOV32ItoM(pparentinst->pMACWrite, 0);
// xMOV(eax, ptr[(void*)(pparentinst->pMACWrite)]);
// xOR(ptr[(void*)(s_MACRead)], eax);
// xMOV(ptr32[(u32*)(pparentinst->pMACWrite)], 0);
// }
if (nParentCheckForExecution >= 0)
{
@ -3466,26 +3466,26 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
// don't now which parent we came from, so have to check
// uptr tempmac = (uptr)SuperVUStaticAlloc(4);
// if( s_MACRead != NULL )
// MOV32MtoR(EAX, s_MACRead);
// xMOV(eax, ptr[(void*)(s_MACRead)]);
// else
// MOV32MtoR(EAX, (uptr)&VU->VI[REG_MAC_FLAG]);
// xMOV(eax, ptr[(&VU->VI[REG_MAC_FLAG])]);
// s_MACRead = tempmac;
if (s_MACRead == 0) s_MACRead = (uptr) & VU->VI[REG_MAC_FLAG];
CMP32ItoM((uptr)&g_nLastBlockExecuted, nParentCheckForExecution);
xCMP(ptr32[&g_nLastBlockExecuted], nParentCheckForExecution);
u8* jptr = JNE8(0);
MOV32MtoR(EAX, pparentinst->pMACWrite);
MOV32ItoM(pparentinst->pMACWrite, 0);
MOV32RtoM(s_MACRead, EAX);
xMOV(eax, ptr[(void*)(pparentinst->pMACWrite)]);
xMOV(ptr32[(u32*)(pparentinst->pMACWrite)], 0);
xMOV(ptr[(void*)(s_MACRead)], eax);
x86SetJ8(jptr);
}
else
{
uptr tempMAC = (uptr)SuperVUStaticAlloc(4);
MOV32MtoR(EAX, pparentinst->pMACWrite);
MOV32RtoM(tempMAC, EAX);
MOV32ItoM(pparentinst->pMACWrite, 0);
xMOV(eax, ptr[(void*)(pparentinst->pMACWrite)]);
xMOV(ptr[(void*)(tempMAC)], eax);
xMOV(ptr32[(u32*)(pparentinst->pMACWrite)], 0);
s_MACRead = tempMAC;
}
@ -3497,9 +3497,9 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
// if( pc >= (u32)s_pCurBlock->endpc-8 ) {
// // towards the end, so variable might be leaked to another block (silent hill 4)
// uptr tempMAC = (uptr)SuperVUStaticAlloc(4);
// MOV32MtoR(EAX, s_MACRead);
// MOV32RtoM(tempMAC, EAX);
// MOV32ItoM(s_MACRead, 0);
// xMOV(eax, ptr[(void*)(s_MACRead)]);
// xMOV(ptr[(void*)(tempMAC)], eax);
// xMOV(ptr32[(u32*)(s_MACRead)], 0);
// s_MACRead = tempMAC;
// }
}
@ -3515,9 +3515,9 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
{
// make sure to reset the mac and status flags! (katamari)
if (pparentinst->pStatusWrite)
MOV32ItoM(pparentinst->pStatusWrite, 0);
xMOV(ptr32[(u32*)(pparentinst->pStatusWrite)], 0);
if (pparentinst->pMACWrite)
MOV32ItoM(pparentinst->pMACWrite, 0);
xMOV(ptr32[(u32*)(pparentinst->pMACWrite)], 0);
}
pxAssert(s_ClipRead != 0);
@ -3530,7 +3530,7 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
s_pCurBlock->prevFlagsOutOfBlock = 0;
if( IsDebugBuild )
MOV32ItoR(EAX, pc);
xMOV(eax, pc);
pxAssert(!(type & (INST_CLIP_WRITE | INST_STATUS_WRITE | INST_MAC_WRITE)));
pc += 8;
@ -3544,12 +3544,12 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
if (pMACWrite == 0)
{
pMACWrite = (uptr)SuperVUStaticAlloc(4);
//MOV32ItoM(pMACWrite, 0);
//xMOV(ptr32[(u32*)(pMACWrite)], 0);
}
if (pStatusWrite == 0)
{
pStatusWrite = (uptr)SuperVUStaticAlloc(4);
//MOV32ItoM(pStatusWrite, 0);
//xMOV(ptr32[(u32*)(pStatusWrite)], 0);
}
}
else
@ -3564,7 +3564,7 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
if ((pClipWrite == 0) && ((regs[0].VIwrite | regs[1].VIwrite) & (1 << REG_CLIP_FLAG)))
{
pClipWrite = (uptr)SuperVUStaticAlloc(4);
//MOV32ItoM(pClipWrite, 0);
//xMOV(ptr32[(u32*)(pClipWrite)], 0);
}
#ifdef SUPERVU_X86CACHING
@ -3592,22 +3592,22 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
if (s_vu == 0 && (code_ptr[1] & 0x20000000)) // M flag
{
OR8ItoM((uptr)&VU->flags, VUFLAG_MFLAGSET);
xOR(ptr8[(u8*)((uptr)&VU->flags)], VUFLAG_MFLAGSET);
}
if (code_ptr[1] & 0x10000000) // D flag
{
TEST32ItoM((uptr)&VU0.VI[REG_FBRST].UL, s_vu ? 0x400 : 0x004);
xTEST(ptr32[&VU0.VI[REG_FBRST].UL], s_vu ? 0x400 : 0x004);
u8* jptr = JZ8(0);
OR32ItoM((uptr)&VU0.VI[REG_VPU_STAT].UL, s_vu ? 0x200 : 0x002);
xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], s_vu ? 0x200 : 0x002);
xMOV( ecx, s_vu ? INTC_VU1 : INTC_VU0 );
xCALL( hwIntcIrq );
x86SetJ8(jptr);
}
if (code_ptr[1] & 0x08000000) // T flag
{
TEST32ItoM((uptr)&VU0.VI[REG_FBRST].UL, s_vu ? 0x800 : 0x008);
xTEST(ptr32[&VU0.VI[REG_FBRST].UL], s_vu ? 0x800 : 0x008);
u8* jptr = JZ8(0);
OR32ItoM((uptr)&VU0.VI[REG_VPU_STAT].UL, s_vu ? 0x400 : 0x004);
xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], s_vu ? 0x400 : 0x004);
xMOV( ecx, s_vu ? INTC_VU1 : INTC_VU0 );
xCALL( hwIntcIrq );
x86SetJ8(jptr);
@ -3674,25 +3674,25 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
// new is written so flush old
// if type & INST_Q_READ, already flushed
if (!(type & INST_Q_READ) && s_recWriteQ == 0) MOV32MtoR(EAX, (uptr)&s_writeQ);
if (!(type & INST_Q_READ) && s_recWriteQ == 0) xMOV(eax, ptr[&s_writeQ]);
if (cacheq)
MOV32MtoR(x86temp, (uptr)&s_TotalVUCycles);
xMOV(xRegister32(x86temp), ptr[&s_TotalVUCycles]);
if (!(type & INST_Q_READ))
{
if (s_recWriteQ == 0)
{
OR32RtoR(EAX, EAX);
xOR(eax, eax);
pjmp = JS8(0);
MOV32MtoR(EAX, SuperVUGetVIAddr(REG_Q, 0));
MOV32RtoM(SuperVUGetVIAddr(REG_Q, 1), EAX);
xMOV(eax, ptr[(void*)(SuperVUGetVIAddr(REG_Q, 0))]);
xMOV(ptr[(void*)(SuperVUGetVIAddr(REG_Q, 1))], eax);
x86SetJ8(pjmp);
}
else if (s_needFlush & 1)
{
MOV32MtoR(EAX, SuperVUGetVIAddr(REG_Q, 0));
MOV32RtoM(SuperVUGetVIAddr(REG_Q, 1), EAX);
xMOV(eax, ptr[(void*)(SuperVUGetVIAddr(REG_Q, 0))]);
xMOV(ptr[(void*)(SuperVUGetVIAddr(REG_Q, 1))], eax);
s_needFlush &= ~1;
}
}
@ -3701,8 +3701,8 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
if (cacheq)
{
pxAssert(s_pCurInst->pqcycles > 1);
ADD32ItoR(x86temp, s_pCurInst->info.cycle + s_pCurInst->pqcycles);
MOV32RtoM((uptr)&s_writeQ, x86temp);
xADD(xRegister32(x86temp), s_pCurInst->info.cycle + s_pCurInst->pqcycles);
xMOV(ptr[&s_writeQ], xRegister32(x86temp));
s_needFlush |= 1;
}
else
@ -3710,7 +3710,7 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
// won't be writing back
s_WriteToReadQ = 1;
s_needFlush &= ~1;
MOV32ItoM((uptr)&s_writeQ, 0x80000001);
xMOV(ptr32[&s_writeQ], 0x80000001);
}
s_recWriteQ = s_pCurInst->info.cycle + s_pCurInst->pqcycles;
@ -3725,31 +3725,31 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
// new is written so flush old
if (!(type & INST_P_READ) && s_recWriteP == 0)
MOV32MtoR(EAX, (uptr)&s_writeP);
MOV32MtoR(x86temp, (uptr)&s_TotalVUCycles);
xMOV(eax, ptr[&s_writeP]);
xMOV(xRegister32(x86temp), ptr[&s_TotalVUCycles]);
if (!(type & INST_P_READ))
{
if (s_recWriteP == 0)
{
OR32RtoR(EAX, EAX);
xOR(eax, eax);
pjmp = JS8(0);
MOV32MtoR(EAX, SuperVUGetVIAddr(REG_P, 0));
MOV32RtoM(SuperVUGetVIAddr(REG_P, 1), EAX);
xMOV(eax, ptr[(void*)(SuperVUGetVIAddr(REG_P, 0))]);
xMOV(ptr[(void*)(SuperVUGetVIAddr(REG_P, 1))], eax);
x86SetJ8(pjmp);
}
else if (s_needFlush & 2)
{
MOV32MtoR(EAX, SuperVUGetVIAddr(REG_P, 0));
MOV32RtoM(SuperVUGetVIAddr(REG_P, 1), EAX);
xMOV(eax, ptr[(void*)(SuperVUGetVIAddr(REG_P, 0))]);
xMOV(ptr[(void*)(SuperVUGetVIAddr(REG_P, 1))], eax);
s_needFlush &= ~2;
}
}
// write new P
pxAssert(s_pCurInst->pqcycles > 1);
ADD32ItoR(x86temp, s_pCurInst->info.cycle + s_pCurInst->pqcycles);
MOV32RtoM((uptr)&s_writeP, x86temp);
xADD(xRegister32(x86temp), s_pCurInst->info.cycle + s_pCurInst->pqcycles);
xMOV(ptr[&s_writeP], xRegister32(x86temp));
s_needFlush |= 2;
s_recWriteP = s_pCurInst->info.cycle + s_pCurInst->pqcycles;
@ -3791,7 +3791,7 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
pxAssert(vfflush[0] >= 0);
if (modewrite)
{
SSE_MOVAPS_XMM_to_M128((uptr)&VU->VF[regs[1].VFwrite], (x86SSERegType)vfwrite[1]);
xMOVAPS(ptr[(&VU->VF[regs[1].VFwrite])], xRegisterSSE((x86SSERegType)vfwrite[1]));
}
vfregstore = 1;
}
@ -3817,7 +3817,7 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
if (vfregstore)
{
// load
SSE_MOVAPS_M128_to_XMM(vfflush[0], (uptr)&VU->VF[regs[1].VFwrite]);
xMOVAPS(xRegisterSSE(vfflush[0]), ptr[(&VU->VF[regs[1].VFwrite])]);
pxAssert(xmmregs[vfwrite[1]].mode & MODE_WRITE);
@ -3848,7 +3848,7 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
{
pxAssert(vicached >= 0);
int cachedreg = _allocX86reg(-1, X86TYPE_VI | (s_vu ? X86TYPE_VU1 : 0), vicached, MODE_READ);
MOV32RtoM((uptr)&s_VIBranchDelay, cachedreg);
xMOV(ptr[&s_VIBranchDelay], xRegister32(cachedreg));
}
#endif
@ -3858,7 +3858,7 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
// itinst2 = itinst; ++itinst2;
// if( itinst2->regs[0].pipe == VUPIPE_BRANCH && (itinst->regs[0].VIwrite&itinst2->regs[0].VIread) ) {
//
// CALLFunc((u32)branchfn);
// xCALL((void*)(u32)branchfn);
// pxAssert( itinst->regs[0].VIwrite & 0xffff );
// Console.WriteLn("vi write before branch");
// for(s_CacheVIReg = 0; s_CacheVIReg < 16; ++s_CacheVIReg) {
@ -3868,7 +3868,7 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
//
// oldreg = _allocX86reg(-1, X86TYPE_VI|(s_vu?X86TYPE_VU1:0), s_CacheVIReg, MODE_READ);
// s_CacheVIX86 = _allocX86reg(-1, X86TYPE_VITEMP, s_CacheVIReg, MODE_WRITE);
// MOV32RtoR(s_CacheVIX86, oldreg);
// xMOV(xRegister32(s_CacheVIX86), xRegister32(oldreg));
// }
// }
// else if( pc == s_pCurBlock->endpc-8 && s_CacheVIReg >= 0 ) {
@ -3938,8 +3938,8 @@ void recVUMI_BranchHandle()
pxAssert(s_JumpX86 > 0);
if ((s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 || SUPERVU_CHECKCONDITION)
MOV32ItoM(SuperVUGetVIAddr(REG_TPC, 0), bpc);
MOV32ItoR(s_JumpX86, 1); // use 1 to disable optimization to XOR
xMOV(ptr32[(u32*)(SuperVUGetVIAddr(REG_TPC, 0))], bpc);
xMOV(xRegister32(s_JumpX86), 1); // use 1 to disable optimization to XOR
s_pCurBlock->pChildJumps[curjump] = (u32*)x86Ptr - 1;
if (!(s_pCurInst->type & INST_BRANCH_DELAY))
@ -3948,8 +3948,8 @@ void recVUMI_BranchHandle()
x86SetJ8(j8Ptr[ 0 ]);
if ((s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 || SUPERVU_CHECKCONDITION)
MOV32ItoM(SuperVUGetVIAddr(REG_TPC, 0), pc + 8);
MOV32ItoR(s_JumpX86, 1); // use 1 to disable optimization to XOR
xMOV(ptr32[(u32*)(SuperVUGetVIAddr(REG_TPC, 0))], pc + 8);
xMOV(xRegister32(s_JumpX86), 1); // use 1 to disable optimization to XOR
s_pCurBlock->pChildJumps[curjump+1] = (u32*)x86Ptr - 1;
x86SetJ8(j8Ptr[ 1 ]);
@ -3982,9 +3982,9 @@ void recVUMI_IBQ_prep()
if (itreg >= 0)
{
CMP16ItoR(itreg, 0);
xCMP(xRegister16(itreg), 0);
}
else CMP16ItoM(SuperVUGetVIAddr(_It_, 1), 0);
else xCMP(ptr16[(u16*)(SuperVUGetVIAddr(_It_, 1))], 0);
}
else if (_It_ == 0)
{
@ -4003,9 +4003,9 @@ void recVUMI_IBQ_prep()
if (isreg >= 0)
{
CMP16ItoR(isreg, 0);
xCMP(xRegister16(isreg), 0);
}
else CMP16ItoM(SuperVUGetVIAddr(_Is_, 1), 0);
else xCMP(ptr16[(u16*)(SuperVUGetVIAddr(_Is_, 1))], 0);
}
else
@ -4034,7 +4034,7 @@ void recVUMI_IBQ_prep()
if (s_pCurInst->vicached >= 0 && s_pCurInst->vicached == (s8)_Is_)
{
isreg = _allocX86reg(-1, X86TYPE_TEMP, 0, MODE_READ | MODE_WRITE);
MOV32MtoR(isreg, SuperVUGetVIAddr(_Is_, 1));
xMOV(xRegister32(isreg), ptr[(void*)(SuperVUGetVIAddr(_Is_, 1))]);
}
else
isreg = _allocX86reg(-1, X86TYPE_VI | (VU == &VU1 ? X86TYPE_VU1 : 0), _Is_, MODE_READ);
@ -4052,18 +4052,18 @@ void recVUMI_IBQ_prep()
{
if (itreg >= 0)
{
CMP16RtoR(isreg, itreg);
xCMP(xRegister16(isreg), xRegister16(itreg));
}
else CMP16MtoR(isreg, SuperVUGetVIAddr(_It_, 1));
else xCMP(xRegister16(isreg), ptr[(void*)(SuperVUGetVIAddr(_It_, 1))]);
}
else if (itreg >= 0)
{
CMP16MtoR(itreg, SuperVUGetVIAddr(_Is_, 1));
xCMP(xRegister16(itreg), ptr[(void*)(SuperVUGetVIAddr(_Is_, 1))]);
}
else
{
isreg = _allocX86reg(-1, X86TYPE_VI | (VU == &VU1 ? X86TYPE_VU1 : 0), _Is_, MODE_READ);
CMP16MtoR(isreg, SuperVUGetVIAddr(_It_, 1));
xCMP(xRegister16(isreg), ptr[(void*)(SuperVUGetVIAddr(_It_, 1))]);
}
}
}
@ -4093,12 +4093,12 @@ void recVUMI_IBGEZ(VURegs* vuu, s32 info)
if (isreg >= 0)
{
TEST16RtoR(isreg, isreg);
xTEST(xRegister16(isreg), xRegister16(isreg));
j8Ptr[ 0 ] = JS8(0);
}
else
{
CMP16ItoM(SuperVUGetVIAddr(_Is_, 1), 0x0);
xCMP(ptr16[(u16*)(SuperVUGetVIAddr(_Is_, 1))], 0x0);
j8Ptr[ 0 ] = JL8(0);
}
@ -4123,12 +4123,12 @@ void recVUMI_IBGTZ(VURegs* vuu, s32 info)
if (isreg >= 0)
{
CMP16ItoR(isreg, 0);
xCMP(xRegister16(isreg), 0);
j8Ptr[ 0 ] = JLE8(0);
}
else
{
CMP16ItoM(SuperVUGetVIAddr(_Is_, 1), 0x0);
xCMP(ptr16[(u16*)(SuperVUGetVIAddr(_Is_, 1))], 0x0);
j8Ptr[ 0 ] = JLE8(0);
}
recVUMI_BranchHandle();
@ -4152,12 +4152,12 @@ void recVUMI_IBLEZ(VURegs* vuu, s32 info)
if (isreg >= 0)
{
CMP16ItoR(isreg, 0);
xCMP(xRegister16(isreg), 0);
j8Ptr[ 0 ] = JG8(0);
}
else
{
CMP16ItoM(SuperVUGetVIAddr(_Is_, 1), 0x0);
xCMP(ptr16[(u16*)(SuperVUGetVIAddr(_Is_, 1))], 0x0);
j8Ptr[ 0 ] = JG8(0);
}
recVUMI_BranchHandle();
@ -4181,12 +4181,12 @@ void recVUMI_IBLTZ(VURegs* vuu, s32 info)
if (isreg >= 0)
{
TEST16RtoR(isreg, isreg);
xTEST(xRegister16(isreg), xRegister16(isreg));
j8Ptr[ 0 ] = JNS8(0);
}
else
{
CMP16ItoM(SuperVUGetVIAddr(_Is_, 1), 0x0);
xCMP(ptr16[(u16*)(SuperVUGetVIAddr(_Is_, 1))], 0x0);
j8Ptr[ 0 ] = JGE8(0);
}
recVUMI_BranchHandle();
@ -4204,7 +4204,7 @@ void recVUMI_B(VURegs* vuu, s32 info)
// supervu will take care of the rest
int bpc = _recbranchAddr(VU->code);
if ((s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 || SUPERVU_CHECKCONDITION)
MOV32ItoM(SuperVUGetVIAddr(REG_TPC, 0), bpc);
xMOV(ptr32[(u32*)(SuperVUGetVIAddr(REG_TPC, 0))], bpc);
// loops to self, so check condition
if (bpc == s_pCurBlock->startpc && (s_vu == 0 || SUPERVU_CHECKCONDITION))
@ -4215,7 +4215,7 @@ void recVUMI_B(VURegs* vuu, s32 info)
if (s_pCurBlock->blocks.size() > 1)
{
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
MOV32ItoR(s_JumpX86, 1);
xMOV(xRegister32(s_JumpX86), 1);
s_pCurBlock->pChildJumps[(s_pCurInst->type & INST_BRANCH_DELAY)?1:0] = (u32*)x86Ptr - 1;
s_UnconditionalDelay = 1;
}
@ -4227,7 +4227,7 @@ void recVUMI_BAL(VURegs* vuu, s32 info)
{
int bpc = _recbranchAddr(VU->code);
if ((s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 || SUPERVU_CHECKCONDITION)
MOV32ItoM(SuperVUGetVIAddr(REG_TPC, 0), bpc);
xMOV(ptr32[(u32*)(SuperVUGetVIAddr(REG_TPC, 0))], bpc);
// loops to self, so check condition
if (bpc == s_pCurBlock->startpc && (s_vu == 0 || SUPERVU_CHECKCONDITION))
@ -4238,13 +4238,13 @@ void recVUMI_BAL(VURegs* vuu, s32 info)
if (_It_)
{
_deleteX86reg(X86TYPE_VI | (s_vu ? X86TYPE_VU1 : 0), _It_, 2);
MOV16ItoM(SuperVUGetVIAddr(_It_, 0), (pc + 8) >> 3);
xMOV(ptr16[(u16*)(SuperVUGetVIAddr(_It_, 0))], (pc + 8) >> 3);
}
if (s_pCurBlock->blocks.size() > 1)
{
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
MOV32ItoR(s_JumpX86, 1);
xMOV(xRegister32(s_JumpX86), 1);
s_pCurBlock->pChildJumps[(s_pCurInst->type & INST_BRANCH_DELAY)?1:0] = (u32*)x86Ptr - 1;
s_UnconditionalDelay = 1;
}
@ -4255,20 +4255,20 @@ void recVUMI_BAL(VURegs* vuu, s32 info)
void recVUMI_JR(VURegs* vuu, s32 info)
{
int isreg = _allocX86reg(-1, X86TYPE_VI | (s_vu ? X86TYPE_VU1 : 0), _Is_, MODE_READ);
LEA32RStoR(EAX, isreg, 3);
xLEA(eax, ptr[xAddressReg(isreg) * (1<<3)]);
//Mask the address to something valid
if (vuu == &VU0)
AND32ItoR(EAX, 0xfff);
xAND(eax, 0xfff);
else
AND32ItoR(EAX, 0x3fff);
xAND(eax, 0x3fff);
if ((s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0) MOV32RtoM(SuperVUGetVIAddr(REG_TPC, 0), EAX);
if ((s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0) xMOV(ptr[(void*)(SuperVUGetVIAddr(REG_TPC, 0))], eax);
if (!(s_pCurBlock->type & BLOCKTYPE_HASEOP))
{
PUSH32I(s_vu);
PUSH32R(EAX);
xPUSH(s_vu);
xPUSH(eax);
}
g_branch |= 0x10; // 0x08 is reserved
}
@ -4278,26 +4278,26 @@ void recVUMI_JALR(VURegs* vuu, s32 info)
_addNeededX86reg(X86TYPE_VI | (s_vu ? X86TYPE_VU1 : 0), _It_);
int isreg = _allocX86reg(-1, X86TYPE_VI | (s_vu ? X86TYPE_VU1 : 0), _Is_, MODE_READ);
LEA32RStoR(EAX, isreg, 3);
xLEA(eax, ptr[xAddressReg(isreg) * (1<<3)]);
//Mask the address to something valid
if (vuu == &VU0)
AND32ItoR(EAX, 0xfff);
xAND(eax, 0xfff);
else
AND32ItoR(EAX, 0x3fff);
xAND(eax, 0x3fff);
if (_It_)
{
_deleteX86reg(X86TYPE_VI | (s_vu ? X86TYPE_VU1 : 0), _It_, 2);
MOV16ItoM(SuperVUGetVIAddr(_It_, 0), (pc + 8) >> 3);
xMOV(ptr16[(u16*)(SuperVUGetVIAddr(_It_, 0))], (pc + 8) >> 3);
}
if ((s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0) MOV32RtoM(SuperVUGetVIAddr(REG_TPC, 0), EAX);
if ((s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0) xMOV(ptr[(void*)(SuperVUGetVIAddr(REG_TPC, 0))], eax);
if (!(s_pCurBlock->type & BLOCKTYPE_HASEOP))
{
PUSH32I(s_vu);
PUSH32R(EAX);
xPUSH(s_vu);
xPUSH(eax);
}
g_branch |= 4;
@ -4330,8 +4330,8 @@ void recVUMI_XGKICK(VURegs *VU, int info)
x86regs[isreg].type = X86TYPE_VITEMP;
x86regs[isreg].needed = 1;
x86regs[isreg].mode = MODE_WRITE | MODE_READ;
SHL32ItoR(isreg, 4);
AND32ItoR(isreg, 0x3fff);
xSHL(xRegister32(isreg), 4);
xAND(xRegister32(isreg), 0x3fff);
s_XGKICKReg = isreg;
if (!SUPERVU_XGKICKDELAY || pc == s_pCurBlock->endpc) {