mirror of https://github.com/PCSX2/pcsx2.git
Changed some code around in microVU that was causing 10+ minute link times in Release builds (LTCG mode), also added some new x86Emitter cleanups along the way. :)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1374 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
d1c7d2f1a6
commit
fb4fcc7d29
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@ -231,4 +231,15 @@ namespace x86Emitter
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}
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}
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// ------------------------------------------------------------------------
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// returns the inverted conditional type for this Jcc condition. Ie, JNS will become JS.
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//
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static __forceinline JccComparisonType xInvertCond( JccComparisonType src )
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{
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jASSUME( src != Jcc_Unknown );
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if( Jcc_Unconditional == src ) return Jcc_Unconditional;
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// x86 conditionals are clever! To invert conditional types, just invert the lower bit:
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return (JccComparisonType)((int)src ^ 1);
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}
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}
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@ -252,6 +252,202 @@ microVUf(int) mVUsearchProg() {
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return 1; // If !cleared, then we're still on the same program as last-time ;)
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}
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//------------------------------------------------------------------
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// JIT recompiler -- called from recompiled code when register jumps are made.
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//------------------------------------------------------------------
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microVUf(void*) __fastcall mVUcompileJIT(u32 startPC, uptr pState) {
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return mVUblockFetch( mVUx, startPC, pState );
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}
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//------------------------------------------------------------------
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// Recompiler
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//------------------------------------------------------------------
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static void* __fastcall mVUcompile( microVU* mVU, u32 startPC, uptr pState )
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{
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using namespace x86Emitter;
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// Setup Program Bounds/Range
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mVUsetupRange(mVU, startPC);
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microBlock* pBlock = NULL;
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u8* thisPtr = x86Ptr;
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const u32 microSizeDiv8 = (mVU->microSize-1) / 8;
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// First Pass
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iPC = startPC / 4;
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setCode();
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mVUbranch = 0;
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mVUstartPC = iPC;
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mVUcount = 0;
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mVUcycles = 0; // Skips "M" phase, and starts counting cycles at "T" stage
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mVU->p = 0; // All blocks start at p index #0
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mVU->q = 0; // All blocks start at q index #0
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memcpy_fast(&mVUregs, (microRegInfo*)pState, sizeof(microRegInfo)); // Loads up Pipeline State Info
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mVUblock.x86ptrStart = thisPtr;
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pBlock = mVUblocks[startPC/8]->add(&mVUblock); // Add this block to block manager
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mVUpBlock = pBlock;
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mVUregs.flags = 0;
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mVUflagInfo = 0;
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mVUsFlagHack = CHECK_VU_FLAGHACK;
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for (int branch = 0; mVUcount < microSizeDiv8; ) {
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incPC(1);
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startLoop();
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mVUincCycles(mVU, 1);
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mVUopU(mVU, 0);
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if (curI & _Ebit_) { branch = 1; mVUup.eBit = 1; }
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if (curI & _DTbit_) { branch = 4; }
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if (curI & _Mbit_) { mVUup.mBit = 1; }
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if (curI & _Ibit_) { mVUlow.isNOP = 1; mVUup.iBit = 1; }
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else { incPC(-1); mVUopL(mVU, 0); incPC(1); }
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mVUsetCycles(mVU);
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mVUinfo.readQ = mVU->q;
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mVUinfo.writeQ = !mVU->q;
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mVUinfo.readP = mVU->p;
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mVUinfo.writeP = !mVU->p;
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if (branch >= 2) { mVUinfo.isEOB = 1; if (branch == 3) { mVUinfo.isBdelay = 1; } mVUcount++; branchWarning(); break; }
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else if (branch == 1) { branch = 2; }
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if (mVUbranch) { mVUsetFlagInfo(mVU); branch = 3; mVUbranch = 0; }
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incPC(1);
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mVUcount++;
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}
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// Sets Up Flag instances
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int xStatus[4], xMac[4], xClip[4];
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int xCycles = mVUsetFlags(mVU, xStatus, xMac, xClip);
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mVUtestCycles(mVU);
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// Second Pass
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iPC = mVUstartPC;
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setCode();
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mVUbranch = 0;
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uint x;
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for (x = 0; x < microSizeDiv8; x++) {
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if (mVUinfo.isEOB) { x = 0xffff; }
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if (mVUup.mBit) { OR32ItoM((uptr)&mVU->regs->flags, VUFLAG_MFLAGSET); }
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if (mVUlow.isNOP) { incPC(1); doUpperOp(); doIbit(); }
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else if (!mVUinfo.swapOps) { incPC(1); doUpperOp(); doLowerOp(); }
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else { doSwapOp(); }
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if (mVUinfo.doXGKICK) { mVU_XGKICK_DELAY(mVU, 1); }
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if (!mVUinfo.isBdelay) { incPC(1); }
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else {
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microBlock* bBlock = NULL;
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s32* ajmp = 0;
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mVUsetupRange(mVU, xPC);
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mVUdebugNOW(1);
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switch (mVUbranch) {
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case 3: branchCase(Jcc_Equal); // IBEQ
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case 4: branchCase(Jcc_GreaterOrEqual); // IBGEZ
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case 5: branchCase(Jcc_Greater); // IBGTZ
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case 6: branchCase(Jcc_LessOrEqual); // IBLEQ
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case 7: branchCase(Jcc_Less); // IBLTZ
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case 8: branchCase(Jcc_NotEqual); // IBNEQ
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case 1: case 2: // B/BAL
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mVUprint("mVUcompile B/BAL");
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incPC(-3); // Go back to branch opcode (to get branch imm addr)
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if (mVUup.eBit) { iPC = branchAddr/4; mVUendProgram(mVU, 1, xStatus, xMac, xClip); } // E-bit Branch
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mVUsetupBranch(mVU, xStatus, xMac, xClip, xCycles);
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if (mVUblocks[branchAddr/8] == NULL)
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mVUblocks[branchAddr/8] = microBlockManager::AlignedNew();
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// Check if branch-block has already been compiled
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pBlock = mVUblocks[branchAddr/8]->search((microRegInfo*)&mVUregs);
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if (pBlock) { xJMP(pBlock->x86ptrStart); }
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else { mVUcompile(mVU, branchAddr, (uptr)&mVUregs); }
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return thisPtr;
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case 9: case 10: // JR/JALR
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mVUprint("mVUcompile JR/JALR");
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incPC(-3); // Go back to jump opcode
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if (mVUup.eBit) { // E-bit Jump
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mVUendProgram(mVU, 2, xStatus, xMac, xClip);
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MOV32MtoR(gprT1, (uptr)&mVU->branch);
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MOV32RtoM((uptr)&mVU->regs->VI[REG_TPC].UL, gprT1);
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xJMP(mVU->exitFunct);
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return thisPtr;
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}
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memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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mVUsetupBranch(mVU, xStatus, xMac, xClip, xCycles);
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mVUbackupRegs(mVU);
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MOV32MtoR(gprT2, (uptr)&mVU->branch); // Get startPC (ECX first argument for __fastcall)
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MOV32ItoR(gprR, (u32)&pBlock->pStateEnd); // Get pState (EDX second argument for __fastcall)
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if (!mVU->index) xCALL( mVUcompileJIT<0> ); //(u32 startPC, uptr pState)
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else xCALL( mVUcompileJIT<1> );
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mVUrestoreRegs(mVU);
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JMPR(gprT1); // Jump to rec-code address
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return thisPtr;
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}
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// Conditional Branches
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mVUprint("mVUcompile conditional branch");
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if (bBlock) { // Branch non-taken has already been compiled
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incPC(-3); // Go back to branch opcode (to get branch imm addr)
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if (mVUblocks[branchAddr/8] == NULL)
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mVUblocks[branchAddr/8] = microBlockManager::AlignedNew();
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// Check if branch-block has already been compiled
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pBlock = mVUblocks[branchAddr/8]->search((microRegInfo*)&mVUregs);
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if (pBlock) { xJMP( pBlock->x86ptrStart ); }
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else if (!mVU->index) { mVUblockFetch(mVU, branchAddr, (uptr)&mVUregs); }
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else { mVUblockFetch(mVU, branchAddr, (uptr)&mVUregs); }
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}
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else {
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uptr jumpAddr;
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u32 bPC = iPC; // mVUcompile can modify iPC and mVUregs so back them up
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memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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incPC2(1); // Get PC for branch not-taken
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mVUcompile(mVU, xPC, (uptr)&mVUregs);
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iPC = bPC;
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incPC(-3); // Go back to branch opcode (to get branch imm addr)
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if (!mVU->index) jumpAddr = (uptr)mVUblockFetch(mVU, branchAddr, (uptr)&pBlock->pStateEnd);
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else jumpAddr = (uptr)mVUblockFetch(mVU, branchAddr, (uptr)&pBlock->pStateEnd);
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*ajmp = (jumpAddr - ((uptr)ajmp + 4));
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}
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return thisPtr;
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}
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}
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if (x == microSizeDiv8) { Console::Error("microVU%d: Possible infinite compiling loop!", params mVU->index); }
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// E-bit End
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mVUendProgram(mVU, 1, xStatus, xMac, xClip);
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return thisPtr;
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}
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microVUt(void*) mVUblockFetch( microVU* mVU, u32 startPC, uptr pState )
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{
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using namespace x86Emitter;
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if (startPC > mVU->microSize-1) { Console::Error("microVU%d: invalid startPC", params mVU->index); }
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startPC &= ~7;
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if (mVUblocks[startPC/8] == NULL) {
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mVUblocks[startPC/8] = microBlockManager::AlignedNew();
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}
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// Searches for Existing Compiled Block (if found, then returns; else, compile)
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microBlock* pBlock = mVUblocks[startPC/8]->search((microRegInfo*)pState);
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if (pBlock) { return pBlock->x86ptrStart; }
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return mVUcompile( mVU, startPC, pState );
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}
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//------------------------------------------------------------------
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// Wrapper Functions - Called by other parts of the Emu
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//------------------------------------------------------------------
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@ -155,17 +155,15 @@ microVUf(void) mVUinit(VURegs*);
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microVUx(void) mVUreset();
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microVUf(void) mVUclose();
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microVUf(void) mVUclear(u32, u32);
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microVUt(void*) mVUblockFetch( microVU* mVU, u32 startPC, uptr pState );
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// Prototypes for Linux
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void __fastcall mVUcleanUpVU0();
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void __fastcall mVUcleanUpVU1();
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void* __fastcall mVUcompileVU0(u32 startPC, uptr pState);
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void* __fastcall mVUcompileVU1(u32 startPC, uptr pState);
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mVUop(mVUopU);
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mVUop(mVUopL);
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// Private Functions
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microVUf(void) mVUclearProg(microVU* mVU, int progIndex);
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microVUf(int) mVUfindLeastUsedProg(microVU* mVU);
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microVUf(int) mVUsearchProg();
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microVUf(void) mVUcacheProg(int progIndex);
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@ -22,20 +22,20 @@
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// Helper Macros
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//------------------------------------------------------------------
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#define branchCase(JMPcc, nJMPcc, ebitJMP) \
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#define branchCase(JMPcc) \
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mVUsetupBranch(mVU, xStatus, xMac, xClip, xCycles); \
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CMP16ItoM((uptr)&mVU->branch, 0); \
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xCMP( ptr16[&mVU->branch], 0); \
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if (mVUup.eBit) { /* Conditional Branch With E-Bit Set */ \
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mVUendProgram(mVU, 2, xStatus, xMac, xClip); \
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u8* eJMP = ebitJMP(0); \
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xForwardJump8 eJMP( JMPcc ); \
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incPC(1); /* Set PC to First instruction of Non-Taken Side */ \
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MOV32ItoM((uptr)&mVU->regs->VI[REG_TPC].UL, xPC); \
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JMP32((uptr)mVU->exitFunct - ((uptr)x86Ptr + 5)); \
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x86SetJ8(eJMP); \
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xMOV( ptr32[&mVU->regs->VI[REG_TPC].UL], xPC); \
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xJMP( mVU->exitFunct ); \
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eJMP.SetTarget(); \
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incPC(-4); /* Go Back to Branch Opcode to get branchAddr */ \
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iPC = branchAddr/4; \
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MOV32ItoM((uptr)&mVU->regs->VI[REG_TPC].UL, xPC); \
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JMP32((uptr)mVU->exitFunct - ((uptr)x86Ptr + 5)); \
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xMOV( ptr32[&mVU->regs->VI[REG_TPC].UL], xPC); \
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xJMP( mVU->exitFunct ); \
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return thisPtr; \
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} \
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else { /* Normal Conditional Branch */ \
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@ -43,14 +43,14 @@
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if (!mVUblocks[iPC/2]) { mVUblocks[iPC/2] = microBlockManager::AlignedNew(); } \
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bBlock = mVUblocks[iPC/2]->search((microRegInfo*)&mVUregs); \
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incPC2(-1); \
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if (bBlock) { nJMPcc((uptr)bBlock->x86ptrStart - ((uptr)x86Ptr + 6)); } \
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else { ajmp = JMPcc((uptr)0); } \
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if (bBlock) { xJcc( xInvertCond( JMPcc ), bBlock->x86ptrStart ); } \
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else { ajmp = xJcc32( JMPcc ); } \
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} \
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break
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#define branchWarning() { \
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if (mVUbranch) { \
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Console::Error("microVU%d Warning: Branch in E-bit/Branch delay slot! [%04x]", params vuIndex, xPC); \
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Console::Error("microVU%d Warning: Branch in E-bit/Branch delay slot! [%04x]", params mVU->index, xPC); \
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mVUlow.isNOP = 1; \
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} \
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}
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@ -282,182 +282,3 @@ microVUt(void) mVUtestCycles(mV) {
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mVUendProgram(mVU, 0, NULL, NULL, NULL);
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x86SetJ32(jmp32);
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}
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//------------------------------------------------------------------
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// Recompiler
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//------------------------------------------------------------------
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microVUf(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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microVU* mVU = mVUx;
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u8* thisPtr = x86Ptr;
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if (startPC > ((vuIndex) ? 0x3fff : 0xfff)) { Console::Error("microVU%d: invalid startPC", params vuIndex); }
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startPC &= (vuIndex ? 0x3ff8 : 0xff8);
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if (mVUblocks[startPC/8] == NULL) {
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mVUblocks[startPC/8] = microBlockManager::AlignedNew();
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}
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// Searches for Existing Compiled Block (if found, then returns; else, compile)
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microBlock* pBlock = mVUblocks[startPC/8]->search((microRegInfo*)pState);
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if (pBlock) { return pBlock->x86ptrStart; }
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// Setup Program Bounds/Range
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mVUsetupRange(mVU, startPC);
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// First Pass
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iPC = startPC / 4;
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setCode();
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mVUbranch = 0;
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mVUstartPC = iPC;
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mVUcount = 0;
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mVUcycles = 0; // Skips "M" phase, and starts counting cycles at "T" stage
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mVU->p = 0; // All blocks start at p index #0
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mVU->q = 0; // All blocks start at q index #0
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memcpy_fast(&mVUregs, (microRegInfo*)pState, sizeof(microRegInfo)); // Loads up Pipeline State Info
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mVUblock.x86ptrStart = thisPtr;
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pBlock = mVUblocks[startPC/8]->add(&mVUblock); // Add this block to block manager
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mVUpBlock = pBlock;
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mVUregs.flags = 0;
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mVUflagInfo = 0;
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mVUsFlagHack = CHECK_VU_FLAGHACK;
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for (int branch = 0; mVUcount < (vuIndex ? (0x3fff/8) : (0xfff/8)); ) {
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incPC(1);
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startLoop();
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mVUincCycles(mVU, 1);
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mVUopU(mVU, 0);
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if (curI & _Ebit_) { branch = 1; mVUup.eBit = 1; }
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if (curI & _DTbit_) { branch = 4; }
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if (curI & _Mbit_) { mVUup.mBit = 1; }
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if (curI & _Ibit_) { mVUlow.isNOP = 1; mVUup.iBit = 1; }
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else { incPC(-1); mVUopL(mVU, 0); incPC(1); }
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mVUsetCycles(mVU);
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mVUinfo.readQ = mVU->q;
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mVUinfo.writeQ = !mVU->q;
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mVUinfo.readP = mVU->p;
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mVUinfo.writeP = !mVU->p;
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if (branch >= 2) { mVUinfo.isEOB = 1; if (branch == 3) { mVUinfo.isBdelay = 1; } mVUcount++; branchWarning(); break; }
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else if (branch == 1) { branch = 2; }
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if (mVUbranch) { mVUsetFlagInfo(mVU); branch = 3; mVUbranch = 0; }
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incPC(1);
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mVUcount++;
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}
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// Sets Up Flag instances
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int xStatus[4], xMac[4], xClip[4];
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int xCycles = mVUsetFlags(mVU, xStatus, xMac, xClip);
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mVUtestCycles(mVU);
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// Second Pass
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iPC = mVUstartPC;
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setCode();
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mVUbranch = 0;
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int x;
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for (x = 0; x < (vuIndex ? (0x3fff/8) : (0xfff/8)); x++) {
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if (mVUinfo.isEOB) { x = 0xffff; }
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if (mVUup.mBit) { OR32ItoM((uptr)&mVU->regs->flags, VUFLAG_MFLAGSET); }
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if (mVUlow.isNOP) { incPC(1); doUpperOp(); doIbit(); }
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else if (!mVUinfo.swapOps) { incPC(1); doUpperOp(); doLowerOp(); }
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else { doSwapOp(); }
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if (mVUinfo.doXGKICK) { mVU_XGKICK_DELAY(mVU, 1); }
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if (!mVUinfo.isBdelay) { incPC(1); }
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else {
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microBlock* bBlock = NULL;
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u32* ajmp = 0;
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mVUsetupRange(mVU, xPC);
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mVUdebugNOW(1);
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switch (mVUbranch) {
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case 3: branchCase(JE32, JNE32, JE8); // IBEQ
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case 4: branchCase(JGE32, JNGE32, JGE8); // IBGEZ
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case 5: branchCase(JG32, JNG32, JG8); // IBGTZ
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case 6: branchCase(JLE32, JNLE32, JLE8); // IBLEQ
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case 7: branchCase(JL32, JNL32, JL8); // IBLTZ
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case 8: branchCase(JNE32, JE32, JNE8); // IBNEQ
|
||||
case 1: case 2: // B/BAL
|
||||
|
||||
mVUprint("mVUcompile B/BAL");
|
||||
incPC(-3); // Go back to branch opcode (to get branch imm addr)
|
||||
|
||||
if (mVUup.eBit) { iPC = branchAddr/4; mVUendProgram(mVU, 1, xStatus, xMac, xClip); } // E-bit Branch
|
||||
mVUsetupBranch(mVU, xStatus, xMac, xClip, xCycles);
|
||||
|
||||
if (mVUblocks[branchAddr/8] == NULL)
|
||||
mVUblocks[branchAddr/8] = microBlockManager::AlignedNew();
|
||||
|
||||
// Check if branch-block has already been compiled
|
||||
pBlock = mVUblocks[branchAddr/8]->search((microRegInfo*)&mVUregs);
|
||||
if (pBlock) { JMP32((uptr)pBlock->x86ptrStart - ((uptr)x86Ptr + 5)); }
|
||||
else if (!vuIndex) { mVUcompileVU0(branchAddr, (uptr)&mVUregs); }
|
||||
else { mVUcompileVU1(branchAddr, (uptr)&mVUregs); }
|
||||
return thisPtr;
|
||||
case 9: case 10: // JR/JALR
|
||||
|
||||
mVUprint("mVUcompile JR/JALR");
|
||||
incPC(-3); // Go back to jump opcode
|
||||
|
||||
if (mVUup.eBit) { // E-bit Jump
|
||||
mVUendProgram(mVU, 2, xStatus, xMac, xClip);
|
||||
MOV32MtoR(gprT1, (uptr)&mVU->branch);
|
||||
MOV32RtoM((uptr)&mVU->regs->VI[REG_TPC].UL, gprT1);
|
||||
JMP32((uptr)mVU->exitFunct - ((uptr)x86Ptr + 5));
|
||||
return thisPtr;
|
||||
}
|
||||
|
||||
memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
|
||||
mVUsetupBranch(mVU, xStatus, xMac, xClip, xCycles);
|
||||
|
||||
mVUbackupRegs(mVU);
|
||||
MOV32MtoR(gprT2, (uptr)&mVU->branch); // Get startPC (ECX first argument for __fastcall)
|
||||
MOV32ItoR(gprR, (u32)&pBlock->pStateEnd); // Get pState (EDX second argument for __fastcall)
|
||||
|
||||
if (!vuIndex) CALLFunc((uptr)mVUcompileVU0); //(u32 startPC, uptr pState)
|
||||
else CALLFunc((uptr)mVUcompileVU1);
|
||||
mVUrestoreRegs(mVU);
|
||||
JMPR(gprT1); // Jump to rec-code address
|
||||
return thisPtr;
|
||||
}
|
||||
// Conditional Branches
|
||||
mVUprint("mVUcompile conditional branch");
|
||||
if (bBlock) { // Branch non-taken has already been compiled
|
||||
incPC(-3); // Go back to branch opcode (to get branch imm addr)
|
||||
|
||||
if (mVUblocks[branchAddr/8] == NULL)
|
||||
mVUblocks[branchAddr/8] = microBlockManager::AlignedNew();
|
||||
|
||||
// Check if branch-block has already been compiled
|
||||
pBlock = mVUblocks[branchAddr/8]->search((microRegInfo*)&mVUregs);
|
||||
if (pBlock) { JMP32((uptr)pBlock->x86ptrStart - ((uptr)x86Ptr + 5)); }
|
||||
else if (!vuIndex) { mVUcompileVU0(branchAddr, (uptr)&mVUregs); }
|
||||
else { mVUcompileVU1(branchAddr, (uptr)&mVUregs); }
|
||||
}
|
||||
else {
|
||||
uptr jumpAddr;
|
||||
u32 bPC = iPC; // mVUcompile can modify iPC and mVUregs so back them up
|
||||
memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
|
||||
|
||||
incPC2(1); // Get PC for branch not-taken
|
||||
if (!vuIndex) mVUcompileVU0(xPC, (uptr)&mVUregs);
|
||||
else mVUcompileVU1(xPC, (uptr)&mVUregs);
|
||||
|
||||
iPC = bPC;
|
||||
incPC(-3); // Go back to branch opcode (to get branch imm addr)
|
||||
if (!vuIndex) jumpAddr = (uptr)mVUcompileVU0(branchAddr, (uptr)&pBlock->pStateEnd);
|
||||
else jumpAddr = (uptr)mVUcompileVU1(branchAddr, (uptr)&pBlock->pStateEnd);
|
||||
*ajmp = (jumpAddr - ((uptr)ajmp + 4));
|
||||
}
|
||||
return thisPtr;
|
||||
}
|
||||
}
|
||||
if (x == (vuIndex?(0x3fff/8):(0xfff/8))) { Console::Error("microVU%d: Possible infinite compiling loop!", params vuIndex); }
|
||||
|
||||
// E-bit End
|
||||
mVUendProgram(mVU, 1, xStatus, xMac, xClip);
|
||||
return thisPtr;
|
||||
}
|
||||
|
||||
void* __fastcall mVUcompileVU0(u32 startPC, uptr pState) { return mVUcompile<0>(startPC, pState); }
|
||||
void* __fastcall mVUcompileVU1(u32 startPC, uptr pState) { return mVUcompile<1>(startPC, pState); }
|
||||
|
||||
|
|
|
|||
|
|
@ -128,8 +128,7 @@ microVUx(void*) __fastcall mVUexecute(u32 startPC, u32 cycles) {
|
|||
mVU->totalCycles = cycles;
|
||||
|
||||
x86SetPtr(mVUcurProg.x86ptr); // Set x86ptr to where program left off
|
||||
if (!vuIndex) return mVUcompileVU0(startPC, (uptr)&mVU->prog.lpState);
|
||||
else return mVUcompileVU1(startPC, (uptr)&mVU->prog.lpState);
|
||||
return mVUblockFetch(mVU, startPC, (uptr)&mVU->prog.lpState);
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -94,7 +94,7 @@ declareAllVariables
|
|||
#define _Ftf_ ((mVU->code >> 23) & 0x03)
|
||||
|
||||
#define _Imm5_ (s16)(((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf))
|
||||
#define _Imm11_ (s32)((mVU->code & 0x400) ? (0xfffffc00 | (mVU->code & 0x3ff)) : mVU->code & 0x3ff)
|
||||
#define _Imm11_ (s32)((mVU->code & 0x400) ? (0xfffffc00 | (mVU->code & 0x3ff)) : (mVU->code & 0x3ff))
|
||||
#define _Imm12_ (((mVU->code >> 21) & 0x1) << 11) | (mVU->code & 0x7ff)
|
||||
#define _Imm15_ (((mVU->code >> 10) & 0x7800) | (mVU->code & 0x7ff))
|
||||
#define _Imm24_ (u32)(mVU->code & 0xffffff)
|
||||
|
|
@ -204,7 +204,7 @@ typedef u32 (__fastcall *mVUCall)(void*, void*);
|
|||
#define incPC(x) { iPC = ((iPC + x) & (mVU->progSize-1)); setCode(); }
|
||||
#define incPC2(x) { iPC = ((iPC + x) & (mVU->progSize-1)); }
|
||||
#define bSaveAddr (((xPC + (2 * 8)) & ((isVU1) ? 0x3ff8:0xff8)) / 8)
|
||||
#define branchAddr ((xPC + 8 + (_Imm11_ * 8)) & ((isVU1) ? 0x3ff8 : 0xff8))
|
||||
#define branchAddr ((xPC + 8 + (_Imm11_ * 8)) & (mVU->microSize-8))
|
||||
#define shufflePQ (((mVU->p) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04))
|
||||
#define Rmem (uptr)&mVU->regs->VI[REG_R].UL
|
||||
#define Roffset (uptr)&mVU->regs->VI[9].UL
|
||||
|
|
|
|||
Loading…
Reference in New Issue