mirror of https://github.com/PCSX2/pcsx2.git
Hack for Midway (Thanks guys!) games, as to show their muppetry in coding, i have left big dev warnings everytime it hits their cockup. On a more serious note, Solves the issue of a failing COP Condition they are trying to achieve.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4077 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
refraction
parent
5c54b8279e
commit
fa76cfdeca
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@ -308,6 +308,7 @@ enum EERegisterAddresses
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DMAC_RBSR = 0x1000E040,
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DMAC_RBOR = 0x1000E050,
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DMAC_STADR = 0x1000E060,
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DMAC_FAKESTAT = 0x1000E100, //Midway, you're idiots (checked this in the MK Deception ELF!) (Refraction)
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INTC_STAT = 0x1000F000,
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INTC_MASK = 0x1000F010,
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@ -292,125 +292,141 @@ template< uint page >
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__fi bool dmacWrite32( u32 mem, mem32_t& value )
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{
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iswitch(mem) {
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icase(D0_CHCR) // dma0 - vif0
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{
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DMA_LOG("VIF0dma EXECUTE, value=0x%x", value);
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DmaExec(dmaVIF0, mem, value);
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return false;
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}
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icase(D1_CHCR) // dma1 - vif1 - chcr
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{
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DMA_LOG("VIF1dma EXECUTE, value=0x%x", value);
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DmaExec(dmaVIF1, mem, value);
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return false;
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}
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icase(D2_CHCR) // dma2 - gif
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{
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DMA_LOG("GIFdma EXECUTE, value=0x%x", value);
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DmaExec(dmaGIF, mem, value);
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return false;
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}
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icase(D3_CHCR) // dma3 - fromIPU
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{
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DMA_LOG("IPU0dma EXECUTE, value=0x%x\n", value);
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DmaExec(dmaIPU0, mem, value);
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return false;
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}
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icase(D4_CHCR) // dma4 - toIPU
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{
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DMA_LOG("IPU1dma EXECUTE, value=0x%x\n", value);
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DmaExec(dmaIPU1, mem, value);
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return false;
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}
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icase(D5_CHCR) // dma5 - sif0
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{
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DMA_LOG("SIF0dma EXECUTE, value=0x%x", value);
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DmaExec(dmaSIF0, mem, value);
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return false;
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}
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icase(D6_CHCR) // dma6 - sif1
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{
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DMA_LOG("SIF1dma EXECUTE, value=0x%x", value);
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DmaExec(dmaSIF1, mem, value);
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return false;
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}
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icase(D7_CHCR) // dma7 - sif2
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{
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DMA_LOG("SIF2dma EXECUTE, value=0x%x", value);
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DmaExec(dmaSIF2, mem, value);
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return false;
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}
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icase(D8_CHCR) // dma8 - fromSPR
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{
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DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x", value);
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DmaExec(dmaSPR0, mem, value);
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return false;
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}
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icase(D9_CHCR) // dma9 - toSPR
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{
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DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x", value);
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DmaExec(dmaSPR1, mem, value);
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return false;
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}
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icase(DMAC_CTRL)
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{
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u32 oldvalue = psHu32(mem);
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HW_LOG("DMAC_CTRL Write 32bit %x", value);
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psHu32(mem) = value;
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//Check for DMAS that were started while the DMAC was disabled
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if (((oldvalue & 0x1) == 0) && ((value & 0x1) == 1))
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icase(D0_CHCR) // dma0 - vif0
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{
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if (!QueuedDMA.empty()) StartQueuedDMA();
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DMA_LOG("VIF0dma EXECUTE, value=0x%x", value);
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DmaExec(dmaVIF0, mem, value);
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return false;
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}
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if ((oldvalue & 0x30) != (value & 0x30))
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icase(D1_CHCR) // dma1 - vif1 - chcr
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{
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DevCon.Warning("32bit Stall Source Changed to %x", (value & 0x30) >> 4);
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DMA_LOG("VIF1dma EXECUTE, value=0x%x", value);
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DmaExec(dmaVIF1, mem, value);
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return false;
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}
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if ((oldvalue & 0xC0) != (value & 0xC0))
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icase(D2_CHCR) // dma2 - gif
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{
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DevCon.Warning("32bit Stall Destination Changed to %x", (value & 0xC0) >> 4);
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DMA_LOG("GIFdma EXECUTE, value=0x%x", value);
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DmaExec(dmaGIF, mem, value);
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return false;
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}
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return false;
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}
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icase(DMAC_STAT)
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{
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HW_LOG("DMAC_STAT Write 32bit %x", value);
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// lower 16 bits: clear on 1
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// upper 16 bits: reverse on 1
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psHu16(0xe010) &= ~(value & 0xffff);
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psHu16(0xe012) ^= (u16)(value >> 16);
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cpuTestDMACInts();
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return false;
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}
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icase(DMAC_ENABLEW)
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{
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HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
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oldvalue = psHu8(DMAC_ENABLEW + 2);
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psHu32(DMAC_ENABLEW) = value;
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psHu32(DMAC_ENABLER) = value;
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if (((oldvalue & 0x1) == 1) && (((value >> 16) & 0x1) == 0))
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icase(D3_CHCR) // dma3 - fromIPU
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{
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if (!QueuedDMA.empty()) StartQueuedDMA();
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DMA_LOG("IPU0dma EXECUTE, value=0x%x\n", value);
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DmaExec(dmaIPU0, mem, value);
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return false;
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}
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icase(D4_CHCR) // dma4 - toIPU
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{
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DMA_LOG("IPU1dma EXECUTE, value=0x%x\n", value);
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DmaExec(dmaIPU1, mem, value);
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return false;
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}
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icase(D5_CHCR) // dma5 - sif0
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{
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DMA_LOG("SIF0dma EXECUTE, value=0x%x", value);
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DmaExec(dmaSIF0, mem, value);
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return false;
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}
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icase(D6_CHCR) // dma6 - sif1
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{
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DMA_LOG("SIF1dma EXECUTE, value=0x%x", value);
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DmaExec(dmaSIF1, mem, value);
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return false;
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}
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icase(D7_CHCR) // dma7 - sif2
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{
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DMA_LOG("SIF2dma EXECUTE, value=0x%x", value);
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DmaExec(dmaSIF2, mem, value);
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return false;
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}
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icase(D8_CHCR) // dma8 - fromSPR
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{
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DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x", value);
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DmaExec(dmaSPR0, mem, value);
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return false;
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}
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icase(D9_CHCR) // dma9 - toSPR
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{
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DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x", value);
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DmaExec(dmaSPR1, mem, value);
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return false;
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}
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icase(DMAC_CTRL)
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{
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u32 oldvalue = psHu32(mem);
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HW_LOG("DMAC_CTRL Write 32bit %x", value);
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psHu32(mem) = value;
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//Check for DMAS that were started while the DMAC was disabled
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if (((oldvalue & 0x1) == 0) && ((value & 0x1) == 1))
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{
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if (!QueuedDMA.empty()) StartQueuedDMA();
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}
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if ((oldvalue & 0x30) != (value & 0x30))
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{
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DevCon.Warning("32bit Stall Source Changed to %x", (value & 0x30) >> 4);
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}
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if ((oldvalue & 0xC0) != (value & 0xC0))
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{
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DevCon.Warning("32bit Stall Destination Changed to %x", (value & 0xC0) >> 4);
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}
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return false;
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}
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//Midway are a bunch of idiots, writing to E100 (reserved) instead of E010
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//Which causes a CPCOND0 to fail.
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icase(DMAC_FAKESTAT)
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{
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DevCon.Warning("Midway fixup addr=%x writing %x for DMA_STAT", mem, value);
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HW_LOG("Midways own DMAC_STAT Write 32bit %x", value);
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// lower 16 bits: clear on 1
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// upper 16 bits: reverse on 1
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psHu16(0xe010) &= ~(value & 0xffff);
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psHu16(0xe012) ^= (u16)(value >> 16);
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cpuTestDMACInts();
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return false;
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}
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icase(DMAC_STAT)
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{
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HW_LOG("DMAC_STAT Write 32bit %x", value);
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// lower 16 bits: clear on 1
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// upper 16 bits: reverse on 1
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psHu16(0xe010) &= ~(value & 0xffff);
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psHu16(0xe012) ^= (u16)(value >> 16);
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cpuTestDMACInts();
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return false;
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}
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icase(DMAC_ENABLEW)
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{
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HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
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oldvalue = psHu8(DMAC_ENABLEW + 2);
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psHu32(DMAC_ENABLEW) = value;
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psHu32(DMAC_ENABLER) = value;
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if (((oldvalue & 0x1) == 1) && (((value >> 16) & 0x1) == 0))
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{
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if (!QueuedDMA.empty()) StartQueuedDMA();
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}
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return false;
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}
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return false;
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}
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}
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//DMA Writes are invalid to everything except the STR on CHCR when it is busy
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