From fa76cfdeca75089c7c0016e61b97a3f9cc48a22b Mon Sep 17 00:00:00 2001 From: refraction Date: Mon, 6 Dec 2010 21:40:36 +0000 Subject: [PATCH] Hack for Midway (Thanks guys!) games, as to show their muppetry in coding, i have left big dev warnings everytime it hits their cockup. On a more serious note, Solves the issue of a failing COP Condition they are trying to achieve. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4077 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/Hw.h | 1 + pcsx2/ps2/LegacyDmac.cpp | 236 +++++++++++++++++++++------------------ 2 files changed, 127 insertions(+), 110 deletions(-) diff --git a/pcsx2/Hw.h b/pcsx2/Hw.h index ef1bb0b658..02b92d64b1 100644 --- a/pcsx2/Hw.h +++ b/pcsx2/Hw.h @@ -308,6 +308,7 @@ enum EERegisterAddresses DMAC_RBSR = 0x1000E040, DMAC_RBOR = 0x1000E050, DMAC_STADR = 0x1000E060, + DMAC_FAKESTAT = 0x1000E100, //Midway, you're idiots (checked this in the MK Deception ELF!) (Refraction) INTC_STAT = 0x1000F000, INTC_MASK = 0x1000F010, diff --git a/pcsx2/ps2/LegacyDmac.cpp b/pcsx2/ps2/LegacyDmac.cpp index d40f588aa6..1b22b79f3a 100644 --- a/pcsx2/ps2/LegacyDmac.cpp +++ b/pcsx2/ps2/LegacyDmac.cpp @@ -292,125 +292,141 @@ template< uint page > __fi bool dmacWrite32( u32 mem, mem32_t& value ) { iswitch(mem) { - icase(D0_CHCR) // dma0 - vif0 - { - DMA_LOG("VIF0dma EXECUTE, value=0x%x", value); - DmaExec(dmaVIF0, mem, value); - return false; - } - - icase(D1_CHCR) // dma1 - vif1 - chcr - { - DMA_LOG("VIF1dma EXECUTE, value=0x%x", value); - DmaExec(dmaVIF1, mem, value); - return false; - } - - icase(D2_CHCR) // dma2 - gif - { - DMA_LOG("GIFdma EXECUTE, value=0x%x", value); - DmaExec(dmaGIF, mem, value); - return false; - } - - icase(D3_CHCR) // dma3 - fromIPU - { - DMA_LOG("IPU0dma EXECUTE, value=0x%x\n", value); - DmaExec(dmaIPU0, mem, value); - return false; - } - - icase(D4_CHCR) // dma4 - toIPU - { - DMA_LOG("IPU1dma EXECUTE, value=0x%x\n", value); - DmaExec(dmaIPU1, mem, value); - return false; - } - - icase(D5_CHCR) // dma5 - sif0 - { - DMA_LOG("SIF0dma EXECUTE, value=0x%x", value); - DmaExec(dmaSIF0, mem, value); - return false; - } - - icase(D6_CHCR) // dma6 - sif1 - { - DMA_LOG("SIF1dma EXECUTE, value=0x%x", value); - DmaExec(dmaSIF1, mem, value); - return false; - } - - icase(D7_CHCR) // dma7 - sif2 - { - DMA_LOG("SIF2dma EXECUTE, value=0x%x", value); - DmaExec(dmaSIF2, mem, value); - return false; - } - - icase(D8_CHCR) // dma8 - fromSPR - { - DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x", value); - DmaExec(dmaSPR0, mem, value); - return false; - } - - icase(D9_CHCR) // dma9 - toSPR - { - DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x", value); - DmaExec(dmaSPR1, mem, value); - return false; - } - - icase(DMAC_CTRL) - { - u32 oldvalue = psHu32(mem); - - HW_LOG("DMAC_CTRL Write 32bit %x", value); - - psHu32(mem) = value; - //Check for DMAS that were started while the DMAC was disabled - if (((oldvalue & 0x1) == 0) && ((value & 0x1) == 1)) + icase(D0_CHCR) // dma0 - vif0 { - if (!QueuedDMA.empty()) StartQueuedDMA(); + DMA_LOG("VIF0dma EXECUTE, value=0x%x", value); + DmaExec(dmaVIF0, mem, value); + return false; } - if ((oldvalue & 0x30) != (value & 0x30)) + + icase(D1_CHCR) // dma1 - vif1 - chcr { - DevCon.Warning("32bit Stall Source Changed to %x", (value & 0x30) >> 4); + DMA_LOG("VIF1dma EXECUTE, value=0x%x", value); + DmaExec(dmaVIF1, mem, value); + return false; } - if ((oldvalue & 0xC0) != (value & 0xC0)) + + icase(D2_CHCR) // dma2 - gif { - DevCon.Warning("32bit Stall Destination Changed to %x", (value & 0xC0) >> 4); + DMA_LOG("GIFdma EXECUTE, value=0x%x", value); + DmaExec(dmaGIF, mem, value); + return false; } - return false; - } - icase(DMAC_STAT) - { - HW_LOG("DMAC_STAT Write 32bit %x", value); - - // lower 16 bits: clear on 1 - // upper 16 bits: reverse on 1 - - psHu16(0xe010) &= ~(value & 0xffff); - psHu16(0xe012) ^= (u16)(value >> 16); - - cpuTestDMACInts(); - return false; - } - - icase(DMAC_ENABLEW) - { - HW_LOG("DMAC_ENABLEW Write 32bit %lx", value); - oldvalue = psHu8(DMAC_ENABLEW + 2); - psHu32(DMAC_ENABLEW) = value; - psHu32(DMAC_ENABLER) = value; - if (((oldvalue & 0x1) == 1) && (((value >> 16) & 0x1) == 0)) + icase(D3_CHCR) // dma3 - fromIPU { - if (!QueuedDMA.empty()) StartQueuedDMA(); + DMA_LOG("IPU0dma EXECUTE, value=0x%x\n", value); + DmaExec(dmaIPU0, mem, value); + return false; + } + + icase(D4_CHCR) // dma4 - toIPU + { + DMA_LOG("IPU1dma EXECUTE, value=0x%x\n", value); + DmaExec(dmaIPU1, mem, value); + return false; + } + + icase(D5_CHCR) // dma5 - sif0 + { + DMA_LOG("SIF0dma EXECUTE, value=0x%x", value); + DmaExec(dmaSIF0, mem, value); + return false; + } + + icase(D6_CHCR) // dma6 - sif1 + { + DMA_LOG("SIF1dma EXECUTE, value=0x%x", value); + DmaExec(dmaSIF1, mem, value); + return false; + } + + icase(D7_CHCR) // dma7 - sif2 + { + DMA_LOG("SIF2dma EXECUTE, value=0x%x", value); + DmaExec(dmaSIF2, mem, value); + return false; + } + + icase(D8_CHCR) // dma8 - fromSPR + { + DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x", value); + DmaExec(dmaSPR0, mem, value); + return false; + } + + icase(D9_CHCR) // dma9 - toSPR + { + DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x", value); + DmaExec(dmaSPR1, mem, value); + return false; + } + + icase(DMAC_CTRL) + { + u32 oldvalue = psHu32(mem); + + HW_LOG("DMAC_CTRL Write 32bit %x", value); + + psHu32(mem) = value; + //Check for DMAS that were started while the DMAC was disabled + if (((oldvalue & 0x1) == 0) && ((value & 0x1) == 1)) + { + if (!QueuedDMA.empty()) StartQueuedDMA(); + } + if ((oldvalue & 0x30) != (value & 0x30)) + { + DevCon.Warning("32bit Stall Source Changed to %x", (value & 0x30) >> 4); + } + if ((oldvalue & 0xC0) != (value & 0xC0)) + { + DevCon.Warning("32bit Stall Destination Changed to %x", (value & 0xC0) >> 4); + } + return false; + } + + //Midway are a bunch of idiots, writing to E100 (reserved) instead of E010 + //Which causes a CPCOND0 to fail. + icase(DMAC_FAKESTAT) + { + DevCon.Warning("Midway fixup addr=%x writing %x for DMA_STAT", mem, value); + HW_LOG("Midways own DMAC_STAT Write 32bit %x", value); + + // lower 16 bits: clear on 1 + // upper 16 bits: reverse on 1 + + psHu16(0xe010) &= ~(value & 0xffff); + psHu16(0xe012) ^= (u16)(value >> 16); + + cpuTestDMACInts(); + return false; + } + icase(DMAC_STAT) + { + HW_LOG("DMAC_STAT Write 32bit %x", value); + + // lower 16 bits: clear on 1 + // upper 16 bits: reverse on 1 + + psHu16(0xe010) &= ~(value & 0xffff); + psHu16(0xe012) ^= (u16)(value >> 16); + + cpuTestDMACInts(); + return false; + } + + icase(DMAC_ENABLEW) + { + HW_LOG("DMAC_ENABLEW Write 32bit %lx", value); + oldvalue = psHu8(DMAC_ENABLEW + 2); + psHu32(DMAC_ENABLEW) = value; + psHu32(DMAC_ENABLER) = value; + if (((oldvalue & 0x1) == 1) && (((value >> 16) & 0x1) == 0)) + { + if (!QueuedDMA.empty()) StartQueuedDMA(); + } + return false; } - return false; - } } //DMA Writes are invalid to everything except the STR on CHCR when it is busy