mirror of https://github.com/PCSX2/pcsx2.git
Cleaned a few things up, and moved a few things around.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@978 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
parent
12adbcc061
commit
fa1a79b368
34
pcsx2/GS.cpp
34
pcsx2/GS.cpp
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@ -24,16 +24,27 @@
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#include "GS.h"
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#include "GS.h"
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#include "iR5900.h"
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#include "iR5900.h"
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#include "Counters.h"
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#include "Counters.h"
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#include "VifDma.h"
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#include "VifDma.h"
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using namespace Threading;
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using namespace Threading;
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using namespace std;
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using namespace std;
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using namespace R5900;
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using namespace R5900;
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static bool m_gsOpened = false;
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static bool m_gsOpened = false;
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u32 CSRw;
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PCSX2_ALIGNED16( u8 g_RealGSMem[0x2000] );
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extern int m_nCounters[];
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// FrameSkipping Stuff
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// Yuck, iSlowStart is needed by the MTGS, so can't make it static yet.
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u64 m_iSlowStart=0;
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static s64 m_iSlowTicks=0;
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static bool m_justSkipped = false;
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static bool m_StrictSkipping = false;
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#ifdef PCSX2_DEVBUILD
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#ifdef PCSX2_DEVBUILD
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// GS Playback
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// GS Playback
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@ -98,21 +109,6 @@ __forceinline void GSVSYNC(void) {
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}
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}
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#endif
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#endif
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u32 CSRw;
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PCSX2_ALIGNED16( u8 g_RealGSMem[0x2000] );
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#define PS2GS_BASE(mem) (g_RealGSMem+(mem&0x13ff))
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extern int m_nCounters[];
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// FrameSkipping Stuff
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// Yuck, iSlowStart is needed by the MTGS, so can't make it static yet.
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u64 m_iSlowStart=0;
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static s64 m_iSlowTicks=0;
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static bool m_justSkipped = false;
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static bool m_StrictSkipping = false;
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void _gs_ChangeTimings( u32 framerate, u32 iTicks )
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void _gs_ChangeTimings( u32 framerate, u32 iTicks )
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{
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{
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m_iSlowStart = GetCPUTicks();
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m_iSlowStart = GetCPUTicks();
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@ -839,8 +835,6 @@ void RunGSState( gzLoadingState& f )
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list<GSStatePacket>::iterator it = packets.begin();
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list<GSStatePacket>::iterator it = packets.begin();
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g_SaveGSStream = 3;
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g_SaveGSStream = 3;
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//int skipfirst = 1;
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// first extract the data
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// first extract the data
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while(1) {
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while(1) {
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@ -877,4 +871,4 @@ void RunGSState( gzLoadingState& f )
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#endif
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#endif
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#undef GIFchain
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//#undef GIFchain
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@ -28,9 +28,6 @@
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using std::min;
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using std::min;
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#define gif ((DMACh*)&psH[0xA000])
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#define spr0 ((DMACh*)&PS2MEM_HW[0xD000])
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enum gifstate_t
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enum gifstate_t
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{
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{
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GIF_STATE_EMPTY = 0,
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GIF_STATE_EMPTY = 0,
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@ -49,6 +46,7 @@ static int gspath3done = 0;
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static u32 gscycles = 0, prevcycles = 0, mfifocycles = 0;
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static u32 gscycles = 0, prevcycles = 0, mfifocycles = 0;
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static u32 gifqwc = 0;
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static u32 gifqwc = 0;
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bool gifmfifoirq = FALSE;
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__forceinline void gsInterrupt() {
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__forceinline void gsInterrupt() {
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GIF_LOG("gsInterrupt: %8.8x", cpuRegs.cycle);
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GIF_LOG("gsInterrupt: %8.8x", cpuRegs.cycle);
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@ -151,7 +149,7 @@ int _GIFchain() {
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return (qwc)*2;
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return (qwc)*2;
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}
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}
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__forceinline void GIFchain()
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static __forceinline void GIFchain()
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{
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{
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FreezeRegs(1);
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FreezeRegs(1);
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if (gif->qwc) gscycles+= _GIFchain(); /* guessing */
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if (gif->qwc) gscycles+= _GIFchain(); /* guessing */
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@ -243,14 +241,10 @@ void GIFdma()
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}
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}
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}
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}
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}
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}
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// When MTGS is enabled, Gifchain calls WRITERING_DMA, which calls GSRINGBUF_DONECOPY, which freezes
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// the registers inside of the FreezeXMMRegs calls here and in the other two below..
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// I'm not really sure that is intentional. --arcum42
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GIFchain();
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GIFchain();
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// Theres a comment below that says not to unfreeze the xmm regs, so not sure about freezing and unfreezing in GIFchain.
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if((gif->qwc == 0) && ((gspath3done == 1) || (gif->chcr & 0xc) == 0)){
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if((gif->qwc == 0) && ((gspath3done == 1) || (gif->chcr & 0xc) == 0)){
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//if(gif->qwc > 0) Console::WriteLn("Hurray!"); // We *know* it is 0!
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gspath3done = 0;
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gspath3done = 0;
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gif->chcr &= ~0x100;
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gif->chcr &= ~0x100;
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GSCSRr &= ~0xC000;
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GSCSRr &= ~0xC000;
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@ -445,7 +439,6 @@ static __forceinline int mfifoGIFchain() {
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return 0;
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return 0;
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}
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}
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bool gifmfifoirq = FALSE;
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void mfifoGIFtransfer(int qwc) {
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void mfifoGIFtransfer(int qwc) {
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u32 *ptag;
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u32 *ptag;
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@ -521,12 +514,15 @@ void mfifoGIFtransfer(int qwc) {
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gifmfifoirq = TRUE;
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gifmfifoirq = TRUE;
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}
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}
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}
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}
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FreezeRegs(1);
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FreezeRegs(1);
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if (mfifoGIFchain() == -1) {
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if (mfifoGIFchain() == -1) {
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Console::WriteLn("GIF dmaChain error size=%d, madr=%lx, tadr=%lx", params
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Console::WriteLn("GIF dmaChain error size=%d, madr=%lx, tadr=%lx", params
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gif->qwc, gif->madr, gif->tadr);
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gif->qwc, gif->madr, gif->tadr);
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gifstate = GIF_STATE_STALL;
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gifstate = GIF_STATE_STALL;
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}
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}
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FreezeRegs(0);
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FreezeRegs(0);
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if(gif->qwc == 0 && gifstate == GIF_STATE_DONE) gifstate = GIF_STATE_STALL;
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if(gif->qwc == 0 && gifstate == GIF_STATE_DONE) gifstate = GIF_STATE_STALL;
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59
pcsx2/Hw.h
59
pcsx2/Hw.h
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@ -21,25 +21,16 @@
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extern u8 *psH; // hw mem
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extern u8 *psH; // hw mem
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#define psHs8(mem) (*(s8 *)&PS2MEM_HW[(mem) & 0xffff])
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#define psHs16(mem) (*(s16*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHs32(mem) (*(s32*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHs64(mem) (*(s64*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu8(mem) (*(u8 *)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu16(mem) (*(u16*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu32(mem) (*(u32*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu64(mem) (*(u64*)&PS2MEM_HW[(mem) & 0xffff])
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extern void CPU_INT( u32 n, s32 ecycle );
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extern void CPU_INT( u32 n, s32 ecycle );
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//////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////
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// Hardware FIFOs (128 bit access only!)
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// Hardware FIFOs (128 bit access only!)
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//
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//
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// VIF0 -- 0x10004000 -- psH[0x4000]
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// VIF0 -- 0x10004000 -- PS2MEM_HW[0x4000]
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// VIF1 -- 0x10005000 -- psH[0x5000]
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// VIF1 -- 0x10005000 -- PS2MEM_HW[0x5000]
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// GIF -- 0x10006000 -- psH[0x6000]
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// GIF -- 0x10006000 -- PS2MEM_HW[0x6000]
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// IPUout -- 0x10007000 -- psH[0x7000]
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// IPUout -- 0x10007000 -- PS2MEM_HW[0x7000]
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// IPUin -- 0x10007010 -- psH[0x7010]
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// IPUin -- 0x10007010 -- PS2MEM_HW[0x7010]
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void __fastcall ReadFIFO_page_4(u32 mem, mem128_t *out);
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void __fastcall ReadFIFO_page_4(u32 mem, mem128_t *out);
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void __fastcall ReadFIFO_page_5(u32 mem, mem128_t *out);
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void __fastcall ReadFIFO_page_5(u32 mem, mem128_t *out);
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#define INTC_GS 0
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#define INTC_GS 0
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#define INTC_SBUS 1
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#define INTC_SBUS 1
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#define INTC_VBLANK_S 2
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#define INTC_VBLANK_S 2
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#define INTC_VBLANK_E 3
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#define INTC_VBLANK_E 3
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#define INTC_VIF0 4
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#define INTC_VIF0 4
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#define INTC_VIF1 5
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#define INTC_VIF1 5
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#define INTC_VU0 6
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#define INTC_VU0 6
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#define SISintr (0x20002000)
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#define SISintr (0x20002000)
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#define MEISintr (0x40004000)
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#define MEISintr (0x40004000)
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#define DMAend(dma, num) { \
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dma->chcr &= ~0x100; \
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psHu32(DMAC_STAT)|= 1<<num; \
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return; \
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}
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#define DMAerror(dma, num) { \
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psHu32(DMAC_STAT)|= 1<<15; /* BUS error */ \
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DMAend(dma, num); \
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}
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#define _dmaGetAddr(dma, ptr, addr, num) \
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ptr = (u32*)dmaGetAddr(addr); \
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if (ptr == NULL) DMAerror(dma, num);
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#ifdef PCSX2_VIRTUAL_MEM
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#ifdef PCSX2_VIRTUAL_MEM
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#define dmaGetAddrBase(addr) (((addr) & 0x80000000) ? (void*)&PS2MEM_SCRATCH[(addr) & 0x3ff0] : (void*)(PS2MEM_BASE+TRANSFORM_ADDR(addr)))
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#define dmaGetAddrBase(addr) (((addr) & 0x80000000) ? (void*)&PS2MEM_SCRATCH[(addr) & 0x3ff0] : (void*)(PS2MEM_BASE+TRANSFORM_ADDR(addr)))
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// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
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// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); }
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if (addr & 0x80000000) { // teh sux why the f00k 0xE0000000
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// teh sux why the f00k 0xE0000000
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return (void*)&psS[addr & 0x3ff0];
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if (addr & 0x80000000) return (void*)&psS[addr & 0x3ff0];
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}
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ptr = (u8*)vtlb_GetPhyPtr(addr&0x1FFFFFF0);
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ptr = (u8*)vtlb_GetPhyPtr(addr&0x1FFFFFF0);
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if (ptr == NULL) {
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if (ptr == NULL) {
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@ -363,6 +338,22 @@ static __forceinline void *dmaGetAddr(u32 addr) {
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#endif
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#endif
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static __forceinline u32 *_dmaGetAddr(DMACh *dma, u32 addr, u32 num)
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{
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u32 *ptr = (u32*)dmaGetAddr(addr);
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if (ptr == NULL)
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{
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// DMA Error
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psHu32(DMAC_STAT)|= 1<<15; /* BUS error */
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// DMA End
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psHu32(DMAC_STAT)|= 1<<num;
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dma->chcr &= ~0x100;
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}
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return ptr;
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}
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void hwInit();
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void hwInit();
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void hwReset();
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void hwReset();
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void hwShutdown();
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void hwShutdown();
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# define IPU_FORCEINLINE __forceinline
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# define IPU_FORCEINLINE __forceinline
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#endif
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#endif
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//IPUregisters g_ipuRegsReal;
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#define ipu0dma ((DMACh *)&PS2MEM_HW[0xb000])
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#define ipu1dma ((DMACh *)&PS2MEM_HW[0xb400])
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#define IPU_DMA_GIFSTALL 1
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#define IPU_DMA_GIFSTALL 1
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#define IPU_DMA_TIE0 2
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#define IPU_DMA_TIE0 2
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#define IPU_DMA_TIE1 4
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#define IPU_DMA_TIE1 4
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#endif
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#endif
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//#define ENABLECACHE
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//#define ENABLECACHE
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#include "vtlb.h"
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namespace Ps2MemSize
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namespace Ps2MemSize
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{
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{
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extern u8 g_RealGSMem[Ps2MemSize::GSregs];
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extern u8 g_RealGSMem[Ps2MemSize::GSregs];
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#define PS2MEM_GS g_RealGSMem
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#define PS2MEM_GS g_RealGSMem
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#define PS2GS_BASE(mem) (g_RealGSMem+(mem&0x13ff))
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// Various useful locations
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#define spr0 ((DMACh*)&PS2MEM_HW[0xD000])
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#define spr1 ((DMACh*)&PS2MEM_HW[0xD400])
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#define gif ((DMACh*)&PS2MEM_HW[0xA000])
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#define vif0ch ((DMACh*)&PS2MEM_HW[0x8000])
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#define vif1ch ((DMACh*)&PS2MEM_HW[0x9000])
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#define sif0dma ((DMACh*)&PS2MEM_HW[0xc000])
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#define sif1dma ((DMACh*)&PS2MEM_HW[0xc400])
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#define sif2dma ((DMACh*)&PS2MEM_HW[0xc800])
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#define ipu0dma ((DMACh *)&PS2MEM_HW[0xb000])
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#define ipu1dma ((DMACh *)&PS2MEM_HW[0xb400])
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// From Gif.h
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#define GSCSRr *((u64*)(g_RealGSMem+0x1000))
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#define GSIMR *((u32*)(g_RealGSMem+0x1010))
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#define GSSIGLBLID ((GSRegSIGBLID*)(g_RealGSMem+0x1080))
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#define PSM(mem) (vtlb_GetPhyPtr((mem)&0x1fffffff)) //pcsx2 is a competition.The one with most hacks wins :D
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#define PSM(mem) (vtlb_GetPhyPtr((mem)&0x1fffffff)) //pcsx2 is a competition.The one with most hacks wins :D
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#define psHs8(mem) (*(s8 *)&PS2MEM_HW[(mem) & 0xffff])
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#define psHs16(mem) (*(s16*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHs32(mem) (*(s32*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHs64(mem) (*(s64*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu8(mem) (*(u8 *)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu16(mem) (*(u16*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu32(mem) (*(u32*)&PS2MEM_HW[(mem) & 0xffff])
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#define psHu64(mem) (*(u64*)&PS2MEM_HW[(mem) & 0xffff])
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#define psMs8(mem) (*(s8 *)&PS2MEM_BASE[(mem) & 0x1ffffff])
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#define psMs8(mem) (*(s8 *)&PS2MEM_BASE[(mem) & 0x1ffffff])
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#define psMs16(mem) (*(s16*)&PS2MEM_BASE[(mem) & 0x1ffffff])
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#define psMs16(mem) (*(s16*)&PS2MEM_BASE[(mem) & 0x1ffffff])
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#define psMs32(mem) (*(s32*)&PS2MEM_BASE[(mem) & 0x1ffffff])
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#define psMs32(mem) (*(s32*)&PS2MEM_BASE[(mem) & 0x1ffffff])
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@ -134,8 +166,6 @@ extern void memClearPageAddr(u32 vaddr);
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extern void memMapVUmicro();
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extern void memMapVUmicro();
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#include "vtlb.h"
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extern int mmap_GetRamPageInfo(void* ptr);
|
extern int mmap_GetRamPageInfo(void* ptr);
|
||||||
extern void mmap_MarkCountedRamPage(void* ptr,u32 vaddr);
|
extern void mmap_MarkCountedRamPage(void* ptr,u32 vaddr);
|
||||||
extern void mmap_ResetBlockTracking();
|
extern void mmap_ResetBlockTracking();
|
||||||
|
|
|
@ -23,10 +23,6 @@
|
||||||
#include "iR5900.h"
|
#include "iR5900.h"
|
||||||
#include "VUmicro.h"
|
#include "VUmicro.h"
|
||||||
|
|
||||||
#define spr0 ((DMACh*)&PS2MEM_HW[0xD000])
|
|
||||||
#define spr1 ((DMACh*)&PS2MEM_HW[0xD400])
|
|
||||||
#define gif ((DMACh*)&PS2MEM_HW[0xA000])
|
|
||||||
|
|
||||||
extern void mfifoGIFtransfer(int);
|
extern void mfifoGIFtransfer(int);
|
||||||
|
|
||||||
/* Both of these should be bools. Again, next savestate break. --arcum42 */
|
/* Both of these should be bools. Again, next savestate break. --arcum42 */
|
||||||
|
@ -66,8 +62,10 @@ int _SPR0chain()
|
||||||
|
|
||||||
if ((psHu32(DMAC_CTRL) & 0xC) >= 0x8) // 0x8 VIF1 MFIFO, 0xC GIF MFIFO
|
if ((psHu32(DMAC_CTRL) & 0xC) >= 0x8) // 0x8 VIF1 MFIFO, 0xC GIF MFIFO
|
||||||
{
|
{
|
||||||
if ((spr0->madr & ~psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR)) Console::WriteLn("SPR MFIFO Write outside MFIFO area");
|
if ((spr0->madr & ~psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR))
|
||||||
else mfifotransferred += spr0->qwc;
|
Console::WriteLn("SPR MFIFO Write outside MFIFO area");
|
||||||
|
else
|
||||||
|
mfifotransferred += spr0->qwc;
|
||||||
|
|
||||||
hwMFIFOWrite(spr0->madr, (u8*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
|
hwMFIFOWrite(spr0->madr, (u8*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
|
||||||
spr0->madr += spr0->qwc << 4;
|
spr0->madr += spr0->qwc << 4;
|
||||||
|
@ -89,9 +87,11 @@ int _SPR0chain()
|
||||||
return (spr0->qwc) * BIAS; // bus is 1/2 the ee speed
|
return (spr0->qwc) * BIAS; // bus is 1/2 the ee speed
|
||||||
}
|
}
|
||||||
|
|
||||||
#define SPR0chain() \
|
__forceinline void SPR0chain()
|
||||||
cycles += _SPR0chain(); \
|
{
|
||||||
|
_SPR0chain();
|
||||||
spr0->qwc = 0;
|
spr0->qwc = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
void _SPR0interleave()
|
void _SPR0interleave()
|
||||||
|
@ -99,7 +99,6 @@ void _SPR0interleave()
|
||||||
int qwc = spr0->qwc;
|
int qwc = spr0->qwc;
|
||||||
int sqwc = psHu32(DMAC_SQWC) & 0xff;
|
int sqwc = psHu32(DMAC_SQWC) & 0xff;
|
||||||
int tqwc = (psHu32(DMAC_SQWC) >> 16) & 0xff;
|
int tqwc = (psHu32(DMAC_SQWC) >> 16) & 0xff;
|
||||||
//int cycles = 0;
|
|
||||||
u32 *pMem;
|
u32 *pMem;
|
||||||
|
|
||||||
if (tqwc == 0) tqwc = qwc;
|
if (tqwc == 0) tqwc = qwc;
|
||||||
|
@ -124,9 +123,8 @@ void _SPR0interleave()
|
||||||
TestClearVUs(spr0->madr, spr0->qwc << 2);
|
TestClearVUs(spr0->madr, spr0->qwc << 2);
|
||||||
memcpy_fast((u8*)pMem, &PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
|
memcpy_fast((u8*)pMem, &PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
|
||||||
}
|
}
|
||||||
//cycles += tqwc * BIAS;
|
|
||||||
spr0->sadr += spr0->qwc * 16;
|
spr0->sadr += spr0->qwc * 16;
|
||||||
spr0->madr += (sqwc + spr0->qwc) * 16; //qwc-= sqwc;
|
spr0->madr += (sqwc + spr0->qwc) * 16;
|
||||||
}
|
}
|
||||||
|
|
||||||
spr0->qwc = 0;
|
spr0->qwc = 0;
|
||||||
|
@ -143,15 +141,12 @@ static __forceinline void _dmaSPR0()
|
||||||
// Transfer Dn_QWC from SPR to Dn_MADR
|
// Transfer Dn_QWC from SPR to Dn_MADR
|
||||||
if ((spr0->chcr & 0xc) == 0x0) // Normal Mode
|
if ((spr0->chcr & 0xc) == 0x0) // Normal Mode
|
||||||
{
|
{
|
||||||
int cycles = 0;
|
|
||||||
SPR0chain();
|
SPR0chain();
|
||||||
spr0finished = 1;
|
spr0finished = 1;
|
||||||
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
else if ((spr0->chcr & 0xc) == 0x4)
|
else if ((spr0->chcr & 0xc) == 0x4)
|
||||||
{
|
{
|
||||||
int cycles = 0;
|
|
||||||
u32 *ptag;
|
u32 *ptag;
|
||||||
int id;
|
int id;
|
||||||
bool done = FALSE;
|
bool done = FALSE;
|
||||||
|
@ -167,7 +162,6 @@ static __forceinline void _dmaSPR0()
|
||||||
spr0->sadr += 16;
|
spr0->sadr += 16;
|
||||||
|
|
||||||
// Transfer dma tag if tte is set
|
// Transfer dma tag if tte is set
|
||||||
|
|
||||||
spr0->chcr = (spr0->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15
|
spr0->chcr = (spr0->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15
|
||||||
|
|
||||||
id = (ptag[0] >> 28) & 0x7; //ID for DmaChain copied from bit 28 of the tag
|
id = (ptag[0] >> 28) & 0x7; //ID for DmaChain copied from bit 28 of the tag
|
||||||
|
@ -201,7 +195,6 @@ static __forceinline void _dmaSPR0()
|
||||||
{
|
{
|
||||||
//Console::WriteLn("SPR0 TIE");
|
//Console::WriteLn("SPR0 TIE");
|
||||||
done = TRUE;
|
done = TRUE;
|
||||||
spr0->qwc = 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
spr0finished = (done) ? 1 : 0;
|
spr0finished = (done) ? 1 : 0;
|
||||||
|
@ -209,9 +202,7 @@ static __forceinline void _dmaSPR0()
|
||||||
if (!done)
|
if (!done)
|
||||||
{
|
{
|
||||||
ptag = (u32*) & PS2MEM_SCRATCH[spr0->sadr & 0x3fff]; //Set memory pointer to SADR
|
ptag = (u32*) & PS2MEM_SCRATCH[spr0->sadr & 0x3fff]; //Set memory pointer to SADR
|
||||||
//spr0->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
|
CPU_INT(8, ((u16)ptag[0]) / BIAS); // the lower 16bits of the tag / BIAS);
|
||||||
CPU_INT(8, ((u16)ptag[0]) / BIAS); //spr0->qwc / BIAS);
|
|
||||||
spr0->qwc = 0;
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
SPR_LOG("spr0 dmaChain complete %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx",
|
SPR_LOG("spr0 dmaChain complete %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx",
|
||||||
|
@ -292,9 +283,11 @@ int _SPR1chain()
|
||||||
return (spr1->qwc) * BIAS;
|
return (spr1->qwc) * BIAS;
|
||||||
}
|
}
|
||||||
|
|
||||||
#define SPR1chain() \
|
__forceinline void SPR1chain()
|
||||||
cycles += _SPR1chain(); \
|
{
|
||||||
spr1->qwc = 0;
|
_SPR1chain();
|
||||||
|
spr1->qwc = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
void _SPR1interleave()
|
void _SPR1interleave()
|
||||||
|
@ -302,7 +295,6 @@ void _SPR1interleave()
|
||||||
int qwc = spr1->qwc;
|
int qwc = spr1->qwc;
|
||||||
int sqwc = psHu32(DMAC_SQWC) & 0xff;
|
int sqwc = psHu32(DMAC_SQWC) & 0xff;
|
||||||
int tqwc = (psHu32(DMAC_SQWC) >> 16) & 0xff;
|
int tqwc = (psHu32(DMAC_SQWC) >> 16) & 0xff;
|
||||||
//int cycles = 0;
|
|
||||||
u32 *pMem;
|
u32 *pMem;
|
||||||
|
|
||||||
if (tqwc == 0) tqwc = qwc;
|
if (tqwc == 0) tqwc = qwc;
|
||||||
|
@ -316,8 +308,7 @@ void _SPR1interleave()
|
||||||
pMem = (u32*)dmaGetAddr(spr1->madr);
|
pMem = (u32*)dmaGetAddr(spr1->madr);
|
||||||
memcpy_fast(&PS2MEM_SCRATCH[spr1->sadr & 0x3fff], (u8*)pMem, spr1->qwc << 4);
|
memcpy_fast(&PS2MEM_SCRATCH[spr1->sadr & 0x3fff], (u8*)pMem, spr1->qwc << 4);
|
||||||
spr1->sadr += spr1->qwc * 16;
|
spr1->sadr += spr1->qwc * 16;
|
||||||
//cycles += spr1->qwc * BIAS;
|
spr1->madr += (sqwc + spr1->qwc) * 16;
|
||||||
spr1->madr += (sqwc + spr1->qwc) * 16; //qwc-= sqwc;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
spr1->qwc = 0;
|
spr1->qwc = 0;
|
||||||
|
@ -328,7 +319,7 @@ void _dmaSPR1() // toSPR work function
|
||||||
{
|
{
|
||||||
if ((spr1->chcr & 0xc) == 0) // Normal Mode
|
if ((spr1->chcr & 0xc) == 0) // Normal Mode
|
||||||
{
|
{
|
||||||
int cycles = 0;
|
//int cycles = 0;
|
||||||
// Transfer Dn_QWC from Dn_MADR to SPR1
|
// Transfer Dn_QWC from Dn_MADR to SPR1
|
||||||
SPR1chain();
|
SPR1chain();
|
||||||
spr1finished = 1;
|
spr1finished = 1;
|
||||||
|
@ -336,7 +327,6 @@ void _dmaSPR1() // toSPR work function
|
||||||
}
|
}
|
||||||
else if ((spr1->chcr & 0xc) == 0x4)
|
else if ((spr1->chcr & 0xc) == 0x4)
|
||||||
{
|
{
|
||||||
int cycles = 0;
|
|
||||||
u32 *ptag;
|
u32 *ptag;
|
||||||
int id;
|
int id;
|
||||||
bool done = FALSE;
|
bool done = FALSE;
|
||||||
|
@ -363,7 +353,7 @@ void _dmaSPR1() // toSPR work function
|
||||||
spr1->chcr = (spr1->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15
|
spr1->chcr = (spr1->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15
|
||||||
|
|
||||||
id = (ptag[0] >> 28) & 0x7; //ID for DmaChain copied from bit 28 of the tag
|
id = (ptag[0] >> 28) & 0x7; //ID for DmaChain copied from bit 28 of the tag
|
||||||
spr1->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
|
spr1->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag until SPR1chain is called in a few lines.
|
||||||
spr1->madr = ptag[1]; //MADR = ADDR field
|
spr1->madr = ptag[1]; //MADR = ADDR field
|
||||||
|
|
||||||
// Transfer dma tag if tte is set
|
// Transfer dma tag if tte is set
|
||||||
|
@ -384,7 +374,6 @@ void _dmaSPR1() // toSPR work function
|
||||||
SPR_LOG("dmaIrq Set");
|
SPR_LOG("dmaIrq Set");
|
||||||
|
|
||||||
//Console::WriteLn("SPR1 TIE");
|
//Console::WriteLn("SPR1 TIE");
|
||||||
spr1->qwc = 0;
|
|
||||||
done = TRUE;
|
done = TRUE;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -392,9 +381,7 @@ void _dmaSPR1() // toSPR work function
|
||||||
if (!done)
|
if (!done)
|
||||||
{
|
{
|
||||||
ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
|
ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
|
||||||
//spr1->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag
|
CPU_INT(9, (((u16)ptag[0]) / BIAS));// the lower 16 bits of the tag / BIAS);
|
||||||
CPU_INT(9, (((u16)ptag[0]) / BIAS));// spr1->qwc / BIAS);
|
|
||||||
spr1->qwc = 0;
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
else // Interleave Mode
|
else // Interleave Mode
|
||||||
|
@ -411,7 +398,7 @@ void dmaSPR1() // toSPR
|
||||||
spr1->chcr, spr1->madr, spr1->qwc,
|
spr1->chcr, spr1->madr, spr1->qwc,
|
||||||
spr1->tadr, spr1->sadr);
|
spr1->tadr, spr1->sadr);
|
||||||
|
|
||||||
if ((spr1->chcr & 0xc) == 0x4 && spr1->qwc == 0)
|
if (((spr1->chcr & 0xc) == 0x4) && (spr1->qwc == 0))
|
||||||
{
|
{
|
||||||
u32 *ptag;
|
u32 *ptag;
|
||||||
ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
|
ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR
|
||||||
|
|
|
@ -25,10 +25,6 @@
|
||||||
|
|
||||||
using namespace std;
|
using namespace std;
|
||||||
|
|
||||||
#define sif0dma ((DMACh*)&PS2MEM_HW[0xc000])
|
|
||||||
#define sif1dma ((DMACh*)&PS2MEM_HW[0xc400])
|
|
||||||
#define sif2dma ((DMACh*)&PS2MEM_HW[0xc800])
|
|
||||||
|
|
||||||
DMACh *sif0ch;
|
DMACh *sif0ch;
|
||||||
DMACh *sif1ch;
|
DMACh *sif1ch;
|
||||||
DMACh *sif2ch;
|
DMACh *sif2ch;
|
||||||
|
@ -206,7 +202,10 @@ __forceinline void SIF0Dma()
|
||||||
//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr);
|
//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr);
|
||||||
SIF_LOG("----------- %lX of %lX", readSize << 2, size << 2);
|
SIF_LOG("----------- %lX of %lX", readSize << 2, size << 2);
|
||||||
|
|
||||||
_dmaGetAddr(sif0dma, ptag, sif0dma->madr, 5);
|
ptag = _dmaGetAddr(sif0dma, sif0dma->madr, 5);
|
||||||
|
if (ptag == NULL) return;
|
||||||
|
|
||||||
|
//_dmaGetAddr(sif0dma, *ptag, sif0dma->madr, 5);
|
||||||
|
|
||||||
SIF0read((u32*)ptag, readSize << 2);
|
SIF0read((u32*)ptag, readSize << 2);
|
||||||
|
|
||||||
|
@ -285,7 +284,12 @@ __forceinline void SIF1Dma()
|
||||||
{
|
{
|
||||||
// Process DMA tag at sif1dma->tadr
|
// Process DMA tag at sif1dma->tadr
|
||||||
done = FALSE;
|
done = FALSE;
|
||||||
_dmaGetAddr(sif1dma, ptag, sif1dma->tadr, 6);
|
ptag = _dmaGetAddr(sif1dma, sif1dma->tadr, 6);
|
||||||
|
if (ptag == NULL) return;
|
||||||
|
|
||||||
|
//_dmaGetAddr(sif1dma, *ptag, sif1dma->tadr, 6);
|
||||||
|
|
||||||
|
|
||||||
sif1dma->chcr = (sif1dma->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); // Copy the tag
|
sif1dma->chcr = (sif1dma->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); // Copy the tag
|
||||||
sif1dma->qwc = (u16)ptag[0];
|
sif1dma->qwc = (u16)ptag[0];
|
||||||
|
|
||||||
|
@ -348,7 +352,10 @@ __forceinline void SIF1Dma()
|
||||||
int qwTransfer = sif1dma->qwc;
|
int qwTransfer = sif1dma->qwc;
|
||||||
u32 *data;
|
u32 *data;
|
||||||
|
|
||||||
_dmaGetAddr(sif1dma, data, sif1dma->madr, 6);
|
data = _dmaGetAddr(sif1dma, sif1dma->madr, 6);
|
||||||
|
if (data == NULL) return;
|
||||||
|
|
||||||
|
//_dmaGetAddr(sif1dma, *data, sif1dma->madr, 6);
|
||||||
|
|
||||||
if (qwTransfer > (FIFO_SIF1_W - sif1.fifoSize) / 4) // Copy part of sif1dma into FIFO
|
if (qwTransfer > (FIFO_SIF1_W - sif1.fifoSize) / 4) // Copy part of sif1dma into FIFO
|
||||||
qwTransfer = (FIFO_SIF1_W - sif1.fifoSize) / 4;
|
qwTransfer = (FIFO_SIF1_W - sif1.fifoSize) / 4;
|
||||||
|
|
|
@ -427,7 +427,7 @@ void mfifoVIF1transfer(int qwc)
|
||||||
{
|
{
|
||||||
u32 *ptag;
|
u32 *ptag;
|
||||||
int id;
|
int id;
|
||||||
int ret, temp;
|
int ret;
|
||||||
|
|
||||||
g_vifCycles = 0;
|
g_vifCycles = 0;
|
||||||
|
|
||||||
|
@ -493,12 +493,14 @@ void mfifoVIF1transfer(int qwc)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case 2: // Next - Transfer QWC following tag. TADR = ADDR
|
case 2: // Next - Transfer QWC following tag. TADR = ADDR
|
||||||
temp = vif1ch->madr; //Temporarily Store ADDR
|
{
|
||||||
|
int temp = vif1ch->madr; //Temporarily Store ADDR
|
||||||
vif1ch->madr = psHu32(DMAC_RBOR) + ((vif1ch->tadr + 16) & psHu32(DMAC_RBSR)); //Set MADR to QW following the tag
|
vif1ch->madr = psHu32(DMAC_RBOR) + ((vif1ch->tadr + 16) & psHu32(DMAC_RBSR)); //Set MADR to QW following the tag
|
||||||
vif1ch->tadr = temp; //Copy temporarily stored ADDR to Tag
|
vif1ch->tadr = temp; //Copy temporarily stored ADDR to Tag
|
||||||
if ((temp & psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR)) Console::WriteLn("Next tag = %x outside ring %x size %x", params temp, psHu32(DMAC_RBOR), psHu32(DMAC_RBSR));
|
if ((temp & psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR)) Console::WriteLn("Next tag = %x outside ring %x size %x", params temp, psHu32(DMAC_RBOR), psHu32(DMAC_RBSR));
|
||||||
vif1.done = 0;
|
vif1.done = 0;
|
||||||
break;
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
case 3: // Ref - Transfer QWC from ADDR field
|
case 3: // Ref - Transfer QWC from ADDR field
|
||||||
case 4: // Refs - Transfer QWC from ADDR field (Stall Control)
|
case 4: // Refs - Transfer QWC from ADDR field (Stall Control)
|
||||||
|
|
|
@ -171,7 +171,6 @@ static __forceinline u32 getVifColRegs(u32 reg)
|
||||||
|
|
||||||
#define vif0Regs ((VIFregisters*)&PS2MEM_HW[0x3800])
|
#define vif0Regs ((VIFregisters*)&PS2MEM_HW[0x3800])
|
||||||
#define vif1Regs ((VIFregisters*)&PS2MEM_HW[0x3c00])
|
#define vif1Regs ((VIFregisters*)&PS2MEM_HW[0x3c00])
|
||||||
#define spr0 ((DMACh*)&PS2MEM_HW[0xD000])
|
|
||||||
|
|
||||||
void dmaVIF0();
|
void dmaVIF0();
|
||||||
void dmaVIF1();
|
void dmaVIF1();
|
||||||
|
|
|
@ -29,10 +29,6 @@
|
||||||
|
|
||||||
using namespace std; // for min / max
|
using namespace std; // for min / max
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#define gif ((DMACh*)&PS2MEM_HW[0xA000])
|
|
||||||
|
|
||||||
// Extern variables
|
// Extern variables
|
||||||
extern "C"
|
extern "C"
|
||||||
{
|
{
|
||||||
|
@ -66,6 +62,9 @@ int g_vifCycles = 0;
|
||||||
bool path3hack = FALSE;
|
bool path3hack = FALSE;
|
||||||
bool Path3transfer = FALSE;
|
bool Path3transfer = FALSE;
|
||||||
|
|
||||||
|
u32 splittransfer[4];
|
||||||
|
u32 splitptr = 0;
|
||||||
|
|
||||||
typedef void (__fastcall *UNPACKFUNCTYPE)(u32 *dest, u32 *data, int size);
|
typedef void (__fastcall *UNPACKFUNCTYPE)(u32 *dest, u32 *data, int size);
|
||||||
typedef int (*UNPACKPARTFUNCTYPESSE)(u32 *dest, u32 *data, int size);
|
typedef int (*UNPACKPARTFUNCTYPESSE)(u32 *dest, u32 *data, int size);
|
||||||
extern void (*Vif1CMDTLB[82])();
|
extern void (*Vif1CMDTLB[82])();
|
||||||
|
@ -952,6 +951,8 @@ static int __fastcall Vif0TransMPG(u32 *data) // MPG
|
||||||
|
|
||||||
static int __fastcall Vif0TransUnpack(u32 *data) // UNPACK
|
static int __fastcall Vif0TransUnpack(u32 *data) // UNPACK
|
||||||
{
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
FreezeXMMRegs(1);
|
FreezeXMMRegs(1);
|
||||||
if (vif0.vifpacketsize < vif0.tag.size)
|
if (vif0.vifpacketsize < vif0.tag.size)
|
||||||
{
|
{
|
||||||
|
@ -960,35 +961,32 @@ static int __fastcall Vif0TransUnpack(u32 *data) // UNPACK
|
||||||
|
|
||||||
ProcessMemSkip(vif0.vifpacketsize << 2, (vif0.cmd & 0xf), VIF0dmanum);
|
ProcessMemSkip(vif0.vifpacketsize << 2, (vif0.cmd & 0xf), VIF0dmanum);
|
||||||
|
|
||||||
vif0.tag.size -= vif0.vifpacketsize;
|
ret = vif0.vifpacketsize;
|
||||||
FreezeXMMRegs(0);
|
vif0.tag.size -= ret;
|
||||||
return vif0.vifpacketsize;
|
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
/* we got all the data, transfer it fully */
|
/* we got all the data, transfer it fully */
|
||||||
int ret = vif0.tag.size;
|
ret = vif0.tag.size;
|
||||||
|
|
||||||
//Align data after a split transfer first
|
//Align data after a split transfer first
|
||||||
if(vif0Regs->offset != 0 || vif0.cl != 0)
|
if ((vif0Regs->offset != 0) || (vif0.cl != 0))
|
||||||
{
|
{
|
||||||
vif0.tag.size = VIFalign(data, &vif0.tag, vif0.tag.size, VIF0dmanum);
|
vif0.tag.size = VIFalign(data, &vif0.tag, vif0.tag.size, VIF0dmanum);
|
||||||
data += ret - vif0.tag.size;
|
data += ret - vif0.tag.size;
|
||||||
if(vif0.tag.size > 0) VIFunpack(data, &vif0.tag, vif0.tag.size, VIF0dmanum);
|
if(vif0.tag.size > 0) VIFunpack(data, &vif0.tag, vif0.tag.size, VIF0dmanum);
|
||||||
vif0.tag.size = 0;
|
|
||||||
vif0.cmd = 0;
|
|
||||||
FreezeXMMRegs(0);
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
VIFunpack(data, &vif0.tag, vif0.tag.size, VIF0dmanum);
|
VIFunpack(data, &vif0.tag, vif0.tag.size, VIF0dmanum);
|
||||||
vif0.tag.size = 0;
|
|
||||||
vif0.cmd = 0;
|
|
||||||
FreezeXMMRegs(0);
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
vif0.tag.size = 0;
|
||||||
|
vif0.cmd = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
FreezeXMMRegs(0);
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
@ -1694,8 +1692,6 @@ static int __fastcall Vif1TransMPG(u32 *data)
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
u32 splittransfer[4];
|
|
||||||
u32 splitptr = 0;
|
|
||||||
|
|
||||||
static int __fastcall Vif1TransDirectHL(u32 *data)
|
static int __fastcall Vif1TransDirectHL(u32 *data)
|
||||||
{
|
{
|
||||||
|
@ -2371,7 +2367,6 @@ __forceinline void vif1Interrupt()
|
||||||
if (vif1Regs->mskpath3 == 0 || (vif1ch->chcr & 0x1) == 0x1)vif1Regs->stat &= ~0x1F000000; // FQC=0
|
if (vif1Regs->mskpath3 == 0 || (vif1ch->chcr & 0x1) == 0x1)vif1Regs->stat &= ~0x1F000000; // FQC=0
|
||||||
}
|
}
|
||||||
|
|
||||||
#define spr0 ((DMACh*)&PS2MEM_HW[0xD000])
|
|
||||||
void dmaVIF1()
|
void dmaVIF1()
|
||||||
{
|
{
|
||||||
|
|
||||||
|
|
|
@ -50,9 +50,6 @@ struct vifStruct {
|
||||||
extern vifStruct vif0, vif1;
|
extern vifStruct vif0, vif1;
|
||||||
extern bool Path3transfer;
|
extern bool Path3transfer;
|
||||||
|
|
||||||
#define vif0ch ((DMACh*)&PS2MEM_HW[0x8000])
|
|
||||||
#define vif1ch ((DMACh*)&PS2MEM_HW[0x9000])
|
|
||||||
|
|
||||||
void __fastcall UNPACK_S_32( u32 *dest, u32 *data, int size );
|
void __fastcall UNPACK_S_32( u32 *dest, u32 *data, int size );
|
||||||
|
|
||||||
void __fastcall UNPACK_S_16u( u32 *dest, u32 *data, int size );
|
void __fastcall UNPACK_S_16u( u32 *dest, u32 *data, int size );
|
||||||
|
|
|
@ -116,7 +116,7 @@ static u64 PCSX2_ALIGNED16(dbl_ps2_overflow) = DOUBLE(0,1152,0); //overflow & cl
|
||||||
static u64 PCSX2_ALIGNED16(dbl_underflow) = DOUBLE(0,897,0); //underflow if below
|
static u64 PCSX2_ALIGNED16(dbl_underflow) = DOUBLE(0,897,0); //underflow if below
|
||||||
|
|
||||||
static u64 PCSX2_ALIGNED16(dbl_s_pos[2]) = {0x7fffffffffffffffULL, 0};
|
static u64 PCSX2_ALIGNED16(dbl_s_pos[2]) = {0x7fffffffffffffffULL, 0};
|
||||||
static u64 PCSX2_ALIGNED16(dbl_s_neg[2]) = {0x8000000000000000ULL, 0};
|
//static u64 PCSX2_ALIGNED16(dbl_s_neg[2]) = {0x8000000000000000ULL, 0};
|
||||||
|
|
||||||
// converts small normal numbers to double equivalent
|
// converts small normal numbers to double equivalent
|
||||||
// converts large normal numbers (which represent NaN/inf in IEEE) to double equivalent
|
// converts large normal numbers (which represent NaN/inf in IEEE) to double equivalent
|
||||||
|
|
|
@ -837,7 +837,7 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch)
|
||||||
x86SetJ8( j8Ptr[0] );
|
x86SetJ8( j8Ptr[0] );
|
||||||
}
|
}
|
||||||
|
|
||||||
static const int *s_pCode;
|
//static const int *s_pCode;
|
||||||
|
|
||||||
#if !defined(_MSC_VER)
|
#if !defined(_MSC_VER)
|
||||||
static void checkcodefn()
|
static void checkcodefn()
|
||||||
|
|
|
@ -2963,8 +2963,8 @@ int VuInstruction::SetCachedRegs(int upper, u32 vuxyz)
|
||||||
|
|
||||||
void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
|
void VuInstruction::Recompile(list<VuInstruction>::iterator& itinst, u32 vuxyz)
|
||||||
{
|
{
|
||||||
static PCSX2_ALIGNED16(VECTOR _VF);
|
//static PCSX2_ALIGNED16(VECTOR _VF);
|
||||||
static PCSX2_ALIGNED16(VECTOR _VFc);
|
//static PCSX2_ALIGNED16(VECTOR _VFc);
|
||||||
u32 *ptr;
|
u32 *ptr;
|
||||||
u8* pjmp;
|
u8* pjmp;
|
||||||
int vfregstore=0;
|
int vfregstore=0;
|
||||||
|
|
Loading…
Reference in New Issue