From fa1a79b3681d11d9e3d27cfccb98f418b90d907d Mon Sep 17 00:00:00 2001 From: arcum42 Date: Wed, 15 Apr 2009 01:25:11 +0000 Subject: [PATCH] Cleaned a few things up, and moved a few things around. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@978 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/GS.cpp | 34 +++++++++------------- pcsx2/Gif.cpp | 16 ++++------ pcsx2/Hw.h | 63 +++++++++++++++++----------------------- pcsx2/IPU/IPU.cpp | 5 ---- pcsx2/Memory.h | 34 ++++++++++++++++++++-- pcsx2/SPR.cpp | 53 +++++++++++++-------------------- pcsx2/Sif.cpp | 21 +++++++++----- pcsx2/Vif.cpp | 6 ++-- pcsx2/Vif.h | 1 - pcsx2/VifDma.cpp | 35 ++++++++++------------ pcsx2/VifDma.h | 3 -- pcsx2/x86/iFPUd.cpp | 2 +- pcsx2/x86/iR3000A.cpp | 2 +- pcsx2/x86/iVUzerorec.cpp | 4 +-- 14 files changed, 136 insertions(+), 143 deletions(-) diff --git a/pcsx2/GS.cpp b/pcsx2/GS.cpp index 8772c51056..4ff204c57d 100644 --- a/pcsx2/GS.cpp +++ b/pcsx2/GS.cpp @@ -24,16 +24,27 @@ #include "GS.h" #include "iR5900.h" #include "Counters.h" - #include "VifDma.h" using namespace Threading; using namespace std; - using namespace R5900; static bool m_gsOpened = false; +u32 CSRw; + +PCSX2_ALIGNED16( u8 g_RealGSMem[0x2000] ); +extern int m_nCounters[]; + +// FrameSkipping Stuff +// Yuck, iSlowStart is needed by the MTGS, so can't make it static yet. + +u64 m_iSlowStart=0; +static s64 m_iSlowTicks=0; +static bool m_justSkipped = false; +static bool m_StrictSkipping = false; + #ifdef PCSX2_DEVBUILD // GS Playback @@ -98,21 +109,6 @@ __forceinline void GSVSYNC(void) { } #endif -u32 CSRw; - -PCSX2_ALIGNED16( u8 g_RealGSMem[0x2000] ); -#define PS2GS_BASE(mem) (g_RealGSMem+(mem&0x13ff)) - -extern int m_nCounters[]; - -// FrameSkipping Stuff -// Yuck, iSlowStart is needed by the MTGS, so can't make it static yet. - -u64 m_iSlowStart=0; -static s64 m_iSlowTicks=0; -static bool m_justSkipped = false; -static bool m_StrictSkipping = false; - void _gs_ChangeTimings( u32 framerate, u32 iTicks ) { m_iSlowStart = GetCPUTicks(); @@ -839,8 +835,6 @@ void RunGSState( gzLoadingState& f ) list::iterator it = packets.begin(); g_SaveGSStream = 3; - //int skipfirst = 1; - // first extract the data while(1) { @@ -877,4 +871,4 @@ void RunGSState( gzLoadingState& f ) #endif -#undef GIFchain +//#undef GIFchain diff --git a/pcsx2/Gif.cpp b/pcsx2/Gif.cpp index a36c17f775..4bc894a97f 100644 --- a/pcsx2/Gif.cpp +++ b/pcsx2/Gif.cpp @@ -28,9 +28,6 @@ using std::min; -#define gif ((DMACh*)&psH[0xA000]) -#define spr0 ((DMACh*)&PS2MEM_HW[0xD000]) - enum gifstate_t { GIF_STATE_EMPTY = 0, @@ -49,6 +46,7 @@ static int gspath3done = 0; static u32 gscycles = 0, prevcycles = 0, mfifocycles = 0; static u32 gifqwc = 0; +bool gifmfifoirq = FALSE; __forceinline void gsInterrupt() { GIF_LOG("gsInterrupt: %8.8x", cpuRegs.cycle); @@ -151,7 +149,7 @@ int _GIFchain() { return (qwc)*2; } -__forceinline void GIFchain() +static __forceinline void GIFchain() { FreezeRegs(1); if (gif->qwc) gscycles+= _GIFchain(); /* guessing */ @@ -243,14 +241,10 @@ void GIFdma() } } } - // When MTGS is enabled, Gifchain calls WRITERING_DMA, which calls GSRINGBUF_DONECOPY, which freezes - // the registers inside of the FreezeXMMRegs calls here and in the other two below.. - // I'm not really sure that is intentional. --arcum42 + GIFchain(); - // Theres a comment below that says not to unfreeze the xmm regs, so not sure about freezing and unfreezing in GIFchain. if((gif->qwc == 0) && ((gspath3done == 1) || (gif->chcr & 0xc) == 0)){ - //if(gif->qwc > 0) Console::WriteLn("Hurray!"); // We *know* it is 0! gspath3done = 0; gif->chcr &= ~0x100; GSCSRr &= ~0xC000; @@ -445,7 +439,6 @@ static __forceinline int mfifoGIFchain() { return 0; } -bool gifmfifoirq = FALSE; void mfifoGIFtransfer(int qwc) { u32 *ptag; @@ -521,12 +514,15 @@ void mfifoGIFtransfer(int qwc) { gifmfifoirq = TRUE; } } + FreezeRegs(1); + if (mfifoGIFchain() == -1) { Console::WriteLn("GIF dmaChain error size=%d, madr=%lx, tadr=%lx", params gif->qwc, gif->madr, gif->tadr); gifstate = GIF_STATE_STALL; } + FreezeRegs(0); if(gif->qwc == 0 && gifstate == GIF_STATE_DONE) gifstate = GIF_STATE_STALL; diff --git a/pcsx2/Hw.h b/pcsx2/Hw.h index 07f21049ce..97a981c82b 100644 --- a/pcsx2/Hw.h +++ b/pcsx2/Hw.h @@ -21,25 +21,16 @@ extern u8 *psH; // hw mem -#define psHs8(mem) (*(s8 *)&PS2MEM_HW[(mem) & 0xffff]) -#define psHs16(mem) (*(s16*)&PS2MEM_HW[(mem) & 0xffff]) -#define psHs32(mem) (*(s32*)&PS2MEM_HW[(mem) & 0xffff]) -#define psHs64(mem) (*(s64*)&PS2MEM_HW[(mem) & 0xffff]) -#define psHu8(mem) (*(u8 *)&PS2MEM_HW[(mem) & 0xffff]) -#define psHu16(mem) (*(u16*)&PS2MEM_HW[(mem) & 0xffff]) -#define psHu32(mem) (*(u32*)&PS2MEM_HW[(mem) & 0xffff]) -#define psHu64(mem) (*(u64*)&PS2MEM_HW[(mem) & 0xffff]) - extern void CPU_INT( u32 n, s32 ecycle ); ////////////////////////////////////////////////////////////////////////// // Hardware FIFOs (128 bit access only!) // -// VIF0 -- 0x10004000 -- psH[0x4000] -// VIF1 -- 0x10005000 -- psH[0x5000] -// GIF -- 0x10006000 -- psH[0x6000] -// IPUout -- 0x10007000 -- psH[0x7000] -// IPUin -- 0x10007010 -- psH[0x7010] +// VIF0 -- 0x10004000 -- PS2MEM_HW[0x4000] +// VIF1 -- 0x10005000 -- PS2MEM_HW[0x5000] +// GIF -- 0x10006000 -- PS2MEM_HW[0x6000] +// IPUout -- 0x10007000 -- PS2MEM_HW[0x7000] +// IPUin -- 0x10007010 -- PS2MEM_HW[0x7010] void __fastcall ReadFIFO_page_4(u32 mem, mem128_t *out); void __fastcall ReadFIFO_page_5(u32 mem, mem128_t *out); @@ -215,8 +206,8 @@ struct DMACh { #define INTC_GS 0 #define INTC_SBUS 1 -#define INTC_VBLANK_S 2 -#define INTC_VBLANK_E 3 +#define INTC_VBLANK_S 2 +#define INTC_VBLANK_E 3 #define INTC_VIF0 4 #define INTC_VIF1 5 #define INTC_VU0 6 @@ -290,21 +281,6 @@ struct DMACh { #define SISintr (0x20002000) #define MEISintr (0x40004000) -#define DMAend(dma, num) { \ - dma->chcr &= ~0x100; \ - psHu32(DMAC_STAT)|= 1<chcr &= ~0x100; + } + + return ptr; +} void hwInit(); void hwReset(); diff --git a/pcsx2/IPU/IPU.cpp b/pcsx2/IPU/IPU.cpp index 8c9ca709b9..a1b7626df5 100644 --- a/pcsx2/IPU/IPU.cpp +++ b/pcsx2/IPU/IPU.cpp @@ -48,11 +48,6 @@ using namespace std; // for min / max # define IPU_FORCEINLINE __forceinline #endif -//IPUregisters g_ipuRegsReal; - -#define ipu0dma ((DMACh *)&PS2MEM_HW[0xb000]) -#define ipu1dma ((DMACh *)&PS2MEM_HW[0xb400]) - #define IPU_DMA_GIFSTALL 1 #define IPU_DMA_TIE0 2 #define IPU_DMA_TIE1 4 diff --git a/pcsx2/Memory.h b/pcsx2/Memory.h index 1ac1e085b7..7acd4c3fb9 100644 --- a/pcsx2/Memory.h +++ b/pcsx2/Memory.h @@ -23,6 +23,7 @@ #endif //#define ENABLECACHE +#include "vtlb.h" namespace Ps2MemSize { @@ -57,9 +58,40 @@ extern u8 *psS; //0.015 mb, scratch pad extern u8 g_RealGSMem[Ps2MemSize::GSregs]; #define PS2MEM_GS g_RealGSMem +#define PS2GS_BASE(mem) (g_RealGSMem+(mem&0x13ff)) + +// Various useful locations +#define spr0 ((DMACh*)&PS2MEM_HW[0xD000]) +#define spr1 ((DMACh*)&PS2MEM_HW[0xD400]) + +#define gif ((DMACh*)&PS2MEM_HW[0xA000]) + +#define vif0ch ((DMACh*)&PS2MEM_HW[0x8000]) +#define vif1ch ((DMACh*)&PS2MEM_HW[0x9000]) + +#define sif0dma ((DMACh*)&PS2MEM_HW[0xc000]) +#define sif1dma ((DMACh*)&PS2MEM_HW[0xc400]) +#define sif2dma ((DMACh*)&PS2MEM_HW[0xc800]) + +#define ipu0dma ((DMACh *)&PS2MEM_HW[0xb000]) +#define ipu1dma ((DMACh *)&PS2MEM_HW[0xb400]) + +// From Gif.h +#define GSCSRr *((u64*)(g_RealGSMem+0x1000)) +#define GSIMR *((u32*)(g_RealGSMem+0x1010)) +#define GSSIGLBLID ((GSRegSIGBLID*)(g_RealGSMem+0x1080)) #define PSM(mem) (vtlb_GetPhyPtr((mem)&0x1fffffff)) //pcsx2 is a competition.The one with most hacks wins :D +#define psHs8(mem) (*(s8 *)&PS2MEM_HW[(mem) & 0xffff]) +#define psHs16(mem) (*(s16*)&PS2MEM_HW[(mem) & 0xffff]) +#define psHs32(mem) (*(s32*)&PS2MEM_HW[(mem) & 0xffff]) +#define psHs64(mem) (*(s64*)&PS2MEM_HW[(mem) & 0xffff]) +#define psHu8(mem) (*(u8 *)&PS2MEM_HW[(mem) & 0xffff]) +#define psHu16(mem) (*(u16*)&PS2MEM_HW[(mem) & 0xffff]) +#define psHu32(mem) (*(u32*)&PS2MEM_HW[(mem) & 0xffff]) +#define psHu64(mem) (*(u64*)&PS2MEM_HW[(mem) & 0xffff]) + #define psMs8(mem) (*(s8 *)&PS2MEM_BASE[(mem) & 0x1ffffff]) #define psMs16(mem) (*(s16*)&PS2MEM_BASE[(mem) & 0x1ffffff]) #define psMs32(mem) (*(s32*)&PS2MEM_BASE[(mem) & 0x1ffffff]) @@ -134,8 +166,6 @@ extern void memClearPageAddr(u32 vaddr); extern void memMapVUmicro(); -#include "vtlb.h" - extern int mmap_GetRamPageInfo(void* ptr); extern void mmap_MarkCountedRamPage(void* ptr,u32 vaddr); extern void mmap_ResetBlockTracking(); diff --git a/pcsx2/SPR.cpp b/pcsx2/SPR.cpp index e33fb05e79..71bfc6b948 100644 --- a/pcsx2/SPR.cpp +++ b/pcsx2/SPR.cpp @@ -23,10 +23,6 @@ #include "iR5900.h" #include "VUmicro.h" -#define spr0 ((DMACh*)&PS2MEM_HW[0xD000]) -#define spr1 ((DMACh*)&PS2MEM_HW[0xD400]) -#define gif ((DMACh*)&PS2MEM_HW[0xA000]) - extern void mfifoGIFtransfer(int); /* Both of these should be bools. Again, next savestate break. --arcum42 */ @@ -66,8 +62,10 @@ int _SPR0chain() if ((psHu32(DMAC_CTRL) & 0xC) >= 0x8) // 0x8 VIF1 MFIFO, 0xC GIF MFIFO { - if ((spr0->madr & ~psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR)) Console::WriteLn("SPR MFIFO Write outside MFIFO area"); - else mfifotransferred += spr0->qwc; + if ((spr0->madr & ~psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR)) + Console::WriteLn("SPR MFIFO Write outside MFIFO area"); + else + mfifotransferred += spr0->qwc; hwMFIFOWrite(spr0->madr, (u8*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4); spr0->madr += spr0->qwc << 4; @@ -89,9 +87,11 @@ int _SPR0chain() return (spr0->qwc) * BIAS; // bus is 1/2 the ee speed } -#define SPR0chain() \ - cycles += _SPR0chain(); \ +__forceinline void SPR0chain() +{ + _SPR0chain(); spr0->qwc = 0; +} void _SPR0interleave() @@ -99,7 +99,6 @@ void _SPR0interleave() int qwc = spr0->qwc; int sqwc = psHu32(DMAC_SQWC) & 0xff; int tqwc = (psHu32(DMAC_SQWC) >> 16) & 0xff; - //int cycles = 0; u32 *pMem; if (tqwc == 0) tqwc = qwc; @@ -124,9 +123,8 @@ void _SPR0interleave() TestClearVUs(spr0->madr, spr0->qwc << 2); memcpy_fast((u8*)pMem, &PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4); } - //cycles += tqwc * BIAS; spr0->sadr += spr0->qwc * 16; - spr0->madr += (sqwc + spr0->qwc) * 16; //qwc-= sqwc; + spr0->madr += (sqwc + spr0->qwc) * 16; } spr0->qwc = 0; @@ -143,15 +141,12 @@ static __forceinline void _dmaSPR0() // Transfer Dn_QWC from SPR to Dn_MADR if ((spr0->chcr & 0xc) == 0x0) // Normal Mode { - int cycles = 0; SPR0chain(); spr0finished = 1; - return; } else if ((spr0->chcr & 0xc) == 0x4) { - int cycles = 0; u32 *ptag; int id; bool done = FALSE; @@ -167,7 +162,6 @@ static __forceinline void _dmaSPR0() spr0->sadr += 16; // Transfer dma tag if tte is set - spr0->chcr = (spr0->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15 id = (ptag[0] >> 28) & 0x7; //ID for DmaChain copied from bit 28 of the tag @@ -201,7 +195,6 @@ static __forceinline void _dmaSPR0() { //Console::WriteLn("SPR0 TIE"); done = TRUE; - spr0->qwc = 0; } spr0finished = (done) ? 1 : 0; @@ -209,9 +202,7 @@ static __forceinline void _dmaSPR0() if (!done) { ptag = (u32*) & PS2MEM_SCRATCH[spr0->sadr & 0x3fff]; //Set memory pointer to SADR - //spr0->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag - CPU_INT(8, ((u16)ptag[0]) / BIAS); //spr0->qwc / BIAS); - spr0->qwc = 0; + CPU_INT(8, ((u16)ptag[0]) / BIAS); // the lower 16bits of the tag / BIAS); return; } SPR_LOG("spr0 dmaChain complete %8.8x_%8.8x size=%d, id=%d, addr=%lx spr=%lx", @@ -292,9 +283,11 @@ int _SPR1chain() return (spr1->qwc) * BIAS; } -#define SPR1chain() \ - cycles += _SPR1chain(); \ - spr1->qwc = 0; +__forceinline void SPR1chain() +{ + _SPR1chain(); + spr1->qwc = 0; +} void _SPR1interleave() @@ -302,7 +295,6 @@ void _SPR1interleave() int qwc = spr1->qwc; int sqwc = psHu32(DMAC_SQWC) & 0xff; int tqwc = (psHu32(DMAC_SQWC) >> 16) & 0xff; - //int cycles = 0; u32 *pMem; if (tqwc == 0) tqwc = qwc; @@ -316,8 +308,7 @@ void _SPR1interleave() pMem = (u32*)dmaGetAddr(spr1->madr); memcpy_fast(&PS2MEM_SCRATCH[spr1->sadr & 0x3fff], (u8*)pMem, spr1->qwc << 4); spr1->sadr += spr1->qwc * 16; - //cycles += spr1->qwc * BIAS; - spr1->madr += (sqwc + spr1->qwc) * 16; //qwc-= sqwc; + spr1->madr += (sqwc + spr1->qwc) * 16; } spr1->qwc = 0; @@ -328,7 +319,7 @@ void _dmaSPR1() // toSPR work function { if ((spr1->chcr & 0xc) == 0) // Normal Mode { - int cycles = 0; + //int cycles = 0; // Transfer Dn_QWC from Dn_MADR to SPR1 SPR1chain(); spr1finished = 1; @@ -336,7 +327,6 @@ void _dmaSPR1() // toSPR work function } else if ((spr1->chcr & 0xc) == 0x4) { - int cycles = 0; u32 *ptag; int id; bool done = FALSE; @@ -363,7 +353,7 @@ void _dmaSPR1() // toSPR work function spr1->chcr = (spr1->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); //Transfer upper part of tag to CHCR bits 31-15 id = (ptag[0] >> 28) & 0x7; //ID for DmaChain copied from bit 28 of the tag - spr1->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag + spr1->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag until SPR1chain is called in a few lines. spr1->madr = ptag[1]; //MADR = ADDR field // Transfer dma tag if tte is set @@ -384,7 +374,6 @@ void _dmaSPR1() // toSPR work function SPR_LOG("dmaIrq Set"); //Console::WriteLn("SPR1 TIE"); - spr1->qwc = 0; done = TRUE; } @@ -392,9 +381,7 @@ void _dmaSPR1() // toSPR work function if (!done) { ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR - //spr1->qwc = (u16)ptag[0]; //QWC set to lower 16bits of the tag - CPU_INT(9, (((u16)ptag[0]) / BIAS));// spr1->qwc / BIAS); - spr1->qwc = 0; + CPU_INT(9, (((u16)ptag[0]) / BIAS));// the lower 16 bits of the tag / BIAS); } } else // Interleave Mode @@ -411,7 +398,7 @@ void dmaSPR1() // toSPR spr1->chcr, spr1->madr, spr1->qwc, spr1->tadr, spr1->sadr); - if ((spr1->chcr & 0xc) == 0x4 && spr1->qwc == 0) + if (((spr1->chcr & 0xc) == 0x4) && (spr1->qwc == 0)) { u32 *ptag; ptag = (u32*)dmaGetAddr(spr1->tadr); //Set memory pointer to TADR diff --git a/pcsx2/Sif.cpp b/pcsx2/Sif.cpp index 796be3f9c7..23576f767f 100644 --- a/pcsx2/Sif.cpp +++ b/pcsx2/Sif.cpp @@ -25,10 +25,6 @@ using namespace std; -#define sif0dma ((DMACh*)&PS2MEM_HW[0xc000]) -#define sif1dma ((DMACh*)&PS2MEM_HW[0xc400]) -#define sif2dma ((DMACh*)&PS2MEM_HW[0xc800]) - DMACh *sif0ch; DMACh *sif1ch; DMACh *sif2ch; @@ -206,7 +202,10 @@ __forceinline void SIF0Dma() //SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr); SIF_LOG("----------- %lX of %lX", readSize << 2, size << 2); - _dmaGetAddr(sif0dma, ptag, sif0dma->madr, 5); + ptag = _dmaGetAddr(sif0dma, sif0dma->madr, 5); + if (ptag == NULL) return; + + //_dmaGetAddr(sif0dma, *ptag, sif0dma->madr, 5); SIF0read((u32*)ptag, readSize << 2); @@ -285,7 +284,12 @@ __forceinline void SIF1Dma() { // Process DMA tag at sif1dma->tadr done = FALSE; - _dmaGetAddr(sif1dma, ptag, sif1dma->tadr, 6); + ptag = _dmaGetAddr(sif1dma, sif1dma->tadr, 6); + if (ptag == NULL) return; + + //_dmaGetAddr(sif1dma, *ptag, sif1dma->tadr, 6); + + sif1dma->chcr = (sif1dma->chcr & 0xFFFF) | ((*ptag) & 0xFFFF0000); // Copy the tag sif1dma->qwc = (u16)ptag[0]; @@ -348,7 +352,10 @@ __forceinline void SIF1Dma() int qwTransfer = sif1dma->qwc; u32 *data; - _dmaGetAddr(sif1dma, data, sif1dma->madr, 6); + data = _dmaGetAddr(sif1dma, sif1dma->madr, 6); + if (data == NULL) return; + + //_dmaGetAddr(sif1dma, *data, sif1dma->madr, 6); if (qwTransfer > (FIFO_SIF1_W - sif1.fifoSize) / 4) // Copy part of sif1dma into FIFO qwTransfer = (FIFO_SIF1_W - sif1.fifoSize) / 4; diff --git a/pcsx2/Vif.cpp b/pcsx2/Vif.cpp index cb81e5f6b2..da8bd88aaf 100644 --- a/pcsx2/Vif.cpp +++ b/pcsx2/Vif.cpp @@ -427,7 +427,7 @@ void mfifoVIF1transfer(int qwc) { u32 *ptag; int id; - int ret, temp; + int ret; g_vifCycles = 0; @@ -493,12 +493,14 @@ void mfifoVIF1transfer(int qwc) break; case 2: // Next - Transfer QWC following tag. TADR = ADDR - temp = vif1ch->madr; //Temporarily Store ADDR + { + int temp = vif1ch->madr; //Temporarily Store ADDR vif1ch->madr = psHu32(DMAC_RBOR) + ((vif1ch->tadr + 16) & psHu32(DMAC_RBSR)); //Set MADR to QW following the tag vif1ch->tadr = temp; //Copy temporarily stored ADDR to Tag if ((temp & psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR)) Console::WriteLn("Next tag = %x outside ring %x size %x", params temp, psHu32(DMAC_RBOR), psHu32(DMAC_RBSR)); vif1.done = 0; break; + } case 3: // Ref - Transfer QWC from ADDR field case 4: // Refs - Transfer QWC from ADDR field (Stall Control) diff --git a/pcsx2/Vif.h b/pcsx2/Vif.h index e01cb32bd8..64335c4dde 100644 --- a/pcsx2/Vif.h +++ b/pcsx2/Vif.h @@ -171,7 +171,6 @@ static __forceinline u32 getVifColRegs(u32 reg) #define vif0Regs ((VIFregisters*)&PS2MEM_HW[0x3800]) #define vif1Regs ((VIFregisters*)&PS2MEM_HW[0x3c00]) -#define spr0 ((DMACh*)&PS2MEM_HW[0xD000]) void dmaVIF0(); void dmaVIF1(); diff --git a/pcsx2/VifDma.cpp b/pcsx2/VifDma.cpp index be2cd2e5b7..0c67d44a01 100644 --- a/pcsx2/VifDma.cpp +++ b/pcsx2/VifDma.cpp @@ -29,10 +29,6 @@ using namespace std; // for min / max - - -#define gif ((DMACh*)&PS2MEM_HW[0xA000]) - // Extern variables extern "C" { @@ -66,6 +62,9 @@ int g_vifCycles = 0; bool path3hack = FALSE; bool Path3transfer = FALSE; +u32 splittransfer[4]; +u32 splitptr = 0; + typedef void (__fastcall *UNPACKFUNCTYPE)(u32 *dest, u32 *data, int size); typedef int (*UNPACKPARTFUNCTYPESSE)(u32 *dest, u32 *data, int size); extern void (*Vif1CMDTLB[82])(); @@ -952,6 +951,8 @@ static int __fastcall Vif0TransMPG(u32 *data) // MPG static int __fastcall Vif0TransUnpack(u32 *data) // UNPACK { + int ret; + FreezeXMMRegs(1); if (vif0.vifpacketsize < vif0.tag.size) { @@ -960,35 +961,32 @@ static int __fastcall Vif0TransUnpack(u32 *data) // UNPACK ProcessMemSkip(vif0.vifpacketsize << 2, (vif0.cmd & 0xf), VIF0dmanum); - vif0.tag.size -= vif0.vifpacketsize; - FreezeXMMRegs(0); - return vif0.vifpacketsize; + ret = vif0.vifpacketsize; + vif0.tag.size -= ret; } else { /* we got all the data, transfer it fully */ - int ret = vif0.tag.size; + ret = vif0.tag.size; //Align data after a split transfer first - if(vif0Regs->offset != 0 || vif0.cl != 0) + if ((vif0Regs->offset != 0) || (vif0.cl != 0)) { vif0.tag.size = VIFalign(data, &vif0.tag, vif0.tag.size, VIF0dmanum); data += ret - vif0.tag.size; if(vif0.tag.size > 0) VIFunpack(data, &vif0.tag, vif0.tag.size, VIF0dmanum); - vif0.tag.size = 0; - vif0.cmd = 0; - FreezeXMMRegs(0); - return ret; } else { VIFunpack(data, &vif0.tag, vif0.tag.size, VIF0dmanum); - vif0.tag.size = 0; - vif0.cmd = 0; - FreezeXMMRegs(0); - return ret; } + + vif0.tag.size = 0; + vif0.cmd = 0; } + + FreezeXMMRegs(0); + return ret; } //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// @@ -1694,8 +1692,6 @@ static int __fastcall Vif1TransMPG(u32 *data) return ret; } } -u32 splittransfer[4]; -u32 splitptr = 0; static int __fastcall Vif1TransDirectHL(u32 *data) { @@ -2371,7 +2367,6 @@ __forceinline void vif1Interrupt() if (vif1Regs->mskpath3 == 0 || (vif1ch->chcr & 0x1) == 0x1)vif1Regs->stat &= ~0x1F000000; // FQC=0 } -#define spr0 ((DMACh*)&PS2MEM_HW[0xD000]) void dmaVIF1() { diff --git a/pcsx2/VifDma.h b/pcsx2/VifDma.h index 6af78214e7..7a1023a3a8 100644 --- a/pcsx2/VifDma.h +++ b/pcsx2/VifDma.h @@ -50,9 +50,6 @@ struct vifStruct { extern vifStruct vif0, vif1; extern bool Path3transfer; -#define vif0ch ((DMACh*)&PS2MEM_HW[0x8000]) -#define vif1ch ((DMACh*)&PS2MEM_HW[0x9000]) - void __fastcall UNPACK_S_32( u32 *dest, u32 *data, int size ); void __fastcall UNPACK_S_16u( u32 *dest, u32 *data, int size ); diff --git a/pcsx2/x86/iFPUd.cpp b/pcsx2/x86/iFPUd.cpp index ec7b489b76..33a9693cc3 100644 --- a/pcsx2/x86/iFPUd.cpp +++ b/pcsx2/x86/iFPUd.cpp @@ -116,7 +116,7 @@ static u64 PCSX2_ALIGNED16(dbl_ps2_overflow) = DOUBLE(0,1152,0); //overflow & cl static u64 PCSX2_ALIGNED16(dbl_underflow) = DOUBLE(0,897,0); //underflow if below static u64 PCSX2_ALIGNED16(dbl_s_pos[2]) = {0x7fffffffffffffffULL, 0}; -static u64 PCSX2_ALIGNED16(dbl_s_neg[2]) = {0x8000000000000000ULL, 0}; +//static u64 PCSX2_ALIGNED16(dbl_s_neg[2]) = {0x8000000000000000ULL, 0}; // converts small normal numbers to double equivalent // converts large normal numbers (which represent NaN/inf in IEEE) to double equivalent diff --git a/pcsx2/x86/iR3000A.cpp b/pcsx2/x86/iR3000A.cpp index 66a78c0105..9f79701e7a 100644 --- a/pcsx2/x86/iR3000A.cpp +++ b/pcsx2/x86/iR3000A.cpp @@ -837,7 +837,7 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch) x86SetJ8( j8Ptr[0] ); } -static const int *s_pCode; +//static const int *s_pCode; #if !defined(_MSC_VER) static void checkcodefn() diff --git a/pcsx2/x86/iVUzerorec.cpp b/pcsx2/x86/iVUzerorec.cpp index bebcd3cdf3..ce9549be0c 100644 --- a/pcsx2/x86/iVUzerorec.cpp +++ b/pcsx2/x86/iVUzerorec.cpp @@ -2963,8 +2963,8 @@ int VuInstruction::SetCachedRegs(int upper, u32 vuxyz) void VuInstruction::Recompile(list::iterator& itinst, u32 vuxyz) { - static PCSX2_ALIGNED16(VECTOR _VF); - static PCSX2_ALIGNED16(VECTOR _VFc); + //static PCSX2_ALIGNED16(VECTOR _VF); + //static PCSX2_ALIGNED16(VECTOR _VFc); u32 *ptr; u8* pjmp; int vfregstore=0;