mirror of https://github.com/PCSX2/pcsx2.git
--No longer uses 2 hacks/buffers, it just stores the info needed to generate the memops directly on the code
git-svn-id: http://pcsx2.googlecode.com/svn/branches/vtlb-exp@936 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
drkiiraziel
parent
6c88e99cf2
commit
f5e99af1ab
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@ -62,7 +62,7 @@ int SysPageFaultExceptionFilter( EXCEPTION_POINTERS* eps )
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if (addr&0x80000000)
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{
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uptr _vtlb_HandleRewrite(uptr code);
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uptr _vtlb_HandleRewrite(u32 info,u8* ra);
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u8* pcode=(u8*)ExceptionRecord.ExceptionAddress;
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u32 patch_point=1;
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@ -79,7 +79,7 @@ int SysPageFaultExceptionFilter( EXCEPTION_POINTERS* eps )
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eps->ContextRecord->Eax-=*(u32*)&pcode[-patch_point+2];
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uptr codeloc=_vtlb_HandleRewrite(*(u32*)&pcode[-patch_point+2]);
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uptr codeloc=_vtlb_HandleRewrite(*(u32*)&pcode[-patch_point+2],&pcode[-patch_point+2+4]);
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eps->ContextRecord->Eip=codeloc;
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*(u32*)&pcode[-patch_point+2]=codeloc-(u32)&pcode[-patch_point+6];
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@ -24,14 +24,28 @@
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#include "iCore.h"
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#include "iR5900.h"
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u8* execohax_pos=0;
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u8* execohax_start=0;
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u32 execohx_sz;
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u8* code_pos=0;
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u8* code_start=0;
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u32 code_sz;
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union _vtlb_MemOpInfo
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{
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struct
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{
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u32 sz:8;//0 -> 8, 1 -> 16, 2 -> 32, 3 -> 64, 4 -> 128
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u32 skip:8;//bytes to skip
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u32 sx:1;
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u32 read:1;
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};
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u32 full;
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bool isRead() { return read; }
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bool isWrite(){ return !isRead(); }
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bool isSX() { return sx; }
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u32 getSize() { return sz; }
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u32 getSkip() { return skip; }
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};
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using namespace vtlb_private;
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#include <windows.h>
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@ -49,8 +63,8 @@ void execuCode(bool set)
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while(i<code_sz)
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{
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//UD2 is 0xF 0xB.Fill the stream with it so that the cpu don't try to execute past branches ..
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code_start[i]=0xF;i++;
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code_start[i]=0xB;i++;
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code_start[i]=0xF;i++;
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}
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}
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@ -63,67 +77,33 @@ void execuCode(bool set)
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else
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{
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code_pos=x86SetPtr(old);
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u32 tt=execohx_sz-2*1024*1024+(execohax_pos-execohax_start);
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u32 tc=code_sz-free;
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SysPrintf("%d code, %d pot, %.2f%%\n",tc,tt,tc/(float)tt*100);
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}
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}
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u32* execohaxme(bool set)
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u8* IndirectPlaceholderA()
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{
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u32 used=execohax_pos-execohax_start;
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u32 free=2*1024*1024-used;
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write8<_EmitterId_>( 0x81 );
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ModRM<_EmitterId_>( 3, 0, EAX );
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if (execohax_pos == 0 || free<128)
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{
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SysPrintf("Leaking 2 megabytes of ram\n");
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execohax_start=execohax_pos=(u8*)VirtualAlloc(0,2*1024*1024,MEM_COMMIT,PAGE_EXECUTE_READWRITE);
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execohx_sz+=2*1024*1024;
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}
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static u8* saved;
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static u8* mod;
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if (set)
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{
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write8<_EmitterId_>( 0x81 );
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ModRM<_EmitterId_>( 3, 0, EAX );
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write32<_EmitterId_>( (uptr)execohax_pos );
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u8* rv=x86SetPtr(0);
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write32<_EmitterId_>(0);
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saved=x86SetPtr(execohax_pos);
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mod=execohax_pos;
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write8<_EmitterId_>(0); //size, in bytes
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write32<_EmitterId_>(0); //return address
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}
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else
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{
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//x86AlignExecutable(4);
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//x86Align(64);
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execohax_pos=x86SetPtr(mod);
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write8<_EmitterId_>(execohax_pos-mod-5);
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return (u32*)x86SetPtr(saved);
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}
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return 0;
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}
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uptr _vtlb_HandleRewrite(uptr block)
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{
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u8 size=*(u8*)block;
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u32 ra=*(u32*)(block+1);
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u8* pcode=(u8*)(block+5);
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execuCode(true);
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uptr rv=(uptr)code_pos;
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while(size--)
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{
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write8<_EmitterId_>(*pcode++);
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}
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JMP32(ra-(uptr)x86Ptr[_EmitterId_]-5);
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execuCode(false);
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//do magic
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return rv;
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}
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void IndirectPlaceholderB(u8* pl,bool read,u32 sz,bool sx)
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{
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_vtlb_MemOpInfo inf;
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inf.full=0;
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inf.read=read;
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inf.sz=sz;
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inf.sx=sx;
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u8* old=x86SetPtr(pl);
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inf.skip=old-pl-4;
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//Add32 <eax>,imm, 6 bytes form.
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write32<_EmitterId_>( inf.full );
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x86SetPtr(old);
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}
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PCSX2_ALIGNED16( static u64 g_globalXMMData[2*XMMREGS] );
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void MOVx_SSE( x86IntRegType destRm, x86IntRegType srcRm,u32 srcAddr=0,u32 dstAddr=0,bool half=false )
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{
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@ -196,6 +176,8 @@ void MOV64_MMX( x86IntRegType destRm, x86IntRegType srcRm,u32 srcAddr=0,u32 dstA
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MOVx_SSE(destRm,srcRm,srcAddr,dstAddr,true);
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}
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}
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/*
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// Pseudo-Code For the following Dynarec Implementations -->
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@ -317,16 +299,12 @@ void vtlb_DynGenRead64(u32 bits)
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SHR32ItoR(EAX,VTLB_PAGE_BITS);
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MOV32RmSOffsettoR(EAX,EAX,(int)vtlbdata.vmap,2);
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ADD32RtoR(ECX,EAX);
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//u8* _direct = JMP8(0);
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execohaxme(true);
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_vtlb_DynGen_IndirectRead( bits );
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u32* patch=execohaxme(false);
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u8* patch=IndirectPlaceholderA();
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_vtlb_DynGen_DirectRead( bits, false );
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*patch=(uptr)x86Ptr[_EmitterId_];
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IndirectPlaceholderB(patch,true,bits,false);
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}
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// Recompiled input registers:
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@ -340,33 +318,12 @@ void vtlb_DynGenRead32(u32 bits, bool sign)
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SHR32ItoR(EAX,VTLB_PAGE_BITS);
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MOV32RmSOffsettoR(EAX,EAX,(int)vtlbdata.vmap,2);
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ADD32RtoR(ECX,EAX);
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//u8* _direct = JMP8(0);
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execohaxme(true);
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_vtlb_DynGen_IndirectRead( bits );
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// perform sign extension on the result:
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if( bits==8 )
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{
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if( sign )
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MOVSX32R8toR(EAX,EAX);
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else
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MOVZX32R8toR(EAX,EAX);
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}
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else if( bits==16 )
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{
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if( sign )
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MOVSX32R16toR(EAX,EAX);
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else
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MOVZX32R16toR(EAX,EAX);
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}
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u32* patch=execohaxme(false);
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u8* patch=IndirectPlaceholderA();
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_vtlb_DynGen_DirectRead( bits, sign );
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*patch=(uptr)x86Ptr[_EmitterId_];
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IndirectPlaceholderB(patch,true,bits,sign);
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}
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//
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@ -543,16 +500,11 @@ void vtlb_DynGenWrite(u32 sz)
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MOV32RmSOffsettoR(EAX,EAX,(int)vtlbdata.vmap,2);
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ADD32RtoR(ECX,EAX);
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//u8* _direct=JMP8(0);
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u8* patch=IndirectPlaceholderA();
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execohaxme(true);
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_vtlb_DynGen_IndirectWrite( sz );
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u32* patch=execohaxme(false);
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_vtlb_DynGen_DirectWrite( sz );
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*patch=(uptr)x86Ptr[_EmitterId_];
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IndirectPlaceholderB(patch,false,sz,false);
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}
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@ -608,3 +560,52 @@ void vtlb_DynGenWrite_Const( u32 bits, u32 addr_const )
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CALLFunc( (int)vtlbdata.RWFT[szidx][1][handler] );
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}
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}
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u32 GenIndirectMemOp(u32 info)
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{
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_vtlb_MemOpInfo inf;
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inf.full=info;
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u32 bits=inf.getSize();
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bool sign=inf.isSX();
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if (inf.isWrite())
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{
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_vtlb_DynGen_IndirectWrite(bits);
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}
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else
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{
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_vtlb_DynGen_IndirectRead(bits);
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if( bits==8 )
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{
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if( sign )
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MOVSX32R8toR(EAX,EAX);
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else
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MOVZX32R8toR(EAX,EAX);
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}
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else if( bits==16 )
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{
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if( sign )
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MOVSX32R16toR(EAX,EAX);
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else
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MOVZX32R16toR(EAX,EAX);
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}
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}
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return inf.getSkip();
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}
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uptr _vtlb_HandleRewrite(u32 info,u8* ra)
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{
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execuCode(true);
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uptr rv=(uptr)x86SetPtr(0);
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u32 skip=GenIndirectMemOp(info);
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JMP32(ra-x86Ptr[_EmitterId_]-5+skip);
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execuCode(false);
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return rv;
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}
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