mirror of https://github.com/PCSX2/pcsx2.git
core: convert xCALL to xFastCall
SuperVU wasn't converted (unlikely to be ported to 64 bits) A couple of calls weren't converted because they require extra work but there are not mandatory (debug/MTVU/...)
This commit is contained in:
Gregory Hainaut
parent
859d62d2a7
commit
e3d5eb5a4e
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@ -112,7 +112,7 @@ void recDI()
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//xMOV(eax, ptr[&cpuRegs.cycle ]);
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//xMOV(ptr[&g_nextBranchCycle], eax);
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//xCALL((void*)(uptr)Interp::DI );
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//xFastCall((void*)(uptr)Interp::DI );
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xMOV(eax, ptr[&cpuRegs.CP0.n.Status]);
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xTEST(eax, 0x20006); // EXL | ERL | EDI
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@ -170,12 +170,12 @@ void recMFC0()
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case 1:
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iFlushCall(FLUSH_INTERPRETER);
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xCALL( COP0_UpdatePCCR );
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xFastCall(COP0_UpdatePCCR );
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xMOV(eax, ptr[&cpuRegs.PERF.n.pcr0]);
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break;
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case 3:
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iFlushCall(FLUSH_INTERPRETER);
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xCALL( COP0_UpdatePCCR );
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xFastCall(COP0_UpdatePCCR );
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xMOV(eax, ptr[&cpuRegs.PERF.n.pcr1]);
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break;
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}
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@ -207,8 +207,7 @@ void recMTC0()
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{
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case 12:
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iFlushCall(FLUSH_INTERPRETER);
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xMOV( ecx, g_cpuConstRegs[_Rt_].UL[0] );
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xCALL( WriteCP0Status );
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xFastCall(WriteCP0Status, g_cpuConstRegs[_Rt_].UL[0] );
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break;
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case 9:
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@ -222,9 +221,9 @@ void recMTC0()
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{
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case 0:
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iFlushCall(FLUSH_INTERPRETER);
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xCALL( COP0_UpdatePCCR );
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xFastCall(COP0_UpdatePCCR );
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xMOV( ptr32[&cpuRegs.PERF.n.pccr], g_cpuConstRegs[_Rt_].UL[0] );
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xCALL( COP0_DiagnosticPCCR );
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xFastCall(COP0_DiagnosticPCCR );
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break;
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case 1:
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@ -257,7 +256,7 @@ void recMTC0()
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case 12:
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iFlushCall(FLUSH_INTERPRETER);
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_eeMoveGPRtoR(ecx, _Rt_);
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xCALL( WriteCP0Status );
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xFastCall(WriteCP0Status, ecx );
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break;
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case 9:
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@ -271,9 +270,9 @@ void recMTC0()
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{
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case 0:
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iFlushCall(FLUSH_INTERPRETER);
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xCALL( COP0_UpdatePCCR );
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xFastCall(COP0_UpdatePCCR );
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_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_);
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xCALL( COP0_DiagnosticPCCR );
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xFastCall(COP0_DiagnosticPCCR );
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break;
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case 1:
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@ -92,7 +92,7 @@ static const __aligned16 u32 s_pos[4] = { 0x7fffffff, 0xffffffff, 0xffffffff, 0x
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void f(); \
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void rec##f() { \
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iFlushCall(FLUSH_INTERPRETER); \
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xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \
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xFastCall((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \
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branch = 2; \
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}
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@ -100,7 +100,7 @@ static const __aligned16 u32 s_pos[4] = { 0x7fffffff, 0xffffffff, 0xffffffff, 0x
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void f(); \
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void rec##f() { \
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iFlushCall(FLUSH_INTERPRETER); \
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xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \
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xFastCall((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \
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}
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//------------------------------------------------------------------
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@ -550,7 +550,7 @@ void FPU_MUL(int regd, int regt, bool reverseOperands)
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{
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xMOVD(ecx, xRegisterSSE(reverseOperands ? regt : regd));
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xMOVD(edx, xRegisterSSE(reverseOperands ? regd : regt));
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xCALL((void*)(uptr)&FPU_MUL_HACK ); //returns the hacked result or 0
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xFastCall((void*)(uptr)&FPU_MUL_HACK, ecx, edx); //returns the hacked result or 0
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xTEST(eax, eax);
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noHack = JZ8(0);
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xMOVDZX(xRegisterSSE(regd), eax);
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@ -89,20 +89,6 @@ namespace DOUBLE {
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#define FPUflagSO 0X00000010
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#define FPUflagSU 0X00000008
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#define REC_FPUBRANCH(f) \
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void f(); \
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void rec##f() { \
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iFlushCall(FLUSH_INTERPRETER); \
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xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \
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branch = 2; \
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}
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#define REC_FPUFUNC(f) \
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void f(); \
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void rec##f() { \
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iFlushCall(FLUSH_INTERPRETER); \
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xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \
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}
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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@ -416,7 +402,7 @@ void FPU_MUL(int info, int regd, int sreg, int treg, bool acc)
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{
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xMOVD(ecx, xRegisterSSE(sreg));
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xMOVD(edx, xRegisterSSE(treg));
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xCALL((void*)(uptr)&FPU_MUL_HACK ); //returns the hacked result or 0
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xFastCall((void*)(uptr)&FPU_MUL_HACK, ecx, edx); //returns the hacked result or 0
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xTEST(eax, eax);
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noHack = JZ8(0);
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xMOVDZX(xRegisterSSE(regd), eax);
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@ -185,7 +185,7 @@ void recPMFHL()
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// fall to interp
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_deleteEEreg(_Rd_, 0);
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iFlushCall(FLUSH_INTERPRETER); // since calling CALLFunc
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xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::MMI::PMFHL );
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xFastCall((void*)(uptr)R5900::Interpreter::OpcodeImpl::MMI::PMFHL );
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break;
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case 0x03: // LH
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@ -128,8 +128,7 @@ static DynGenFunc* _DynGen_JITCompile()
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u8* retval = xGetPtr();
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xMOV( ecx, ptr[&psxRegs.pc] );
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xCALL( iopRecRecompile );
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xFastCall(iopRecRecompile, ptr[&psxRegs.pc] );
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xMOV( eax, ptr[&psxRegs.pc] );
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xMOV( ebx, eax );
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@ -199,7 +198,7 @@ static void _DynGen_Dispatchers()
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// Place the EventTest and DispatcherReg stuff at the top, because they get called the
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// most and stand to benefit from strong alignment and direct referencing.
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iopDispatcherEvent = (DynGenFunc*)xGetPtr();
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xCALL( recEventTest );
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xFastCall(recEventTest );
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iopDispatcherReg = _DynGen_DispatcherReg();
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iopJITCompile = _DynGen_JITCompile();
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@ -523,11 +522,11 @@ void psxRecompileCodeConst1(R3000AFNPTR constcode, R3000AFNPTR_INFO noconstcode)
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}
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if (debug)
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xCALL(debug);
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xFastCall(debug);
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#endif
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irxHLE hle = irxImportHLE(libname, index);
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if (hle) {
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xCALL(hle);
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xFastCall(hle);
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xCMP(eax, 0);
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xJNE(iopDispatcherReg);
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}
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@ -907,7 +906,7 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch)
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xSUB(ptr32[&iopCycleEE], eax);
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xJLE(iopExitRecompiledCode);
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xCALL(iopEventTest);
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xFastCall(iopEventTest);
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if( newpc != 0xffffffff )
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{
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@ -929,7 +928,7 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch)
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xSUB(eax, ptr32[&g_iopNextEventCycle]);
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xForwardJS<u8> nointerruptpending;
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xCALL(iopEventTest);
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xFastCall(iopEventTest);
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if( newpc != 0xffffffff ) {
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xCMP(ptr32[&psxRegs.pc], newpc);
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@ -964,9 +963,9 @@ void rpsxSYSCALL()
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xMOV(ptr32[&psxRegs.pc], psxpc - 4);
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_psxFlushCall(FLUSH_NODESTROY);
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xMOV( ecx, 0x20 ); // exception code
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xMOV( edx, psxbranch==1 ); // branch delay slot?
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xCALL( psxException );
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//xMOV( ecx, 0x20 ); // exception code
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//xMOV( edx, psxbranch==1 ); // branch delay slot?
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xFastCall(psxException, 0x20, psxbranch == 1 );
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xCMP(ptr32[&psxRegs.pc], psxpc-4);
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j8Ptr[0] = JE8(0);
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@ -987,9 +986,9 @@ void rpsxBREAK()
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xMOV(ptr32[&psxRegs.pc], psxpc - 4);
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_psxFlushCall(FLUSH_NODESTROY);
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xMOV( ecx, 0x24 ); // exception code
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xMOV( edx, psxbranch==1 ); // branch delay slot?
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xCALL( psxException );
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//xMOV( ecx, 0x24 ); // exception code
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//xMOV( edx, psxbranch==1 ); // branch delay slot?
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xFastCall(psxException, 0x24, psxbranch == 1 );
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xCMP(ptr32[&psxRegs.pc], psxpc-4);
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j8Ptr[0] = JE8(0);
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@ -1102,8 +1101,7 @@ static void __fastcall iopRecRecompile( const u32 startpc )
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if( IsDebugBuild )
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{
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xMOV(ecx, psxpc);
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xCALL(PreBlockCheck);
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xFastCall(PreBlockCheck, psxpc);
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}
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// go until the next branch
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@ -32,7 +32,7 @@ extern u32 g_psxMaxRecMem;
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static void rpsx##f() { \
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xMOV(ptr32[&psxRegs.code], (u32)psxRegs.code); \
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_psxFlushCall(FLUSH_EVERYTHING); \
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xCALL((void*)(uptr)psx##f); \
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xFastCall((void*)(uptr)psx##f); \
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PSX_DEL_CONST(_Rt_); \
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/* branch = 2; */\
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}
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@ -626,7 +626,7 @@ static void rpsxLB()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xCALL( iopMemRead8 ); // returns value in EAX
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xFastCall(iopMemRead8, ecx ); // returns value in EAX
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if (_Rt_) {
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xMOVSX(eax, al);
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xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
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@ -642,7 +642,7 @@ static void rpsxLBU()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xCALL( iopMemRead8 ); // returns value in EAX
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xFastCall(iopMemRead8, ecx ); // returns value in EAX
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if (_Rt_) {
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xMOVZX(eax, al);
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xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
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@ -658,7 +658,7 @@ static void rpsxLH()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xCALL( iopMemRead16 ); // returns value in EAX
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xFastCall(iopMemRead16, ecx ); // returns value in EAX
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if (_Rt_) {
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xMOVSX(eax, ax);
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xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
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@ -674,7 +674,7 @@ static void rpsxLHU()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xCALL( iopMemRead16 ); // returns value in EAX
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xFastCall(iopMemRead16, ecx ); // returns value in EAX
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if (_Rt_) {
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xMOVZX(eax, ax);
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xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
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@ -695,7 +695,7 @@ static void rpsxLW()
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xTEST(ecx, 0x10000000);
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j8Ptr[0] = JZ8(0);
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xCALL( iopMemRead32 ); // returns value in EAX
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xFastCall(iopMemRead32, ecx ); // returns value in EAX
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if (_Rt_) {
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xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
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}
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@ -721,7 +721,7 @@ static void rpsxSB()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] );
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xCALL( iopMemWrite8 );
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xFastCall(iopMemWrite8, ecx, edx );
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}
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static void rpsxSH()
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@ -732,7 +732,7 @@ static void rpsxSH()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] );
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xCALL( iopMemWrite16 );
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xFastCall(iopMemWrite16, ecx, edx );
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}
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static void rpsxSW()
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@ -743,7 +743,7 @@ static void rpsxSW()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] );
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xCALL( iopMemWrite32 );
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xFastCall(iopMemWrite32, ecx, edx );
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}
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//// SLL
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@ -1371,7 +1371,7 @@ void rpsxRFE()
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// Test the IOP's INTC status, so that any pending ints get raised.
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_psxFlushCall(0);
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xCALL((void*)(uptr)&iopTestIntc );
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xFastCall((void*)(uptr)&iopTestIntc );
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}
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// R3000A tables
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@ -71,7 +71,7 @@ namespace OpcodeImpl {
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// xMOV(ptr32[&cpuRegs.code], cpuRegs.code );
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// xMOV(ptr32[&cpuRegs.pc], pc );
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// iFlushCall(FLUSH_EVERYTHING);
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// xCALL((void*)(uptr)CACHE );
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// xFastCall((void*)(uptr)CACHE );
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// //branch = 2;
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//
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// xCMP(ptr32[(u32*)((int)&cpuRegs.pc)], pc);
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@ -203,7 +203,7 @@ void recMTSAH()
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//xMOV(ptr32[&cpuRegs.code], (u32)cpuRegs.code );
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//xMOV(ptr32[&cpuRegs.pc], (u32)pc );
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//iFlushCall(FLUSH_EVERYTHING);
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//xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::CACHE );
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//xFastCall((void*)(uptr)R5900::Interpreter::OpcodeImpl::CACHE );
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//branch = 2;
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}
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@ -340,7 +340,7 @@ void recBranchCall( void (*func)() )
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void recCall( void (*func)() )
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{
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iFlushCall(FLUSH_INTERPRETER);
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xCALL(func);
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xFastCall(func);
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}
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// =====================================================================================================
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@ -380,8 +380,7 @@ static DynGenFunc* _DynGen_JITCompile()
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u8* retval = xGetAlignedCallTarget();
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xMOV( ecx, ptr[&cpuRegs.pc] );
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xCALL( recRecompile );
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xFastCall(recRecompile, ptr[&cpuRegs.pc] );
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xMOV( eax, ptr[&cpuRegs.pc] );
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xMOV( ebx, eax );
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@ -417,7 +416,7 @@ static DynGenFunc* _DynGen_DispatcherEvent()
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{
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u8* retval = xGetPtr();
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xCALL( recEventTest );
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xFastCall(recEventTest );
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return (DynGenFunc*)retval;
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}
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@ -446,7 +445,7 @@ static DynGenFunc* _DynGen_DispatchBlockDiscard()
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{
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u8* retval = xGetPtr();
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xEMMS();
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xCALL(dyna_block_discard);
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xFastCall(dyna_block_discard);
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xJMP(ExitRecompiledCode);
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return (DynGenFunc*)retval;
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}
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@ -455,7 +454,7 @@ static DynGenFunc* _DynGen_DispatchPageReset()
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{
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u8* retval = xGetPtr();
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xEMMS();
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xCALL(dyna_page_reset);
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xFastCall(dyna_page_reset);
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xJMP(ExitRecompiledCode);
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return (DynGenFunc*)retval;
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}
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@ -916,7 +915,7 @@ void SetBranchReg( u32 reg )
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// xCMP(ptr32[&cpuRegs.pc], 0);
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// j8Ptr[5] = JNE8(0);
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// xCALL((void*)(uptr)tempfn);
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// xFastCall((void*)(uptr)tempfn);
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// x86SetJ8( j8Ptr[5] );
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iFlushCall(FLUSH_EVERYTHING);
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@ -1201,11 +1200,11 @@ void recMemcheck(u32 op, u32 bits, bool store)
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if (bits == 128)
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xAND(ecx, ~0x0F);
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xCALL(standardizeBreakpointAddress);
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xFastCall(standardizeBreakpointAddress, ecx);
|
||||
xMOV(ecx,eax);
|
||||
xMOV(edx,eax);
|
||||
xADD(edx,bits/8);
|
||||
|
||||
|
||||
// ecx = access address
|
||||
// edx = access address+size
|
||||
|
||||
|
|
@ -1220,11 +1219,11 @@ void recMemcheck(u32 op, u32 bits, bool store)
|
|||
continue;
|
||||
|
||||
// logic: memAddress < bpEnd && bpStart < memAddress+memSize
|
||||
|
||||
|
||||
xMOV(eax,standardizeBreakpointAddress(checks[i].end));
|
||||
xCMP(ecx,eax); // address < end
|
||||
xForwardJGE8 next1; // if address >= end then goto next1
|
||||
|
||||
|
||||
xMOV(eax,standardizeBreakpointAddress(checks[i].start));
|
||||
xCMP(eax,edx); // start < address+size
|
||||
xForwardJGE8 next2; // if start >= address+size then goto next2
|
||||
|
|
@ -1232,10 +1231,10 @@ void recMemcheck(u32 op, u32 bits, bool store)
|
|||
// hit the breakpoint
|
||||
if (checks[i].result & MEMCHECK_LOG) {
|
||||
xMOV(edx, store);
|
||||
xCALL(&dynarecMemLogcheck);
|
||||
xFastCall(dynarecMemLogcheck, ecx, edx);
|
||||
}
|
||||
if (checks[i].result & MEMCHECK_BREAK) {
|
||||
xCALL(&dynarecMemcheck);
|
||||
xFastCall(dynarecMemcheck);
|
||||
}
|
||||
|
||||
next1.SetTarget();
|
||||
|
|
@ -1248,7 +1247,7 @@ void encodeBreakpoint()
|
|||
if (isBreakpointNeeded(pc) != 0)
|
||||
{
|
||||
iFlushCall(FLUSH_EVERYTHING|FLUSH_PC);
|
||||
xCALL(&dynarecCheckBreakpoint);
|
||||
xFastCall(dynarecCheckBreakpoint);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1297,7 +1296,7 @@ void recompileNextInstruction(int delayslot)
|
|||
|
||||
s_pCode = (int *)PSM( pc );
|
||||
pxAssert(s_pCode);
|
||||
|
||||
|
||||
if( IsDebugBuild )
|
||||
xMOV(eax, pc); // acts as a tag for delimiting recompiled instructions when viewing x86 disasm.
|
||||
|
||||
|
|
@ -1660,7 +1659,7 @@ static void __fastcall recRecompile( const u32 startpc )
|
|||
|
||||
if (0x8000d618 == startpc)
|
||||
DbgCon.WriteLn("Compiling block @ 0x%08x", startpc);
|
||||
|
||||
|
||||
s_pCurBlock = PC_GETBLOCK(startpc);
|
||||
|
||||
pxAssert(s_pCurBlock->GetFnptr() == (uptr)JITCompile
|
||||
|
|
@ -1674,14 +1673,14 @@ static void __fastcall recRecompile( const u32 startpc )
|
|||
pxAssert(s_pCurBlockEx);
|
||||
|
||||
if (g_SkipBiosHack && HWADDR(startpc) == EELOAD_START) {
|
||||
xCALL(eeloadReplaceOSDSYS);
|
||||
xFastCall(eeloadReplaceOSDSYS);
|
||||
xCMP(ptr32[&cpuRegs.pc], startpc);
|
||||
xJNE(DispatcherReg);
|
||||
}
|
||||
|
||||
// this is the only way patches get applied, doesn't depend on a hack
|
||||
if (HWADDR(startpc) == ElfEntry) {
|
||||
xCALL(eeGameStarting);
|
||||
xFastCall(eeGameStarting);
|
||||
// Apply patch as soon as possible. Normally it is done in
|
||||
// eeGameStarting but first block is already compiled.
|
||||
//
|
||||
|
|
@ -1711,20 +1710,18 @@ static void __fastcall recRecompile( const u32 startpc )
|
|||
// [TODO] : These must be enabled from the GUI or INI to be used, otherwise the
|
||||
// code that calls PreBlockCheck will not be generated.
|
||||
|
||||
xMOV(ecx, pc);
|
||||
xCALL(PreBlockCheck);
|
||||
xFastCall(PreBlockCheck, pc);
|
||||
}
|
||||
|
||||
if (EmuConfig.Gamefixes.GoemonTlbHack) {
|
||||
if (pc == 0x33ad48 || pc == 0x35060c) {
|
||||
// 0x33ad48 and 0x35060c are the return address of the function (0x356250) that populate the TLB cache
|
||||
xCALL(GoemonPreloadTlb);
|
||||
xFastCall(GoemonPreloadTlb);
|
||||
} else if (pc == 0x3563b8) {
|
||||
// Game will unmap some virtual addresses. If a constant address were hardcoded in the block, we would be in a bad situation.
|
||||
AtomicExchange( eeRecNeedsReset, true );
|
||||
// 0x3563b8 is the start address of the function that invalidate entry in TLB cache
|
||||
xMOV(ecx, ptr[&cpuRegs.GPR.n.a0.UL[ 0 ] ]);
|
||||
xCALL(GoemonUnloadTlb);
|
||||
xFastCall(GoemonUnloadTlb, ptr[&cpuRegs.GPR.n.a0.UL[0]]);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1745,7 +1742,7 @@ static void __fastcall recRecompile( const u32 startpc )
|
|||
|
||||
while(1) {
|
||||
BASEBLOCK* pblock = PC_GETBLOCK(i);
|
||||
|
||||
|
||||
// stop before breakpoints
|
||||
if (isBreakpointNeeded(i) != 0 || isMemcheckNeeded(i) != 0)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -396,7 +396,7 @@ EERECOMPILE_CODE0(BNEL, XMMINFO_READS|XMMINFO_READT);
|
|||
// xMOV(ptr32[(u32*)((int)&cpuRegs.code)], cpuRegs.code );
|
||||
// xMOV(ptr32[(u32*)((int)&cpuRegs.pc)], pc );
|
||||
// iFlushCall(FLUSH_EVERYTHING);
|
||||
// xCALL((void*)(int)BLTZAL );
|
||||
// xFastCall((void*)(int)BLTZAL );
|
||||
// branch = 2;
|
||||
//}
|
||||
|
||||
|
|
|
|||
|
|
@ -310,7 +310,7 @@ void vtlb_dynarec_init()
|
|||
|
||||
// jump to the indirect handler, which is a __fastcall C++ function.
|
||||
// [ecx is address, edx is data]
|
||||
xCALL( ptr32[(eax*4) + vtlbdata.RWFT[bits][mode]] );
|
||||
xFastCall(ptr32[(eax*4) + vtlbdata.RWFT[bits][mode]], ecx, edx);
|
||||
|
||||
if (!mode)
|
||||
{
|
||||
|
|
@ -406,8 +406,7 @@ void vtlb_DynGenRead64_Const( u32 bits, u32 addr_const )
|
|||
}
|
||||
|
||||
iFlushCall(FLUSH_FULLVTLB);
|
||||
xMOV( ecx, paddr );
|
||||
xCALL( vtlbdata.RWFT[szidx][0][handler] );
|
||||
xFastCall( vtlbdata.RWFT[szidx][0][handler], paddr );
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -470,8 +469,7 @@ void vtlb_DynGenRead32_Const( u32 bits, bool sign, u32 addr_const )
|
|||
else
|
||||
{
|
||||
iFlushCall(FLUSH_FULLVTLB);
|
||||
xMOV( ecx, paddr );
|
||||
xCALL( vtlbdata.RWFT[szidx][0][handler] );
|
||||
xFastCall( vtlbdata.RWFT[szidx][0][handler], paddr );
|
||||
|
||||
// perform sign extension on the result:
|
||||
|
||||
|
|
@ -561,8 +559,7 @@ void vtlb_DynGenWrite_Const( u32 bits, u32 addr_const )
|
|||
}
|
||||
|
||||
iFlushCall(FLUSH_FULLVTLB);
|
||||
xMOV( ecx, paddr );
|
||||
xCALL( vtlbdata.RWFT[szidx][1][handler] );
|
||||
xFastCall( vtlbdata.RWFT[szidx][1][handler], paddr, edx );
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -57,8 +57,8 @@ void mVUDTendProgram(mV, microFlagCycles* mFC, int isEbit) {
|
|||
mVU_XGKICK_DELAY(mVU);
|
||||
}
|
||||
if (doEarlyExit(mVU)) {
|
||||
if (!isVU1) xCALL(mVU0clearlpStateJIT);
|
||||
else xCALL(mVU1clearlpStateJIT);
|
||||
if (!isVU1) xFastCall(mVU0clearlpStateJIT);
|
||||
else xFastCall(mVU1clearlpStateJIT);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -117,9 +117,9 @@ void mVUendProgram(mV, microFlagCycles* mFC, int isEbit) {
|
|||
}
|
||||
if (doEarlyExit(mVU)) {
|
||||
if (!isVU1)
|
||||
xCALL(mVU0clearlpStateJIT);
|
||||
xFastCall(mVU0clearlpStateJIT);
|
||||
else
|
||||
xCALL(mVU1clearlpStateJIT);
|
||||
xFastCall(mVU1clearlpStateJIT);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -192,8 +192,8 @@ void normJumpCompile(mV, microFlagCycles& mFC, bool isEvilJump) {
|
|||
xJMP(mVU.exitFunct);
|
||||
}
|
||||
|
||||
if (!mVU.index) xCALL(mVUcompileJIT<0>); //(u32 startPC, uptr pState)
|
||||
else xCALL(mVUcompileJIT<1>);
|
||||
if (!mVU.index) xFastCall(mVUcompileJIT<0>, gprT2, gprT3); //(u32 startPC, uptr pState)
|
||||
else xFastCall(mVUcompileJIT<1>, gprT2, gprT3);
|
||||
|
||||
mVUrestoreRegs(mVU);
|
||||
xJMP(gprT1); // Jump to rec-code address
|
||||
|
|
|
|||
|
|
@ -194,10 +194,8 @@ __fi void handleBadOp(mV, int count) {
|
|||
#ifdef PCSX2_DEVBUILD
|
||||
if (mVUinfo.isBadOp) {
|
||||
mVUbackupRegs(mVU, true);
|
||||
xMOV(gprT2, mVU.prog.cur->idx);
|
||||
xMOV(gprT3, xPC);
|
||||
if (!isVU1) xCALL(mVUbadOp0);
|
||||
else xCALL(mVUbadOp1);
|
||||
if (!isVU1) xFastCall(mVUbadOp0, mVU.prog.cur->idx, xPC);
|
||||
else xFastCall(mVUbadOp1, mVU.prog.cur->idx, xPC);
|
||||
mVUrestoreRegs(mVU, true);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -345,9 +343,8 @@ void mVUsetCycles(mV) {
|
|||
void mVUdebugPrintBlocks(microVU& mVU, bool isEndPC) {
|
||||
if (mVUdebugNow) {
|
||||
mVUbackupRegs(mVU, true);
|
||||
xMOV(gprT2, xPC);
|
||||
if (isEndPC) xCALL(mVUprintPC2);
|
||||
else xCALL(mVUprintPC1);
|
||||
if (isEndPC) xFastCall(mVUprintPC2, xPC);
|
||||
else xFastCall(mVUprintPC1, xPC);
|
||||
mVUrestoreRegs(mVU, true);
|
||||
}
|
||||
}
|
||||
|
|
@ -375,9 +372,7 @@ void mVUtestCycles(microVU& mVU) {
|
|||
// TEST32ItoM((uptr)&mVU.regs().flags, VUFLAG_MFLAGSET);
|
||||
// xFowardJZ32 vu0jmp;
|
||||
// mVUbackupRegs(mVU, true);
|
||||
// xMOV(gprT2, mVU.prog.cur->idx);
|
||||
// xMOV(gprT3, xPC);
|
||||
// xCALL(mVUwarning0); // VU0 is allowed early exit for COP2 Interlock Simulation
|
||||
// xFastCall(mVUwarning0, mVU.prog.cur->idx, xPC); // VU0 is allowed early exit for COP2 Interlock Simulation
|
||||
// mVUrestoreRegs(mVU, true);
|
||||
mVUsavePipelineState(mVU);
|
||||
mVUendProgram(mVU, NULL, 0);
|
||||
|
|
@ -385,9 +380,7 @@ void mVUtestCycles(microVU& mVU) {
|
|||
}
|
||||
else {
|
||||
mVUbackupRegs(mVU, true);
|
||||
xMOV(gprT2, mVU.prog.cur->idx);
|
||||
xMOV(gprT3, xPC);
|
||||
xCALL(mVUwarning1);
|
||||
xFastCall(mVUwarning1, mVU.prog.cur->idx, xPC);
|
||||
mVUrestoreRegs(mVU, true);
|
||||
mVUsavePipelineState(mVU);
|
||||
mVUendProgram(mVU, NULL, 0);
|
||||
|
|
|
|||
|
|
@ -27,8 +27,8 @@ void mVUdispatcherAB(mV) {
|
|||
xScopedStackFrame frame(false, true);
|
||||
|
||||
// __fastcall = The caller has already put the needed parameters in ecx/edx:
|
||||
if (!isVU1) { xCALL(mVUexecuteVU0); }
|
||||
else { xCALL(mVUexecuteVU1); }
|
||||
if (!isVU1) { xFastCall(mVUexecuteVU0, ecx, edx); }
|
||||
else { xFastCall(mVUexecuteVU1, ecx, edx); }
|
||||
|
||||
// Load VU's MXCSR state
|
||||
xLDMXCSR(g_sseVUMXCSR);
|
||||
|
|
@ -61,8 +61,8 @@ void mVUdispatcherAB(mV) {
|
|||
|
||||
// __fastcall = The first two DWORD or smaller arguments are passed in ECX and EDX registers;
|
||||
// all other arguments are passed right to left.
|
||||
if (!isVU1) { xCALL(mVUcleanUpVU0); }
|
||||
else { xCALL(mVUcleanUpVU1); }
|
||||
if (!isVU1) { xFastCall(mVUcleanUpVU0); }
|
||||
else { xFastCall(mVUcleanUpVU1); }
|
||||
}
|
||||
|
||||
xRET();
|
||||
|
|
|
|||
|
|
@ -1219,8 +1219,7 @@ static __fi void mVU_XGKICK_DELAY(mV) {
|
|||
xMOV (ptr32[&mVU.resumePtrXG], (uptr)xGetPtr() + 10 + 6);
|
||||
xJcc32(Jcc_NotZero, (uptr)mVU.exitFunctXG - ((uptr)xGetPtr()+6));
|
||||
#endif
|
||||
xMOV(gprT2, ptr32[&mVU.VIxgkick]);
|
||||
xCALL(mVU_XGKICK_);
|
||||
xFastCall(mVU_XGKICK_, ptr32[&mVU.VIxgkick]);
|
||||
mVUrestoreRegs(mVU);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -249,15 +249,15 @@ void recBC2TL() { _setupBranchTest(JZ32, true); }
|
|||
void COP2_Interlock(bool mBitSync) {
|
||||
if (cpuRegs.code & 1) {
|
||||
iFlushCall(FLUSH_EVERYTHING | FLUSH_PC);
|
||||
if (mBitSync) xCALL(_vu0WaitMicro);
|
||||
else xCALL(_vu0FinishMicro);
|
||||
if (mBitSync) xFastCall(_vu0WaitMicro);
|
||||
else xFastCall(_vu0FinishMicro);
|
||||
}
|
||||
}
|
||||
|
||||
void TEST_FBRST_RESET(FnType_Void* resetFunct, int vuIndex) {
|
||||
xTEST(eax, (vuIndex) ? 0x200 : 0x002);
|
||||
xForwardJZ8 skip;
|
||||
xCALL(resetFunct);
|
||||
xFastCall(resetFunct);
|
||||
xMOV(eax, ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]);
|
||||
skip.SetTarget();
|
||||
}
|
||||
|
|
@ -316,8 +316,8 @@ static void recCTC2() {
|
|||
xMOV(ecx, ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]);
|
||||
}
|
||||
else xXOR(ecx, ecx);
|
||||
xCALL(vu1ExecMicro);
|
||||
xCALL(vif1VUFinish);
|
||||
xFastCall(vu1ExecMicro, ecx);
|
||||
xFastCall(vif1VUFinish);
|
||||
break;
|
||||
case REG_FBRST:
|
||||
if (!_Rt_) {
|
||||
|
|
@ -336,8 +336,7 @@ static void recCTC2() {
|
|||
// Executing vu0 block here fixes the intro of Ratchet and Clank
|
||||
// sVU's COP2 has a comment that "Donald Duck" needs this too...
|
||||
if (_Rd_) _eeMoveGPRtoM((uptr)&vu0Regs.VI[_Rd_].UL, _Rt_);
|
||||
xMOV(ecx, (uptr)CpuVU0);
|
||||
xCALL(BaseVUmicroCPU::ExecuteBlockJIT);
|
||||
xFastCall(BaseVUmicroCPU::ExecuteBlockJIT, (uptr)CpuVU0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue