From e3d5eb5a4e51b7d964aa7c394e0954d0a3e2d330 Mon Sep 17 00:00:00 2001 From: Gregory Hainaut Date: Mon, 11 Jan 2016 08:26:00 +0100 Subject: [PATCH] core: convert xCALL to xFastCall SuperVU wasn't converted (unlikely to be ported to 64 bits) A couple of calls weren't converted because they require extra work but there are not mandatory (debug/MTVU/...) --- pcsx2/x86/iCOP0.cpp | 19 ++++++------- pcsx2/x86/iFPU.cpp | 6 ++-- pcsx2/x86/iFPUd.cpp | 16 +---------- pcsx2/x86/iMMI.cpp | 2 +- pcsx2/x86/iR3000A.cpp | 28 +++++++++---------- pcsx2/x86/iR3000Atables.cpp | 20 ++++++------- pcsx2/x86/iR5900Misc.cpp | 4 +-- pcsx2/x86/ix86-32/iR5900-32.cpp | 45 ++++++++++++++---------------- pcsx2/x86/ix86-32/iR5900Branch.cpp | 2 +- pcsx2/x86/ix86-32/recVTLB.cpp | 11 +++----- pcsx2/x86/microVU_Branch.inl | 12 ++++---- pcsx2/x86/microVU_Compile.inl | 19 ++++--------- pcsx2/x86/microVU_Execute.inl | 8 +++--- pcsx2/x86/microVU_Lower.inl | 3 +- pcsx2/x86/microVU_Macro.inl | 13 ++++----- 15 files changed, 88 insertions(+), 120 deletions(-) diff --git a/pcsx2/x86/iCOP0.cpp b/pcsx2/x86/iCOP0.cpp index 309bd9b265..a4b672edb5 100644 --- a/pcsx2/x86/iCOP0.cpp +++ b/pcsx2/x86/iCOP0.cpp @@ -112,7 +112,7 @@ void recDI() //xMOV(eax, ptr[&cpuRegs.cycle ]); //xMOV(ptr[&g_nextBranchCycle], eax); - //xCALL((void*)(uptr)Interp::DI ); + //xFastCall((void*)(uptr)Interp::DI ); xMOV(eax, ptr[&cpuRegs.CP0.n.Status]); xTEST(eax, 0x20006); // EXL | ERL | EDI @@ -170,12 +170,12 @@ void recMFC0() case 1: iFlushCall(FLUSH_INTERPRETER); - xCALL( COP0_UpdatePCCR ); + xFastCall(COP0_UpdatePCCR ); xMOV(eax, ptr[&cpuRegs.PERF.n.pcr0]); break; case 3: iFlushCall(FLUSH_INTERPRETER); - xCALL( COP0_UpdatePCCR ); + xFastCall(COP0_UpdatePCCR ); xMOV(eax, ptr[&cpuRegs.PERF.n.pcr1]); break; } @@ -207,8 +207,7 @@ void recMTC0() { case 12: iFlushCall(FLUSH_INTERPRETER); - xMOV( ecx, g_cpuConstRegs[_Rt_].UL[0] ); - xCALL( WriteCP0Status ); + xFastCall(WriteCP0Status, g_cpuConstRegs[_Rt_].UL[0] ); break; case 9: @@ -222,9 +221,9 @@ void recMTC0() { case 0: iFlushCall(FLUSH_INTERPRETER); - xCALL( COP0_UpdatePCCR ); + xFastCall(COP0_UpdatePCCR ); xMOV( ptr32[&cpuRegs.PERF.n.pccr], g_cpuConstRegs[_Rt_].UL[0] ); - xCALL( COP0_DiagnosticPCCR ); + xFastCall(COP0_DiagnosticPCCR ); break; case 1: @@ -257,7 +256,7 @@ void recMTC0() case 12: iFlushCall(FLUSH_INTERPRETER); _eeMoveGPRtoR(ecx, _Rt_); - xCALL( WriteCP0Status ); + xFastCall(WriteCP0Status, ecx ); break; case 9: @@ -271,9 +270,9 @@ void recMTC0() { case 0: iFlushCall(FLUSH_INTERPRETER); - xCALL( COP0_UpdatePCCR ); + xFastCall(COP0_UpdatePCCR ); _eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_); - xCALL( COP0_DiagnosticPCCR ); + xFastCall(COP0_DiagnosticPCCR ); break; case 1: diff --git a/pcsx2/x86/iFPU.cpp b/pcsx2/x86/iFPU.cpp index 9208aaecb5..3513df4c3a 100644 --- a/pcsx2/x86/iFPU.cpp +++ b/pcsx2/x86/iFPU.cpp @@ -92,7 +92,7 @@ static const __aligned16 u32 s_pos[4] = { 0x7fffffff, 0xffffffff, 0xffffffff, 0x void f(); \ void rec##f() { \ iFlushCall(FLUSH_INTERPRETER); \ - xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \ + xFastCall((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \ branch = 2; \ } @@ -100,7 +100,7 @@ static const __aligned16 u32 s_pos[4] = { 0x7fffffff, 0xffffffff, 0xffffffff, 0x void f(); \ void rec##f() { \ iFlushCall(FLUSH_INTERPRETER); \ - xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \ + xFastCall((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \ } //------------------------------------------------------------------ @@ -550,7 +550,7 @@ void FPU_MUL(int regd, int regt, bool reverseOperands) { xMOVD(ecx, xRegisterSSE(reverseOperands ? regt : regd)); xMOVD(edx, xRegisterSSE(reverseOperands ? regd : regt)); - xCALL((void*)(uptr)&FPU_MUL_HACK ); //returns the hacked result or 0 + xFastCall((void*)(uptr)&FPU_MUL_HACK, ecx, edx); //returns the hacked result or 0 xTEST(eax, eax); noHack = JZ8(0); xMOVDZX(xRegisterSSE(regd), eax); diff --git a/pcsx2/x86/iFPUd.cpp b/pcsx2/x86/iFPUd.cpp index fd60ade533..ee397d9054 100644 --- a/pcsx2/x86/iFPUd.cpp +++ b/pcsx2/x86/iFPUd.cpp @@ -89,20 +89,6 @@ namespace DOUBLE { #define FPUflagSO 0X00000010 #define FPUflagSU 0X00000008 -#define REC_FPUBRANCH(f) \ - void f(); \ - void rec##f() { \ - iFlushCall(FLUSH_INTERPRETER); \ - xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \ - branch = 2; \ -} - -#define REC_FPUFUNC(f) \ - void f(); \ - void rec##f() { \ - iFlushCall(FLUSH_INTERPRETER); \ - xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::COP1::f); \ -} //------------------------------------------------------------------ //------------------------------------------------------------------ @@ -416,7 +402,7 @@ void FPU_MUL(int info, int regd, int sreg, int treg, bool acc) { xMOVD(ecx, xRegisterSSE(sreg)); xMOVD(edx, xRegisterSSE(treg)); - xCALL((void*)(uptr)&FPU_MUL_HACK ); //returns the hacked result or 0 + xFastCall((void*)(uptr)&FPU_MUL_HACK, ecx, edx); //returns the hacked result or 0 xTEST(eax, eax); noHack = JZ8(0); xMOVDZX(xRegisterSSE(regd), eax); diff --git a/pcsx2/x86/iMMI.cpp b/pcsx2/x86/iMMI.cpp index eb99ab0f30..5d24c67e9c 100644 --- a/pcsx2/x86/iMMI.cpp +++ b/pcsx2/x86/iMMI.cpp @@ -185,7 +185,7 @@ void recPMFHL() // fall to interp _deleteEEreg(_Rd_, 0); iFlushCall(FLUSH_INTERPRETER); // since calling CALLFunc - xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::MMI::PMFHL ); + xFastCall((void*)(uptr)R5900::Interpreter::OpcodeImpl::MMI::PMFHL ); break; case 0x03: // LH diff --git a/pcsx2/x86/iR3000A.cpp b/pcsx2/x86/iR3000A.cpp index 10a047642f..de1f88b377 100644 --- a/pcsx2/x86/iR3000A.cpp +++ b/pcsx2/x86/iR3000A.cpp @@ -128,8 +128,7 @@ static DynGenFunc* _DynGen_JITCompile() u8* retval = xGetPtr(); - xMOV( ecx, ptr[&psxRegs.pc] ); - xCALL( iopRecRecompile ); + xFastCall(iopRecRecompile, ptr[&psxRegs.pc] ); xMOV( eax, ptr[&psxRegs.pc] ); xMOV( ebx, eax ); @@ -199,7 +198,7 @@ static void _DynGen_Dispatchers() // Place the EventTest and DispatcherReg stuff at the top, because they get called the // most and stand to benefit from strong alignment and direct referencing. iopDispatcherEvent = (DynGenFunc*)xGetPtr(); - xCALL( recEventTest ); + xFastCall(recEventTest ); iopDispatcherReg = _DynGen_DispatcherReg(); iopJITCompile = _DynGen_JITCompile(); @@ -523,11 +522,11 @@ void psxRecompileCodeConst1(R3000AFNPTR constcode, R3000AFNPTR_INFO noconstcode) } if (debug) - xCALL(debug); + xFastCall(debug); #endif irxHLE hle = irxImportHLE(libname, index); if (hle) { - xCALL(hle); + xFastCall(hle); xCMP(eax, 0); xJNE(iopDispatcherReg); } @@ -907,7 +906,7 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch) xSUB(ptr32[&iopCycleEE], eax); xJLE(iopExitRecompiledCode); - xCALL(iopEventTest); + xFastCall(iopEventTest); if( newpc != 0xffffffff ) { @@ -929,7 +928,7 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch) xSUB(eax, ptr32[&g_iopNextEventCycle]); xForwardJS nointerruptpending; - xCALL(iopEventTest); + xFastCall(iopEventTest); if( newpc != 0xffffffff ) { xCMP(ptr32[&psxRegs.pc], newpc); @@ -964,9 +963,9 @@ void rpsxSYSCALL() xMOV(ptr32[&psxRegs.pc], psxpc - 4); _psxFlushCall(FLUSH_NODESTROY); - xMOV( ecx, 0x20 ); // exception code - xMOV( edx, psxbranch==1 ); // branch delay slot? - xCALL( psxException ); + //xMOV( ecx, 0x20 ); // exception code + //xMOV( edx, psxbranch==1 ); // branch delay slot? + xFastCall(psxException, 0x20, psxbranch == 1 ); xCMP(ptr32[&psxRegs.pc], psxpc-4); j8Ptr[0] = JE8(0); @@ -987,9 +986,9 @@ void rpsxBREAK() xMOV(ptr32[&psxRegs.pc], psxpc - 4); _psxFlushCall(FLUSH_NODESTROY); - xMOV( ecx, 0x24 ); // exception code - xMOV( edx, psxbranch==1 ); // branch delay slot? - xCALL( psxException ); + //xMOV( ecx, 0x24 ); // exception code + //xMOV( edx, psxbranch==1 ); // branch delay slot? + xFastCall(psxException, 0x24, psxbranch == 1 ); xCMP(ptr32[&psxRegs.pc], psxpc-4); j8Ptr[0] = JE8(0); @@ -1102,8 +1101,7 @@ static void __fastcall iopRecRecompile( const u32 startpc ) if( IsDebugBuild ) { - xMOV(ecx, psxpc); - xCALL(PreBlockCheck); + xFastCall(PreBlockCheck, psxpc); } // go until the next branch diff --git a/pcsx2/x86/iR3000Atables.cpp b/pcsx2/x86/iR3000Atables.cpp index 07c5ffc78e..1aca465f5d 100644 --- a/pcsx2/x86/iR3000Atables.cpp +++ b/pcsx2/x86/iR3000Atables.cpp @@ -32,7 +32,7 @@ extern u32 g_psxMaxRecMem; static void rpsx##f() { \ xMOV(ptr32[&psxRegs.code], (u32)psxRegs.code); \ _psxFlushCall(FLUSH_EVERYTHING); \ - xCALL((void*)(uptr)psx##f); \ + xFastCall((void*)(uptr)psx##f); \ PSX_DEL_CONST(_Rt_); \ /* branch = 2; */\ } @@ -626,7 +626,7 @@ static void rpsxLB() xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]); if (_Imm_) xADD(ecx, _Imm_); - xCALL( iopMemRead8 ); // returns value in EAX + xFastCall(iopMemRead8, ecx ); // returns value in EAX if (_Rt_) { xMOVSX(eax, al); xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax); @@ -642,7 +642,7 @@ static void rpsxLBU() xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]); if (_Imm_) xADD(ecx, _Imm_); - xCALL( iopMemRead8 ); // returns value in EAX + xFastCall(iopMemRead8, ecx ); // returns value in EAX if (_Rt_) { xMOVZX(eax, al); xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax); @@ -658,7 +658,7 @@ static void rpsxLH() xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]); if (_Imm_) xADD(ecx, _Imm_); - xCALL( iopMemRead16 ); // returns value in EAX + xFastCall(iopMemRead16, ecx ); // returns value in EAX if (_Rt_) { xMOVSX(eax, ax); xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax); @@ -674,7 +674,7 @@ static void rpsxLHU() xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]); if (_Imm_) xADD(ecx, _Imm_); - xCALL( iopMemRead16 ); // returns value in EAX + xFastCall(iopMemRead16, ecx ); // returns value in EAX if (_Rt_) { xMOVZX(eax, ax); xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax); @@ -695,7 +695,7 @@ static void rpsxLW() xTEST(ecx, 0x10000000); j8Ptr[0] = JZ8(0); - xCALL( iopMemRead32 ); // returns value in EAX + xFastCall(iopMemRead32, ecx ); // returns value in EAX if (_Rt_) { xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax); } @@ -721,7 +721,7 @@ static void rpsxSB() xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]); if (_Imm_) xADD(ecx, _Imm_); xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] ); - xCALL( iopMemWrite8 ); + xFastCall(iopMemWrite8, ecx, edx ); } static void rpsxSH() @@ -732,7 +732,7 @@ static void rpsxSH() xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]); if (_Imm_) xADD(ecx, _Imm_); xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] ); - xCALL( iopMemWrite16 ); + xFastCall(iopMemWrite16, ecx, edx ); } static void rpsxSW() @@ -743,7 +743,7 @@ static void rpsxSW() xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]); if (_Imm_) xADD(ecx, _Imm_); xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] ); - xCALL( iopMemWrite32 ); + xFastCall(iopMemWrite32, ecx, edx ); } //// SLL @@ -1371,7 +1371,7 @@ void rpsxRFE() // Test the IOP's INTC status, so that any pending ints get raised. _psxFlushCall(0); - xCALL((void*)(uptr)&iopTestIntc ); + xFastCall((void*)(uptr)&iopTestIntc ); } // R3000A tables diff --git a/pcsx2/x86/iR5900Misc.cpp b/pcsx2/x86/iR5900Misc.cpp index 2a54a6875b..d9f0b28317 100644 --- a/pcsx2/x86/iR5900Misc.cpp +++ b/pcsx2/x86/iR5900Misc.cpp @@ -71,7 +71,7 @@ namespace OpcodeImpl { // xMOV(ptr32[&cpuRegs.code], cpuRegs.code ); // xMOV(ptr32[&cpuRegs.pc], pc ); // iFlushCall(FLUSH_EVERYTHING); -// xCALL((void*)(uptr)CACHE ); +// xFastCall((void*)(uptr)CACHE ); // //branch = 2; // // xCMP(ptr32[(u32*)((int)&cpuRegs.pc)], pc); @@ -203,7 +203,7 @@ void recMTSAH() //xMOV(ptr32[&cpuRegs.code], (u32)cpuRegs.code ); //xMOV(ptr32[&cpuRegs.pc], (u32)pc ); //iFlushCall(FLUSH_EVERYTHING); - //xCALL((void*)(uptr)R5900::Interpreter::OpcodeImpl::CACHE ); + //xFastCall((void*)(uptr)R5900::Interpreter::OpcodeImpl::CACHE ); //branch = 2; } diff --git a/pcsx2/x86/ix86-32/iR5900-32.cpp b/pcsx2/x86/ix86-32/iR5900-32.cpp index a3bd76fd43..8cb340c409 100644 --- a/pcsx2/x86/ix86-32/iR5900-32.cpp +++ b/pcsx2/x86/ix86-32/iR5900-32.cpp @@ -340,7 +340,7 @@ void recBranchCall( void (*func)() ) void recCall( void (*func)() ) { iFlushCall(FLUSH_INTERPRETER); - xCALL(func); + xFastCall(func); } // ===================================================================================================== @@ -380,8 +380,7 @@ static DynGenFunc* _DynGen_JITCompile() u8* retval = xGetAlignedCallTarget(); - xMOV( ecx, ptr[&cpuRegs.pc] ); - xCALL( recRecompile ); + xFastCall(recRecompile, ptr[&cpuRegs.pc] ); xMOV( eax, ptr[&cpuRegs.pc] ); xMOV( ebx, eax ); @@ -417,7 +416,7 @@ static DynGenFunc* _DynGen_DispatcherEvent() { u8* retval = xGetPtr(); - xCALL( recEventTest ); + xFastCall(recEventTest ); return (DynGenFunc*)retval; } @@ -446,7 +445,7 @@ static DynGenFunc* _DynGen_DispatchBlockDiscard() { u8* retval = xGetPtr(); xEMMS(); - xCALL(dyna_block_discard); + xFastCall(dyna_block_discard); xJMP(ExitRecompiledCode); return (DynGenFunc*)retval; } @@ -455,7 +454,7 @@ static DynGenFunc* _DynGen_DispatchPageReset() { u8* retval = xGetPtr(); xEMMS(); - xCALL(dyna_page_reset); + xFastCall(dyna_page_reset); xJMP(ExitRecompiledCode); return (DynGenFunc*)retval; } @@ -916,7 +915,7 @@ void SetBranchReg( u32 reg ) // xCMP(ptr32[&cpuRegs.pc], 0); // j8Ptr[5] = JNE8(0); -// xCALL((void*)(uptr)tempfn); +// xFastCall((void*)(uptr)tempfn); // x86SetJ8( j8Ptr[5] ); iFlushCall(FLUSH_EVERYTHING); @@ -1201,11 +1200,11 @@ void recMemcheck(u32 op, u32 bits, bool store) if (bits == 128) xAND(ecx, ~0x0F); - xCALL(standardizeBreakpointAddress); + xFastCall(standardizeBreakpointAddress, ecx); xMOV(ecx,eax); xMOV(edx,eax); xADD(edx,bits/8); - + // ecx = access address // edx = access address+size @@ -1220,11 +1219,11 @@ void recMemcheck(u32 op, u32 bits, bool store) continue; // logic: memAddress < bpEnd && bpStart < memAddress+memSize - + xMOV(eax,standardizeBreakpointAddress(checks[i].end)); xCMP(ecx,eax); // address < end xForwardJGE8 next1; // if address >= end then goto next1 - + xMOV(eax,standardizeBreakpointAddress(checks[i].start)); xCMP(eax,edx); // start < address+size xForwardJGE8 next2; // if start >= address+size then goto next2 @@ -1232,10 +1231,10 @@ void recMemcheck(u32 op, u32 bits, bool store) // hit the breakpoint if (checks[i].result & MEMCHECK_LOG) { xMOV(edx, store); - xCALL(&dynarecMemLogcheck); + xFastCall(dynarecMemLogcheck, ecx, edx); } if (checks[i].result & MEMCHECK_BREAK) { - xCALL(&dynarecMemcheck); + xFastCall(dynarecMemcheck); } next1.SetTarget(); @@ -1248,7 +1247,7 @@ void encodeBreakpoint() if (isBreakpointNeeded(pc) != 0) { iFlushCall(FLUSH_EVERYTHING|FLUSH_PC); - xCALL(&dynarecCheckBreakpoint); + xFastCall(dynarecCheckBreakpoint); } } @@ -1297,7 +1296,7 @@ void recompileNextInstruction(int delayslot) s_pCode = (int *)PSM( pc ); pxAssert(s_pCode); - + if( IsDebugBuild ) xMOV(eax, pc); // acts as a tag for delimiting recompiled instructions when viewing x86 disasm. @@ -1660,7 +1659,7 @@ static void __fastcall recRecompile( const u32 startpc ) if (0x8000d618 == startpc) DbgCon.WriteLn("Compiling block @ 0x%08x", startpc); - + s_pCurBlock = PC_GETBLOCK(startpc); pxAssert(s_pCurBlock->GetFnptr() == (uptr)JITCompile @@ -1674,14 +1673,14 @@ static void __fastcall recRecompile( const u32 startpc ) pxAssert(s_pCurBlockEx); if (g_SkipBiosHack && HWADDR(startpc) == EELOAD_START) { - xCALL(eeloadReplaceOSDSYS); + xFastCall(eeloadReplaceOSDSYS); xCMP(ptr32[&cpuRegs.pc], startpc); xJNE(DispatcherReg); } // this is the only way patches get applied, doesn't depend on a hack if (HWADDR(startpc) == ElfEntry) { - xCALL(eeGameStarting); + xFastCall(eeGameStarting); // Apply patch as soon as possible. Normally it is done in // eeGameStarting but first block is already compiled. // @@ -1711,20 +1710,18 @@ static void __fastcall recRecompile( const u32 startpc ) // [TODO] : These must be enabled from the GUI or INI to be used, otherwise the // code that calls PreBlockCheck will not be generated. - xMOV(ecx, pc); - xCALL(PreBlockCheck); + xFastCall(PreBlockCheck, pc); } if (EmuConfig.Gamefixes.GoemonTlbHack) { if (pc == 0x33ad48 || pc == 0x35060c) { // 0x33ad48 and 0x35060c are the return address of the function (0x356250) that populate the TLB cache - xCALL(GoemonPreloadTlb); + xFastCall(GoemonPreloadTlb); } else if (pc == 0x3563b8) { // Game will unmap some virtual addresses. If a constant address were hardcoded in the block, we would be in a bad situation. AtomicExchange( eeRecNeedsReset, true ); // 0x3563b8 is the start address of the function that invalidate entry in TLB cache - xMOV(ecx, ptr[&cpuRegs.GPR.n.a0.UL[ 0 ] ]); - xCALL(GoemonUnloadTlb); + xFastCall(GoemonUnloadTlb, ptr[&cpuRegs.GPR.n.a0.UL[0]]); } } @@ -1745,7 +1742,7 @@ static void __fastcall recRecompile( const u32 startpc ) while(1) { BASEBLOCK* pblock = PC_GETBLOCK(i); - + // stop before breakpoints if (isBreakpointNeeded(i) != 0 || isMemcheckNeeded(i) != 0) { diff --git a/pcsx2/x86/ix86-32/iR5900Branch.cpp b/pcsx2/x86/ix86-32/iR5900Branch.cpp index dd8861ea76..e9c6cebe24 100644 --- a/pcsx2/x86/ix86-32/iR5900Branch.cpp +++ b/pcsx2/x86/ix86-32/iR5900Branch.cpp @@ -396,7 +396,7 @@ EERECOMPILE_CODE0(BNEL, XMMINFO_READS|XMMINFO_READT); // xMOV(ptr32[(u32*)((int)&cpuRegs.code)], cpuRegs.code ); // xMOV(ptr32[(u32*)((int)&cpuRegs.pc)], pc ); // iFlushCall(FLUSH_EVERYTHING); -// xCALL((void*)(int)BLTZAL ); +// xFastCall((void*)(int)BLTZAL ); // branch = 2; //} diff --git a/pcsx2/x86/ix86-32/recVTLB.cpp b/pcsx2/x86/ix86-32/recVTLB.cpp index aace596c2c..3b0eb0e797 100644 --- a/pcsx2/x86/ix86-32/recVTLB.cpp +++ b/pcsx2/x86/ix86-32/recVTLB.cpp @@ -310,7 +310,7 @@ void vtlb_dynarec_init() // jump to the indirect handler, which is a __fastcall C++ function. // [ecx is address, edx is data] - xCALL( ptr32[(eax*4) + vtlbdata.RWFT[bits][mode]] ); + xFastCall(ptr32[(eax*4) + vtlbdata.RWFT[bits][mode]], ecx, edx); if (!mode) { @@ -406,8 +406,7 @@ void vtlb_DynGenRead64_Const( u32 bits, u32 addr_const ) } iFlushCall(FLUSH_FULLVTLB); - xMOV( ecx, paddr ); - xCALL( vtlbdata.RWFT[szidx][0][handler] ); + xFastCall( vtlbdata.RWFT[szidx][0][handler], paddr ); } } @@ -470,8 +469,7 @@ void vtlb_DynGenRead32_Const( u32 bits, bool sign, u32 addr_const ) else { iFlushCall(FLUSH_FULLVTLB); - xMOV( ecx, paddr ); - xCALL( vtlbdata.RWFT[szidx][0][handler] ); + xFastCall( vtlbdata.RWFT[szidx][0][handler], paddr ); // perform sign extension on the result: @@ -561,8 +559,7 @@ void vtlb_DynGenWrite_Const( u32 bits, u32 addr_const ) } iFlushCall(FLUSH_FULLVTLB); - xMOV( ecx, paddr ); - xCALL( vtlbdata.RWFT[szidx][1][handler] ); + xFastCall( vtlbdata.RWFT[szidx][1][handler], paddr, edx ); } } diff --git a/pcsx2/x86/microVU_Branch.inl b/pcsx2/x86/microVU_Branch.inl index 11d588bb71..b26ec3f729 100644 --- a/pcsx2/x86/microVU_Branch.inl +++ b/pcsx2/x86/microVU_Branch.inl @@ -57,8 +57,8 @@ void mVUDTendProgram(mV, microFlagCycles* mFC, int isEbit) { mVU_XGKICK_DELAY(mVU); } if (doEarlyExit(mVU)) { - if (!isVU1) xCALL(mVU0clearlpStateJIT); - else xCALL(mVU1clearlpStateJIT); + if (!isVU1) xFastCall(mVU0clearlpStateJIT); + else xFastCall(mVU1clearlpStateJIT); } } @@ -117,9 +117,9 @@ void mVUendProgram(mV, microFlagCycles* mFC, int isEbit) { } if (doEarlyExit(mVU)) { if (!isVU1) - xCALL(mVU0clearlpStateJIT); + xFastCall(mVU0clearlpStateJIT); else - xCALL(mVU1clearlpStateJIT); + xFastCall(mVU1clearlpStateJIT); } } @@ -192,8 +192,8 @@ void normJumpCompile(mV, microFlagCycles& mFC, bool isEvilJump) { xJMP(mVU.exitFunct); } - if (!mVU.index) xCALL(mVUcompileJIT<0>); //(u32 startPC, uptr pState) - else xCALL(mVUcompileJIT<1>); + if (!mVU.index) xFastCall(mVUcompileJIT<0>, gprT2, gprT3); //(u32 startPC, uptr pState) + else xFastCall(mVUcompileJIT<1>, gprT2, gprT3); mVUrestoreRegs(mVU); xJMP(gprT1); // Jump to rec-code address diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl index cb8318ab69..264527d6c5 100644 --- a/pcsx2/x86/microVU_Compile.inl +++ b/pcsx2/x86/microVU_Compile.inl @@ -194,10 +194,8 @@ __fi void handleBadOp(mV, int count) { #ifdef PCSX2_DEVBUILD if (mVUinfo.isBadOp) { mVUbackupRegs(mVU, true); - xMOV(gprT2, mVU.prog.cur->idx); - xMOV(gprT3, xPC); - if (!isVU1) xCALL(mVUbadOp0); - else xCALL(mVUbadOp1); + if (!isVU1) xFastCall(mVUbadOp0, mVU.prog.cur->idx, xPC); + else xFastCall(mVUbadOp1, mVU.prog.cur->idx, xPC); mVUrestoreRegs(mVU, true); } #endif @@ -345,9 +343,8 @@ void mVUsetCycles(mV) { void mVUdebugPrintBlocks(microVU& mVU, bool isEndPC) { if (mVUdebugNow) { mVUbackupRegs(mVU, true); - xMOV(gprT2, xPC); - if (isEndPC) xCALL(mVUprintPC2); - else xCALL(mVUprintPC1); + if (isEndPC) xFastCall(mVUprintPC2, xPC); + else xFastCall(mVUprintPC1, xPC); mVUrestoreRegs(mVU, true); } } @@ -375,9 +372,7 @@ void mVUtestCycles(microVU& mVU) { // TEST32ItoM((uptr)&mVU.regs().flags, VUFLAG_MFLAGSET); // xFowardJZ32 vu0jmp; // mVUbackupRegs(mVU, true); - // xMOV(gprT2, mVU.prog.cur->idx); - // xMOV(gprT3, xPC); - // xCALL(mVUwarning0); // VU0 is allowed early exit for COP2 Interlock Simulation + // xFastCall(mVUwarning0, mVU.prog.cur->idx, xPC); // VU0 is allowed early exit for COP2 Interlock Simulation // mVUrestoreRegs(mVU, true); mVUsavePipelineState(mVU); mVUendProgram(mVU, NULL, 0); @@ -385,9 +380,7 @@ void mVUtestCycles(microVU& mVU) { } else { mVUbackupRegs(mVU, true); - xMOV(gprT2, mVU.prog.cur->idx); - xMOV(gprT3, xPC); - xCALL(mVUwarning1); + xFastCall(mVUwarning1, mVU.prog.cur->idx, xPC); mVUrestoreRegs(mVU, true); mVUsavePipelineState(mVU); mVUendProgram(mVU, NULL, 0); diff --git a/pcsx2/x86/microVU_Execute.inl b/pcsx2/x86/microVU_Execute.inl index 0aaaeef15d..3c88f2e2e3 100644 --- a/pcsx2/x86/microVU_Execute.inl +++ b/pcsx2/x86/microVU_Execute.inl @@ -27,8 +27,8 @@ void mVUdispatcherAB(mV) { xScopedStackFrame frame(false, true); // __fastcall = The caller has already put the needed parameters in ecx/edx: - if (!isVU1) { xCALL(mVUexecuteVU0); } - else { xCALL(mVUexecuteVU1); } + if (!isVU1) { xFastCall(mVUexecuteVU0, ecx, edx); } + else { xFastCall(mVUexecuteVU1, ecx, edx); } // Load VU's MXCSR state xLDMXCSR(g_sseVUMXCSR); @@ -61,8 +61,8 @@ void mVUdispatcherAB(mV) { // __fastcall = The first two DWORD or smaller arguments are passed in ECX and EDX registers; // all other arguments are passed right to left. - if (!isVU1) { xCALL(mVUcleanUpVU0); } - else { xCALL(mVUcleanUpVU1); } + if (!isVU1) { xFastCall(mVUcleanUpVU0); } + else { xFastCall(mVUcleanUpVU1); } } xRET(); diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl index 80bc07e995..ddb42cb26d 100644 --- a/pcsx2/x86/microVU_Lower.inl +++ b/pcsx2/x86/microVU_Lower.inl @@ -1219,8 +1219,7 @@ static __fi void mVU_XGKICK_DELAY(mV) { xMOV (ptr32[&mVU.resumePtrXG], (uptr)xGetPtr() + 10 + 6); xJcc32(Jcc_NotZero, (uptr)mVU.exitFunctXG - ((uptr)xGetPtr()+6)); #endif - xMOV(gprT2, ptr32[&mVU.VIxgkick]); - xCALL(mVU_XGKICK_); + xFastCall(mVU_XGKICK_, ptr32[&mVU.VIxgkick]); mVUrestoreRegs(mVU); } diff --git a/pcsx2/x86/microVU_Macro.inl b/pcsx2/x86/microVU_Macro.inl index a725ddc02f..214f9319e7 100644 --- a/pcsx2/x86/microVU_Macro.inl +++ b/pcsx2/x86/microVU_Macro.inl @@ -249,15 +249,15 @@ void recBC2TL() { _setupBranchTest(JZ32, true); } void COP2_Interlock(bool mBitSync) { if (cpuRegs.code & 1) { iFlushCall(FLUSH_EVERYTHING | FLUSH_PC); - if (mBitSync) xCALL(_vu0WaitMicro); - else xCALL(_vu0FinishMicro); + if (mBitSync) xFastCall(_vu0WaitMicro); + else xFastCall(_vu0FinishMicro); } } void TEST_FBRST_RESET(FnType_Void* resetFunct, int vuIndex) { xTEST(eax, (vuIndex) ? 0x200 : 0x002); xForwardJZ8 skip; - xCALL(resetFunct); + xFastCall(resetFunct); xMOV(eax, ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); skip.SetTarget(); } @@ -316,8 +316,8 @@ static void recCTC2() { xMOV(ecx, ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); } else xXOR(ecx, ecx); - xCALL(vu1ExecMicro); - xCALL(vif1VUFinish); + xFastCall(vu1ExecMicro, ecx); + xFastCall(vif1VUFinish); break; case REG_FBRST: if (!_Rt_) { @@ -336,8 +336,7 @@ static void recCTC2() { // Executing vu0 block here fixes the intro of Ratchet and Clank // sVU's COP2 has a comment that "Donald Duck" needs this too... if (_Rd_) _eeMoveGPRtoM((uptr)&vu0Regs.VI[_Rd_].UL, _Rt_); - xMOV(ecx, (uptr)CpuVU0); - xCALL(BaseVUmicroCPU::ExecuteBlockJIT); + xFastCall(BaseVUmicroCPU::ExecuteBlockJIT, (uptr)CpuVU0); break; } }