mirror of https://github.com/PCSX2/pcsx2.git
So.. I got an "unlazy" day, and coded a bit more of my iop dma handler.
It's disabled in the code, so that it wont' affect normal users. The code isn't working properly yet. Only handlers for cdvd and spu2 are in it: - the cdvd one doesn't work because of the way pcsx2 handles cdvd currently - the spu2 one seems to work, but it's not implemented in the plugin interface, so ATM it's just "faking" it using the old functions. So really nothing worth testing, just commiting to let people know I'm actually working on it... with long pauses in between. xD git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1052 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
gigaherz
parent
2ac355eb03
commit
e22a50a7c8
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@ -937,6 +937,34 @@ void psxDma3(u32 madr, u32 bcr, u32 chcr) {
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psxDmaInterrupt(3);
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}
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#ifdef ENABLE_NEW_IOPDMA
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s32 cdvdDmaRead(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed)
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{
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// hacked up from the code above
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if (cdr.Readed == 0)
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{
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//CDR_LOG("*** DMA 3 *** NOT READY");
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wordsProcessed = 0;
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return 10000;
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}
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memcpy_fast(data, cdr.pTransfer, wordsLeft);
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//psxCpu->Clear(madr, cdsize/4);
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cdr.pTransfer+=wordsLeft;
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*wordsProcessed = wordsLeft;
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Console::Status("New IOP DMA handled CDVD DMA: channel %d, data %p, remaining %08x, processed %08x.", params channel,data,wordsLeft, *wordsProcessed);
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return 0;
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}
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void cdvdDmaInterrupt(s32 channel)
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{
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cdrInterrupt();
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}
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#endif
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void cdrReset() {
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memzero_obj(cdr);
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cdr.CurTrack=1;
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@ -29,10 +29,10 @@
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#include "Sio.h"
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#include "Sif.h"
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#include "IopDma.h"
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#include "IopMem.h"
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#include "IopHw.h"
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#include "IopBios.h"
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#include "IopDma.h"
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#include "IopCounters.h"
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#include "IopSio2.h"
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@ -38,8 +38,7 @@
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#define PSXPIXEL ((int)(PSXCLK / 13500000))
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#define PSXSOUNDCLK ((int)(48000))
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psxCounter psxCounters[8];
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psxCounter psxCounters[NUM_COUNTERS];
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s32 psxNextCounter;
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u32 psxNextsCounter;
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u8 psxhblankgate = 0;
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@ -141,6 +140,12 @@ void psxRcntInit() {
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psxCounters[7].mode = 0x8;
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}
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#ifdef ENABLE_NEW_IOPDMA
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psxCounters[8].rate = 2000;
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psxCounters[8].CycleT = psxCounters[7].rate;
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psxCounters[8].mode = 0x8;
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#endif
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for (i=0; i<8; i++)
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psxCounters[i].sCycleT = psxRegs.cycle;
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@ -453,6 +458,24 @@ void psxRcntUpdate()
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if (c < psxNextCounter) psxNextCounter = c;
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}
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#ifdef ENABLE_NEW_IOPDMA
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// New Iop DMA handler WIP
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{
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const s32 difference = psxRegs.cycle - psxCounters[8].sCycleT;
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s32 c = psxCounters[8].CycleT;
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if(difference >= psxCounters[8].CycleT)
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{
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psxCounters[8].sCycleT = psxRegs.cycle;
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psxCounters[8].CycleT = psxCounters[8].rate;
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IopDmaUpdate(difference);
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}
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else c -= difference;
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if (c < psxNextCounter) psxNextCounter = c;
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}
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#endif
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for (i=0; i<6; i++) _rcntSet( i );
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}
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@ -27,7 +27,13 @@ struct psxCounter {
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s32 CycleT;
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};
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extern psxCounter psxCounters[8];
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#ifdef ENABLE_NEW_IOPDMA
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# define NUM_COUNTERS 9
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#else
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# define NUM_COUNTERS 8
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#endif
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extern psxCounter psxCounters[NUM_COUNTERS];
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extern s32 psxNextCounter;
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extern u32 psxNextsCounter;
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170
pcsx2/IopDma.cpp
170
pcsx2/IopDma.cpp
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@ -258,35 +258,96 @@ void iopIntcIrq(uint irqType)
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//
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// fixme: Is this in progress?
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#if FALSE
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#ifdef ENABLE_NEW_IOPDMA
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typedef s32(* DmaHandler)(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed);
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typedef void (* DmaIHandler)(s32 channel);
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s32 errDmaWrite(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed);
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s32 errDmaRead(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed);
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struct DmaHandlerInfo
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s32 spu2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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DmaHandler Read;
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DmaHandler Write;
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DmaIHandler Interrupt;
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};
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// FIXME: change the plugin interfaces so that they are aware of this new dma handler
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struct DmaStatusInfo
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/*
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u32 bytes = 1024;
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if(bytesLeft<1024)
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bytes=bytesLeft;
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*/
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u32 bytes=bytesLeft;
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// Update the spu2 to the current cycle before initiating the DMA
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if (SPU2async)
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{
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
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//Console::Status("cycles sent to SPU2 %x\n", psxRegs.cycle - psxCounters[6].sCycleT);
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psxCounters[6].sCycleT = psxRegs.cycle;
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psxCounters[6].CycleT = bytes * 3;
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psxNextCounter -= (psxRegs.cycle - psxNextsCounter);
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psxNextsCounter = psxRegs.cycle;
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if (psxCounters[6].CycleT < psxNextCounter)
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psxNextCounter = psxCounters[6].CycleT;
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}
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if(channel==7)
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SPU2readDMA7Mem((u16 *)data, bytes/2);
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else
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SPU2readDMA4Mem((u16 *)data, bytes/2);
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*bytesProcessed = bytes;
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return 0;
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}
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s32 spu2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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u32 Control;
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u32 Width; // bytes/word, for timing purposes
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u32 MemAddr;
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u32 ByteCount;
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u32 Target;
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};
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// FIXME: change the plugin interfaces so that they are aware of this new dma handler
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// FIXME: Dummy constants, to be "filled in" with proper values later
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#define DMA_CTRL_ACTIVE 0x80000000
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#define DMA_CTRL_DIRECTION 0x00000001
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#define DMA_CHANNEL_MAX 16 /* ? */
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/*
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u32 bytes = 1024;
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if(bytesLeft<1024)
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bytes=bytesLeft;
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*/
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u32 bytes=bytesLeft;
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// Update the spu2 to the current cycle before initiating the DMA
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if (SPU2async)
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{
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
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//Console::Status("cycles sent to SPU2 %x\n", psxRegs.cycle - psxCounters[6].sCycleT);
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psxCounters[6].sCycleT = psxRegs.cycle;
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psxCounters[6].CycleT = bytes * 3;
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psxNextCounter -= (psxRegs.cycle - psxNextsCounter);
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psxNextsCounter = psxRegs.cycle;
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if (psxCounters[6].CycleT < psxNextCounter)
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psxNextCounter = psxCounters[6].CycleT;
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}
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if(channel==7)
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SPU2writeDMA7Mem((u16 *)data, bytes/2);
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else
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SPU2writeDMA4Mem((u16 *)data, bytes/2);
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*bytesProcessed = bytes;
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return 0;
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}
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void spu2DmaInterrupt(s32 channel)
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{
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if(channel==7)
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SPU2interruptDMA7();
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else
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SPU2interruptDMA4();
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}
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//typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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//typedef void (* DmaIHandler)(s32 channel);
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s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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DmaStatusInfo IopChannels[DMA_CHANNEL_MAX]; // I dont' knwo how many there are, 10?
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@ -300,9 +361,9 @@ DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] =
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{0}, //5
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{0}, //6: OT?
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{spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //7: Spu Core1
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{dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
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{sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
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{sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
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{0},//{dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
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{0},//{sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
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{0},//{sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
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{0}, // Sio2
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{0}, // Sio2
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};
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@ -324,26 +385,37 @@ const char* IopDmaNames[DMA_CHANNEL_MAX] =
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"Sio2",
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"?", "?", "?"
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};
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};
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// Prototypes. To be implemented later (or in other parts of the emulator)
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void SetDmaUpdateTarget(u32 delay);
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void RaiseDmaIrq(u32 channel);
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void SetDmaUpdateTarget(u32 delay)
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{
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psxCounters[8].CycleT = delay;
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}
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void RaiseDmaIrq(u32 channel)
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{
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if(channel<7)
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psxDmaInterrupt(channel);
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else
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psxDmaInterrupt2(channel-7);
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}
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// WARNING: CALLER ****[MUST]**** CALL IopDmaUpdate RIGHT AFTER THIS!
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void IopDmaStart(int channel, u32 chcr, u32 madr, u32 bcr)
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{
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// I dont' really understand this, but it's used above. Is this BYTES OR WHAT?
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int size = (bcr >> 16) * (bcr & 0xFFFF);
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int size = 4* (bcr >> 16) * (bcr & 0xFFFF);
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IopChannels[channel].Control = chcr | DMA_CTRL_ACTIVE;
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IopChannels[channel].MemAddr = madr;
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IopChannels[channel].ByteCount = size;
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SetDmaUpdateTarget(0);
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}
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void IopDmaUpdate(u32 elapsed)
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{
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u32 MinDelay = 0xFFFFFFFF;
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s32 MinDelay = 0x7FFFFFFF;
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for (int i = 0;i < DMA_CHANNEL_MAX;i++)
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{
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@ -363,12 +435,17 @@ void IopDmaUpdate(u32 elapsed)
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else
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{
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// TODO: Make sure it's the right order
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DmaHandler handler = (ch->Control & DMA_CTRL_DIRECTION) ? IopDmaHandlers[i].Read : IopDmaHandlers[i].Write;
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DmaHandler handler = (ch->Control & DMA_CTRL_DIRECTION) ? IopDmaHandlers[i].Write : IopDmaHandlers[i].Read;
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u32 BCount = 0;
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s32 Target = (handler) ? handler(i, (u32*)PSXM(ch->MemAddr), ch->ByteCount, &BCount) : 0;
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s32 Target = (handler) ? handler(i, (u32*)iopPhysMem(ch->MemAddr), ch->ByteCount, &BCount) : 0;
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ch->Target = 100;
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if(BCount>0)
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{
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psxCpu->Clear(ch->MemAddr, BCount/4);
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}
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int TTarget = 100;
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if (Target < 0)
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{
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// TODO: ... What to do if the plugin errors? :P
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@ -378,29 +455,38 @@ void IopDmaUpdate(u32 elapsed)
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ch->MemAddr += BCount;
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ch->ByteCount -= BCount;
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ch->Target = BCount / ch->Width;
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TTarget = BCount; // / ch->Width;
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}
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if (Target != 0) ch->Target = Target;
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if (Target != 0) TTarget = Target;
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if (ch->Target<MinDelay) MinDelay = TTarget;
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ch->Target += TTarget;
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}
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}
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}
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}
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if(MinDelay<0x7FFFFFFF)
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SetDmaUpdateTarget(MinDelay);
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else
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SetDmaUpdateTarget(10000);
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}
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s32 errDmaRead(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed)
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s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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Console::Error("ERROR: Tried to read using DMA %d (%s). Ignoring.", 0, channel, IopDmaNames[channel]);
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Console::Error("ERROR: Tried to read using DMA %d (%s). Ignoring.", params 0, channel, IopDmaNames[channel]);
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*wordsProcessed = wordsLeft;
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*bytesProcessed = bytesLeft;
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return 0;
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}
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s32 errDmaWrite(s32 channel, u32* data, u32 wordsLeft, u32* wordsProcessed)
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s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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Console::Error("ERROR: Tried to write using DMA %d (%s). Ignoring.", 0, channel, IopDmaNames[channel]);
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Console::Error("ERROR: Tried to write using DMA %d (%s). Ignoring.", params 0, channel, IopDmaNames[channel]);
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*wordsProcessed = wordsLeft;
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*bytesProcessed = bytesLeft;
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return 0;
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}
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@ -21,6 +21,46 @@
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#include "PS2Edefs.h"
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//#define ENABLE_NEW_IOPDMA
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#ifdef ENABLE_NEW_IOPDMA
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typedef s32(* DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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typedef void (* DmaIHandler)(s32 channel);
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struct DmaHandlerInfo
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{
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DmaHandler Read;
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DmaHandler Write;
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DmaIHandler Interrupt;
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};
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struct DmaStatusInfo
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{
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u32 Control;
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u32 Width; // bytes/word, for timing purposes
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u32 MemAddr;
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u32 ByteCount;
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s32 Target;
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};
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// FIXME: Dummy constants, to be "filled in" with proper values later
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#define DMA_CTRL_ACTIVE 0x01000000
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#define DMA_CTRL_DIRECTION 0x00000001
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#define DMA_CHANNEL_MAX 16 /* ? */
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// WARNING: CALLER ****[MUST]**** CALL IopDmaUpdate RIGHT AFTER THIS!
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void IopDmaStart(int channel, u32 chcr, u32 madr, u32 bcr);
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void IopDmaUpdate(u32 elapsed);
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// external dma handlers
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extern s32 cdvdDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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extern void cdvdDmaInterrupt(s32 channel);
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//#else
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#endif
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void psxDma2(u32 madr, u32 bcr, u32 chcr);
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void psxDma3(u32 madr, u32 bcr, u32 chcr);
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void psxDma4(u32 madr, u32 bcr, u32 chcr);
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@ -1020,7 +1020,7 @@ void psxHwWrite32(u32 add, u32 value) {
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case 0x1f8010c8:
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PSXHW_LOG("DMA4 CHCR 32bit write %lx", value);
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HW_DMA4_CHCR = value; // DMA4 chcr (SPU DMA)
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DmaExec(4);
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DmaExecNew(4);
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return;
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//------------------------------------------------------------------
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@ -1053,7 +1053,7 @@ void psxHwWrite32(u32 add, u32 value) {
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case 0x1f801508:
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PSXHW_LOG("DMA7 CHCR 32bit write %lx", value);
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HW_DMA7_CHCR = value; // DMA7 chcr (SPU2)
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DmaExec2(7);
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DmaExecNew2(7);
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return;
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//------------------------------------------------------------------
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@ -69,6 +69,25 @@ enum IOPCountRegs
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} \
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}
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#ifdef ENABLE_NEW_IOPDMA
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#define DmaExecNew(n) { \
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if (HW_DMA##n##_CHCR & 0x01000000 && \
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HW_DMA_PCR & (8 << (n * 4))) { \
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IopDmaStart(n, HW_DMA##n##_CHCR, HW_DMA##n##_MADR, HW_DMA##n##_BCR); \
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} \
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}
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#define DmaExecNew2(n) { \
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if (HW_DMA##n##_CHCR & 0x01000000 && \
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HW_DMA_PCR2 & (8 << ((n-7) * 4))) { \
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IopDmaStart(n, HW_DMA##n##_CHCR, HW_DMA##n##_MADR, HW_DMA##n##_BCR); \
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} \
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||||
}
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||||
#else
|
||||
#define DmaExecNew(n) DmaExec(n)
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||||
#define DmaExecNew2(n) DmaExec2(n)
|
||||
#endif
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||||
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||||
#define HW_DMA0_MADR (psxHu32(0x1080)) // MDEC in DMA
|
||||
#define HW_DMA0_BCR (psxHu32(0x1084))
|
||||
#define HW_DMA0_CHCR (psxHu32(0x1088))
|
||||
|
|
|
|||
Loading…
Reference in New Issue