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pcsx2
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fixed some errors from the last version i submitted, and also added extra clamping support to the remainder of the opcodes. the extra clamping i've been talking about is only enabled when you have Extra FPU Overflow Checks On (when the FPU speedhack is grey). 

git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@108 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes 2008-09-09 04:51:20 +00:00 committed by Gregory Hainaut
parent 55a94259e2
commit e147a43668
1 changed files with 114 additions and 103 deletions
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217
pcsx2/x86/iFPU.c
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@ -1392,7 +1392,7 @@ void recMADDtemp(int info, int regd)
if(regd == EEREC_ACC){
t1reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_MOVSS_M32_to_XMM(t1reg, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_MOVSS_M32_to_XMM(t1reg, (uptr)&fpuRegs.fpr[_Ft_]);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(t0reg); fpuFloat(t1reg); }
SSE_MULSS_XMM_to_XMM(t0reg, t1reg);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
@ -1402,7 +1402,7 @@ void recMADDtemp(int info, int regd)
else
{
SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_MULSS_XMM_to_XMM(regd, t0reg);
if (info & PROCESS_EE_ACC) {
@ -1413,7 +1413,7 @@ void recMADDtemp(int info, int regd)
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_ADDSS_XMM_to_XMM(regd, t0reg);
}
}
}
break;
}
@ -1440,123 +1440,134 @@ FPURECOMPILE_CONSTCODE(MADDA_S, XMMINFO_WRITEACC|XMMINFO_READACC|XMMINFO_READS|X
void recMSUBtemp(int info, int regd)
{
//int vreg;
//u32 mreg;
int t0reg;
int t1reg;
int t0reg = _allocTempXMMreg(XMMT_FPS, -1);
switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
case PROCESS_EE_S:
if(regd == EEREC_S) {
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_S);
SSE_MULSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
if((info&PROCESS_EE_ACC))SSE_MOVSS_XMM_to_XMM(regd, EEREC_ACC);
else SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
} else
if(regd == EEREC_ACC){
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_S);
SSE_MULSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
} else {
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_S);
SSE_MULSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
if((info&PROCESS_EE_ACC))SSE_MOVSS_XMM_to_XMM(regd, EEREC_ACC);
else SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_MULSS_XMM_to_XMM(regd, t0reg);
if (info & PROCESS_EE_ACC) { SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_ACC); }
else { SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC); }
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(t0reg, regd);
SSE_MOVSS_XMM_to_XMM(regd, t0reg);
}
else if (regd == EEREC_ACC){
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_S); fpuFloat(t0reg); }
SSE_MULSS_XMM_to_XMM(t0reg, EEREC_S);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
}
else {
SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Ft_]);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_S); }
SSE_MULSS_XMM_to_XMM(regd, EEREC_S);
if (info & PROCESS_EE_ACC) { SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_ACC); }
else { SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC); }
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(t0reg, regd);
SSE_MOVSS_XMM_to_XMM(regd, t0reg);
}
break;
case PROCESS_EE_T:
if(regd == EEREC_T) {
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_MULSS_XMM_to_XMM(t0reg, EEREC_T);
if((info&PROCESS_EE_ACC))SSE_MOVSS_XMM_to_XMM(regd, EEREC_ACC);
else SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
} else
if(regd == EEREC_ACC){
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_MULSS_XMM_to_XMM(regd, t0reg);
if (info & PROCESS_EE_ACC) { SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_ACC); }
else { SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC); }
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(t0reg, regd);
SSE_MOVSS_XMM_to_XMM(regd, t0reg);
}
else if (regd == EEREC_ACC){
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_T); fpuFloat(t0reg); }
SSE_MULSS_XMM_to_XMM(t0reg, EEREC_T);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
} else {
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
}
else {
SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Fs_]);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_T); }
SSE_MULSS_XMM_to_XMM(regd, EEREC_T);
if (info & PROCESS_EE_ACC) { SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_ACC); }
else { SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC); }
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(t0reg, regd);
SSE_MOVSS_XMM_to_XMM(regd, t0reg);
}
break;
case (PROCESS_EE_S|PROCESS_EE_T):
if(regd == EEREC_S) {
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_T); }
SSE_MULSS_XMM_to_XMM(regd, EEREC_T);
if (info & PROCESS_EE_ACC) { SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_ACC); }
else { SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC); }
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(t0reg, regd);
SSE_MOVSS_XMM_to_XMM(regd, t0reg);
}
else if(regd == EEREC_T) {
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_S); }
SSE_MULSS_XMM_to_XMM(regd, EEREC_S);
if (info & PROCESS_EE_ACC) { SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_ACC); }
else { SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC); }
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(t0reg, regd);
SSE_MOVSS_XMM_to_XMM(regd, t0reg);
}
else if(regd == EEREC_ACC) {
SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_S);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(t0reg); fpuFloat(EEREC_T); }
SSE_MULSS_XMM_to_XMM(t0reg, EEREC_T);
if((info&PROCESS_EE_ACC))SSE_MOVSS_XMM_to_XMM(regd, EEREC_ACC);
else SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
}
else {
SSE_MOVSS_XMM_to_XMM(regd, EEREC_S);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_T); }
SSE_MULSS_XMM_to_XMM(regd, EEREC_T);
if (info & PROCESS_EE_ACC) { SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_ACC); }
else { SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC); }
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(t0reg, regd);
SSE_MOVSS_XMM_to_XMM(regd, t0reg);
}
break;
default:
if((info & PROCESS_EE_S) && (info & PROCESS_EE_T)){
if(regd == EEREC_S) {
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_S);
SSE_MULSS_XMM_to_XMM(t0reg, EEREC_T);
if((info&PROCESS_EE_ACC))SSE_MOVSS_XMM_to_XMM(regd, EEREC_ACC);
else SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
} else
if(regd == EEREC_T) {
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_S);
SSE_MULSS_XMM_to_XMM(t0reg, EEREC_T);
if((info&PROCESS_EE_ACC))SSE_MOVSS_XMM_to_XMM(regd, EEREC_ACC);
else SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
} else
if(regd == EEREC_ACC){
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_S);
SSE_MULSS_XMM_to_XMM(t0reg, EEREC_T);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
} else {
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_S);
SSE_MULSS_XMM_to_XMM(t0reg, EEREC_T);
if((info&PROCESS_EE_ACC))SSE_MOVSS_XMM_to_XMM(regd, EEREC_ACC);
else SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
}
break;
} else {
if(regd == EEREC_ACC){
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_MULSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
}
else
{
t0reg = _allocTempXMMreg(XMMT_FPS, -1);
if((info&PROCESS_EE_ACC))SSE_MOVSS_XMM_to_XMM(regd, EEREC_ACC);
else SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_MULSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t0reg);
}
if(regd == EEREC_ACC){
t1reg = _allocTempXMMreg(XMMT_FPS, -1);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_MOVSS_M32_to_XMM(t1reg, (uptr)&fpuRegs.fpr[_Ft_]);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(t0reg); fpuFloat(t1reg); }
SSE_MULSS_XMM_to_XMM(t0reg, t1reg);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(regd, t0reg);
_freeXMMreg(t1reg);
}
else
{
SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Fs_]);
SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_MULSS_XMM_to_XMM(regd, t0reg);
if (info & PROCESS_EE_ACC) { SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_ACC); }
else { SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC); }
if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
SSE_SUBSS_XMM_to_XMM(t0reg, regd);
SSE_MOVSS_XMM_to_XMM(regd, t0reg);
}
break;
}
ClampValues(regd);
ClampValues(regd);
_freeXMMreg(t0reg);
}
void recMSUB_S_xmm(int info)