mirror of https://github.com/PCSX2/pcsx2.git
more FPU opcodes have extra clamping support. just a few more FPU opcodes to go.
i also realized that VU extra clamping needs more work. i'm hoping this is where God of War's SPS comes from, i'll start coding it as soon as i finish the rest of the FPU opcodes. git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@107 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
44635b6cf7
commit
55a94259e2
195
pcsx2/x86/iFPU.c
195
pcsx2/x86/iFPU.c
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@ -1260,95 +1260,166 @@ void recMULA_S_xmm(int info)
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FPURECOMPILE_CONSTCODE(MULA_S, XMMINFO_WRITEACC|XMMINFO_READS|XMMINFO_READT);
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void recMADDtemp(int info, int regd)
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{
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//int vreg;
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//u32 mreg;
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int t0reg;
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{
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int t1reg;
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int t0reg = _allocTempXMMreg(XMMT_FPS, -1);
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switch(info & (PROCESS_EE_S|PROCESS_EE_T) ) {
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case PROCESS_EE_S:
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if(regd == EEREC_S) {
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SSE_MULSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Ft_]);
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if((info&PROCESS_EE_ACC))SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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else SSE_ADDSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
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} else
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if(regd == EEREC_ACC){
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t0reg = _allocTempXMMreg(XMMT_FPS, -1);
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_MULSS_XMM_to_XMM(regd, t0reg);
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if (info & PROCESS_EE_ACC) {
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(regd); }
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SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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}
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else {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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}
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}
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else if (regd == EEREC_ACC){
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_S); fpuFloat(t0reg); }
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SSE_MULSS_XMM_to_XMM(t0reg, EEREC_S);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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_freeXMMreg(t0reg);
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} else {
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}
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else {
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SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Ft_]);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_S); }
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SSE_MULSS_XMM_to_XMM(regd, EEREC_S);
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if((info&PROCESS_EE_ACC))SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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else SSE_ADDSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
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if (info & PROCESS_EE_ACC) {
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(regd); }
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SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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}
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else {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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}
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}
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break;
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case PROCESS_EE_T:
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if(regd == EEREC_T) {
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SSE_MULSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Fs_]);
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if((info&PROCESS_EE_ACC))SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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} else
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if(regd == EEREC_ACC){
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t0reg = _allocTempXMMreg(XMMT_FPS, -1);
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_MULSS_XMM_to_XMM(regd, t0reg);
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if (info & PROCESS_EE_ACC) {
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(regd); }
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SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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}
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else {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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}
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}
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else if (regd == EEREC_ACC){
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_T); fpuFloat(t0reg); }
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SSE_MULSS_XMM_to_XMM(t0reg, EEREC_T);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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_freeXMMreg(t0reg);
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} else {
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}
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else {
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SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Fs_]);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_T); }
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SSE_MULSS_XMM_to_XMM(regd, EEREC_T);
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if((info&PROCESS_EE_ACC))SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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else SSE_ADDSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
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if (info & PROCESS_EE_ACC) {
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(regd); }
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SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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}
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else {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(EEREC_ACC); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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}
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}
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break;
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case (PROCESS_EE_S|PROCESS_EE_T):
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if(regd == EEREC_S) {
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_T); }
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SSE_MULSS_XMM_to_XMM(regd, EEREC_T);
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if (info & PROCESS_EE_ACC) {
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_ACC); }
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SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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}
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else {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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}
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}
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else if(regd == EEREC_T) {
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_S); }
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SSE_MULSS_XMM_to_XMM(regd, EEREC_S);
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if (info & PROCESS_EE_ACC) {
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_ACC); }
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SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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}
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else {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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}
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}
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else if(regd == EEREC_ACC) {
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SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_S);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(t0reg); fpuFloat(EEREC_T); }
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SSE_MULSS_XMM_to_XMM(t0reg, EEREC_T);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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}
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else {
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SSE_MOVSS_XMM_to_XMM(regd, EEREC_S);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_T); }
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SSE_MULSS_XMM_to_XMM(regd, EEREC_T);
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if (info & PROCESS_EE_ACC) {
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_ACC); }
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SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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}
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else {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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}
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}
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break;
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default:
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if((info & PROCESS_EE_S) && (info & PROCESS_EE_T)){
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if(regd == EEREC_S) {
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SSE_MULSS_XMM_to_XMM(regd, EEREC_T);
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if((info&PROCESS_EE_ACC))SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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else SSE_ADDSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
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} else
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if(regd == EEREC_T) {
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SSE_MULSS_XMM_to_XMM(regd, EEREC_S);
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if((info&PROCESS_EE_ACC))SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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else SSE_ADDSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
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} else
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if(regd == EEREC_ACC){
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t0reg = _allocTempXMMreg(XMMT_FPS, -1);
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SSE_MOVSS_XMM_to_XMM(t0reg, EEREC_S);
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SSE_MULSS_XMM_to_XMM(t0reg, EEREC_T);
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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_freeXMMreg(t0reg);
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} else {
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SSE_MOVSS_XMM_to_XMM(regd, EEREC_S);
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SSE_MULSS_XMM_to_XMM(regd, EEREC_T);
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if((info&PROCESS_EE_ACC))SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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else SSE_ADDSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
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if(regd == EEREC_ACC){
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t1reg = _allocTempXMMreg(XMMT_FPS, -1);
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
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SSE_MOVSS_M32_to_XMM(t1reg, (uptr)&fpuRegs.fpr[_Fs_]);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(t0reg); fpuFloat(t1reg); }
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SSE_MULSS_XMM_to_XMM(t0reg, t1reg);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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_freeXMMreg(t1reg);
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}
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else
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{
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SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Fs_]);
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_MULSS_XMM_to_XMM(regd, t0reg);
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if (info & PROCESS_EE_ACC) {
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(EEREC_ACC); }
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SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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}
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break;
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} else {
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if(regd == EEREC_ACC){
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t0reg = _allocTempXMMreg(XMMT_FPS, -1);
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Fs_]);
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SSE_MULSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.fpr[_Ft_]);
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else {
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SSE_MOVSS_M32_to_XMM(t0reg, (uptr)&fpuRegs.ACC);
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if (CHECK_FPU_EXTRA_OVERFLOW) { fpuFloat(regd); fpuFloat(t0reg); }
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SSE_ADDSS_XMM_to_XMM(regd, t0reg);
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_freeXMMreg(t0reg);
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}
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else
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{
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SSE_MOVSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Fs_]);
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SSE_MULSS_M32_to_XMM(regd, (uptr)&fpuRegs.fpr[_Ft_]);
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if((info&PROCESS_EE_ACC))SSE_ADDSS_XMM_to_XMM(regd, EEREC_ACC);
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else SSE_ADDSS_M32_to_XMM(regd, (uptr)&fpuRegs.ACC);
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}
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}
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}
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break;
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}
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ClampValues(regd);
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_freeXMMreg(t0reg);
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}
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void recMADD_S_xmm(int info)
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