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COP2: Fix CTC2 to R register 

Only 23 bits are writable. Upper 9 bits are hardcoded to 001111111.
This commit is contained in:
Goatman13 2022-07-11 18:18:17 +02:00 committed by refractionpcsx2
parent 8c4fa838fe
commit df1e19dd47
2 changed files with 4 additions and 0 deletions
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3
pcsx2/VU0.cpp
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@ -156,6 +156,9 @@ void CTC2() {
case REG_TPC: // read-only case REG_TPC: // read-only
case REG_VPU_STAT: // read-only case REG_VPU_STAT: // read-only
break; break;
case REG_R:
VU0.VI[REG_R].UL = ((cpuRegs.GPR.r[_Rt_].UL[0] & 0x7FFFFF) | 0x3F800000);
break;
case REG_FBRST: case REG_FBRST:
VU0.VI[REG_FBRST].UL = cpuRegs.GPR.r[_Rt_].UL[0] & 0x0C0C; VU0.VI[REG_FBRST].UL = cpuRegs.GPR.r[_Rt_].UL[0] & 0x0C0C;
if (cpuRegs.GPR.r[_Rt_].UL[0] & 0x1) { // VU0 Force Break if (cpuRegs.GPR.r[_Rt_].UL[0] & 0x1) { // VU0 Force Break

1
pcsx2/x86/microVU_Macro.inl
View File

@ -460,6 +460,7 @@ static void recCTC2()
break; // Read Only Regs break; // Read Only Regs
case REG_R: case REG_R:
xMOV(eax, ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]); xMOV(eax, ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]);
xAND(eax, 0x7FFFFF);
xOR(eax, 0x3f800000); xOR(eax, 0x3f800000);
xMOV(ptr32[&vu0Regs.VI[REG_R].UL], eax); xMOV(ptr32[&vu0Regs.VI[REG_R].UL], eax);
break; break;