From df1e19dd474fec1bedb99a23894d0b291ecc98d3 Mon Sep 17 00:00:00 2001
From: Goatman13 <101417270+Goatman13@users.noreply.github.com>
Date: Mon, 11 Jul 2022 18:18:17 +0200
Subject: [PATCH] COP2: Fix CTC2 to R register

Only 23 bits are writable. Upper 9 bits are hardcoded to 001111111.
---
 pcsx2/VU0.cpp               | 3 +++
 pcsx2/x86/microVU_Macro.inl | 1 +
 2 files changed, 4 insertions(+)

diff --git a/pcsx2/VU0.cpp b/pcsx2/VU0.cpp
index 8f3416ef4f..fc054aad54 100644
--- a/pcsx2/VU0.cpp
+++ b/pcsx2/VU0.cpp
@@ -156,6 +156,9 @@ void CTC2() {
 		case REG_TPC:      // read-only
 		case REG_VPU_STAT: // read-only
 			break;
+		case REG_R:
+			VU0.VI[REG_R].UL = ((cpuRegs.GPR.r[_Rt_].UL[0] & 0x7FFFFF) | 0x3F800000);
+			break;
 		case REG_FBRST:
 			VU0.VI[REG_FBRST].UL = cpuRegs.GPR.r[_Rt_].UL[0] & 0x0C0C;
 			if (cpuRegs.GPR.r[_Rt_].UL[0] & 0x1) { // VU0 Force Break
diff --git a/pcsx2/x86/microVU_Macro.inl b/pcsx2/x86/microVU_Macro.inl
index 4e3966a487..1ab12ddc19 100644
--- a/pcsx2/x86/microVU_Macro.inl
+++ b/pcsx2/x86/microVU_Macro.inl
@@ -460,6 +460,7 @@ static void recCTC2()
 			break; // Read Only Regs
 		case REG_R:
 			xMOV(eax, ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]);
+			xAND(eax, 0x7FFFFF);
 			xOR(eax, 0x3f800000);
 			xMOV(ptr32[&vu0Regs.VI[REG_R].UL], eax);
 			break;