mirror of https://github.com/PCSX2/pcsx2.git
Minor changes:
- Removed small line on PATH3 masking - Fixed a smally bug from my previous cockups - Replaced the SIF irq hack with something that makes more sense. - Removed the vif1DMA call from IPU, this was just causing double IRQ's on VIF1 in Klonoa git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2895 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -105,7 +105,6 @@ static u32 WRITERING_DMA(tDMA_TAG *pMem, u32 qwc)
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int _GIFchain()
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{
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u32 qwc = min( gifsplit, (int)gif->qwc );
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tDMA_TAG *pMem;
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pMem = dmaGetAddr(gif->madr, false);
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@ -121,7 +120,7 @@ int _GIFchain()
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return -1;
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}
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return WRITERING_DMA(pMem, qwc);
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return WRITERING_DMA(pMem, gif->qwc);
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}
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static __forceinline void GIFchain()
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@ -205,11 +204,7 @@ void GIFdma()
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{
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// We are in image mode doing DIRECTHL, Path 1 is in queue, and in intermittant mode.
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//GIF_LOG("Waiting VU %x, PATH2 %x, GIFMODE %x Progress %x", gifRegs->stat.P1Q, (vif1.cmd & 0x7f), gifRegs->mode._u32, GSTransferStatus.PTH3);
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/*if(GSTransferStatus.PTH3 == STOPPED_MODE)
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{
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} else Console.Warning("PATH3 Transfer in action while another one path is running, Path3 mode %x", GSTransferStatus.PTH3);*/
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gifRegs->stat.set_flags(GIF_STAT_P2Q);
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gifRegs->stat.set_flags(GIF_STAT_P3Q);
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CPU_INT(DMAC_GIF, 16);
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return;
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}
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@ -327,7 +322,7 @@ void dmaGIF()
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//It takes the time of 24 QW for the BUS to become ready - The Punisher And Streetball
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GIF_LOG("dmaGIFstart chcr = %lx, madr = %lx, qwc = %lx\n tadr = %lx, asr0 = %lx, asr1 = %lx", gif->chcr._u32, gif->madr, gif->qwc, gif->tadr, gif->asr0, gif->asr1);
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GSTransferStatus.PTH3 = STOPPED_MODE;
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//GSTransferStatus.PTH3 = STOPPED_MODE;
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gspath3done = false; // For some reason this doesn't clear? So when the system starts the thread, we will clear it :)
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gifRegs->stat.P3Q = true;
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@ -16,8 +16,6 @@
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#ifndef __GIF_H__
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#define __GIF_H__
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const int gifsplit = 0x10000;
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enum gifstate_t
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{
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GIF_STATE_READY = 0,
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@ -1644,7 +1644,7 @@ void ipu0Interrupt()
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// vif
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Console.Warning("IPU VIF Stall");
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g_nDMATransfer.VIFSTALL = false;
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if (vif1ch->chcr.STR) dmaVIF1();
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//if (vif1ch->chcr.STR) dmaVIF1();
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}
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if (g_nDMATransfer.SIFSTALL)
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@ -177,18 +177,26 @@ static __forceinline void EndIOP()
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// Handle the EE transfer.
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static __forceinline void HandleEETransfer()
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{
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if(sif0dma->chcr.STR == false)
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{
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DevCon.Warning("Replacement for irq prevention hack EE SIF0");
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sif0.ee.end = false;
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sif0.ee.busy = false;
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return;
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}
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if (dmacRegs->ctrl.STS == STS_SIF0)
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{
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DevCon.Warning("SIF0 stall control");
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}
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if (sif0dma->qwc == 0)
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/*if (sif0dma->qwc == 0)
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if (sif0dma->chcr.MOD == NORMAL_MODE)
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if (!sif0.ee.end){
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DevCon.Warning("sif0 irq prevented");
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done = true;
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return;
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}
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}*/
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if (sif0dma->qwc <= 0)
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{
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@ -280,13 +288,25 @@ static __forceinline void Sif0End()
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// Transfer IOP to EE, putting data in the fifo as an intermediate step.
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__forceinline void SIF0Dma()
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{
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int BusyCheck = 0;
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Sif0Init();
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do
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{
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if (sif0.iop.busy) HandleIOPTransfer();
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if (sif0.ee.busy) HandleEETransfer();
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} while (!done); // Substituting (sif0.ee.busy || sif0.iop.busy) breaks things.
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//I realise this is very hacky in a way but its an easy way of checking if both are doing something
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BusyCheck = 0;
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if (sif0.iop.busy)
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{
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if(sif0.fifo.free() > 0) BusyCheck++;
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HandleIOPTransfer();
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}
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if (sif0.ee.busy)
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{
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if(sif0.fifo.size >= 4) BusyCheck++;
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HandleEETransfer();
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}
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} while (!done && BusyCheck > 0); // Substituting (sif0.ee.busy || sif0.iop.busy) breaks things.
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Sif0End();
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}
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@ -203,18 +203,25 @@ static __forceinline void EndIOP()
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// Handle the EE transfer.
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static __forceinline void HandleEETransfer()
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{
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if(sif1dma->chcr.STR == false)
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{
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DevCon.Warning("Replacement for irq prevention hack EE SIF1");
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sif1.ee.end = false;
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sif1.ee.busy = false;
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return;
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}
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if (dmacRegs->ctrl.STD == STD_SIF1)
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{
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DevCon.Warning("SIF1 stall control"); // STD == fromSIF1
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}
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if (sif1dma->qwc == 0)
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/*if (sif1dma->qwc == 0)
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if (sif1dma->chcr.MOD == NORMAL_MODE)
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if (!sif1.ee.end){
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DevCon.Warning("sif1 irq prevented");
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DevCon.Warning("sif1 irq prevented CHCR %x QWC %x", sif1dma->chcr, sif1dma->qwc);
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done = true;
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return;
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}
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}*/
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// If there's no more to transfer.
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if (sif1dma->qwc <= 0)
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@ -275,13 +282,27 @@ static __forceinline void Sif1End()
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// Transfer EE to IOP, putting data in the fifo as an intermediate step.
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__forceinline void SIF1Dma()
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{
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int BusyCheck = 0;
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Sif1Init();
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do
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{
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if (sif1.ee.busy) HandleEETransfer();
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if (sif1.iop.busy) HandleIOPTransfer();
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} while (!done);
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//I realise this is very hacky in a way but its an easy way of checking if both are doing something
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BusyCheck = 0;
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if (sif1.ee.busy)
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{
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if(sif1.fifo.free() > 0) BusyCheck++;
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HandleEETransfer();
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}
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if (sif1.iop.busy)
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{
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if(sif1.fifo.size >= 4) BusyCheck++;
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HandleIOPTransfer();
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}
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} while (!done && BusyCheck > 0);
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Sif1End();
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}
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@ -300,6 +300,7 @@ __forceinline void vif1Interrupt()
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vif1Regs->stat.VPS = VPS_IDLE; //Vif goes idle as the stall happened between commands;
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vif1ch->chcr.STR = false;
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g_vifCycles = 0;
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VIF_LOG("VIF1 End");
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hwDmacIrq(DMAC_VIF1);
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}
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