diff --git a/pcsx2/Gif.cpp b/pcsx2/Gif.cpp
index f1ec26a8b5..43d8d7da03 100644
--- a/pcsx2/Gif.cpp
+++ b/pcsx2/Gif.cpp
@@ -105,7 +105,6 @@ static u32 WRITERING_DMA(tDMA_TAG *pMem, u32 qwc)
 
 int  _GIFchain()
 {
-	u32 qwc = min( gifsplit, (int)gif->qwc );
 	tDMA_TAG *pMem;
 
 	pMem = dmaGetAddr(gif->madr, false);
@@ -121,7 +120,7 @@ int  _GIFchain()
 		return -1;
 	}
 
-	return WRITERING_DMA(pMem, qwc);
+	return WRITERING_DMA(pMem, gif->qwc);
 }
 
 static __forceinline void GIFchain()
@@ -205,11 +204,7 @@ void GIFdma()
 	{
 	    // We are in image mode doing DIRECTHL, Path 1 is in queue, and in intermittant mode.
 		//GIF_LOG("Waiting VU %x, PATH2 %x, GIFMODE %x Progress %x", gifRegs->stat.P1Q, (vif1.cmd & 0x7f), gifRegs->mode._u32, GSTransferStatus.PTH3);
-		/*if(GSTransferStatus.PTH3 == STOPPED_MODE)
-		{
-			
-		} else Console.Warning("PATH3 Transfer in action while another one path is running, Path3 mode %x", GSTransferStatus.PTH3);*/
-		gifRegs->stat.set_flags(GIF_STAT_P2Q);
+		gifRegs->stat.set_flags(GIF_STAT_P3Q);
 		CPU_INT(DMAC_GIF, 16);
 		return;
 	}
@@ -327,7 +322,7 @@ void dmaGIF()
 	//It takes the time of 24 QW for the BUS to become ready - The Punisher And Streetball
 	GIF_LOG("dmaGIFstart chcr = %lx, madr = %lx, qwc  = %lx\n tadr = %lx, asr0 = %lx, asr1 = %lx", gif->chcr._u32, gif->madr, gif->qwc, gif->tadr, gif->asr0, gif->asr1);
 
-	GSTransferStatus.PTH3 = STOPPED_MODE;
+	//GSTransferStatus.PTH3 = STOPPED_MODE;
 	gspath3done = false; // For some reason this doesn't clear? So when the system starts the thread, we will clear it :)
 
 	gifRegs->stat.P3Q = true;
diff --git a/pcsx2/Gif.h b/pcsx2/Gif.h
index c79a1cc949..f15aed12fa 100644
--- a/pcsx2/Gif.h
+++ b/pcsx2/Gif.h
@@ -16,8 +16,6 @@
 #ifndef __GIF_H__
 #define __GIF_H__
 
-const int gifsplit = 0x10000;
-
 enum gifstate_t
 {
 	GIF_STATE_READY = 0,
diff --git a/pcsx2/IPU/IPU.cpp b/pcsx2/IPU/IPU.cpp
index e17f90c849..a51c3dcf72 100644
--- a/pcsx2/IPU/IPU.cpp
+++ b/pcsx2/IPU/IPU.cpp
@@ -1644,7 +1644,7 @@ void ipu0Interrupt()
 		// vif
 		Console.Warning("IPU VIF Stall");
 		g_nDMATransfer.VIFSTALL = false;
-		if (vif1ch->chcr.STR) dmaVIF1();
+		//if (vif1ch->chcr.STR) dmaVIF1();
 	}
 
 	if (g_nDMATransfer.SIFSTALL)
diff --git a/pcsx2/Sif0.cpp b/pcsx2/Sif0.cpp
index b4219a5203..fa9b909cac 100644
--- a/pcsx2/Sif0.cpp
+++ b/pcsx2/Sif0.cpp
@@ -177,18 +177,26 @@ static __forceinline void EndIOP()
 // Handle the EE transfer.
 static __forceinline void HandleEETransfer()
 {
+	if(sif0dma->chcr.STR == false)
+	{
+		DevCon.Warning("Replacement for irq prevention hack EE SIF0");
+		sif0.ee.end = false;
+		sif0.ee.busy = false;
+		return;
+	}
+
 	if (dmacRegs->ctrl.STS == STS_SIF0)
 	{
 		DevCon.Warning("SIF0 stall control");
 	}
 
-	if (sif0dma->qwc == 0) 
+	/*if (sif0dma->qwc == 0) 
 		if (sif0dma->chcr.MOD == NORMAL_MODE) 
 			if (!sif0.ee.end){ 
 				DevCon.Warning("sif0 irq prevented"); 
 				done = true; 
 				return;
-			}
+			}*/
 
 	if (sif0dma->qwc <= 0)
 	{
@@ -280,13 +288,25 @@ static __forceinline void Sif0End()
 // Transfer IOP to EE, putting data in the fifo as an intermediate step.
 __forceinline void SIF0Dma()
 {
+	int BusyCheck = 0;
 	Sif0Init();
 	
 	do
 	{
-		if (sif0.iop.busy) HandleIOPTransfer();
-		if (sif0.ee.busy) HandleEETransfer();
-	} while (!done); // Substituting (sif0.ee.busy || sif0.iop.busy) breaks things.
+		//I realise this is very hacky in a way but its an easy way of checking if both are doing something
+		BusyCheck = 0;
+
+		if (sif0.iop.busy) 
+		{
+			if(sif0.fifo.free() > 0) BusyCheck++;
+			HandleIOPTransfer();
+		}
+		if (sif0.ee.busy) 
+		{
+			if(sif0.fifo.size >= 4) BusyCheck++;
+			HandleEETransfer();
+		}
+	} while (!done && BusyCheck > 0); // Substituting (sif0.ee.busy || sif0.iop.busy) breaks things.
 	
 	Sif0End();
 }
diff --git a/pcsx2/Sif1.cpp b/pcsx2/Sif1.cpp
index dac9f9627c..3cc1a8eb15 100644
--- a/pcsx2/Sif1.cpp
+++ b/pcsx2/Sif1.cpp
@@ -203,18 +203,25 @@ static __forceinline void EndIOP()
 // Handle the EE transfer.
 static __forceinline void HandleEETransfer()
 {
+	if(sif1dma->chcr.STR == false)
+	{
+		DevCon.Warning("Replacement for irq prevention hack EE SIF1");
+		sif1.ee.end = false;
+		sif1.ee.busy = false;
+		return;
+	}
 	if (dmacRegs->ctrl.STD == STD_SIF1)
 	{
 		DevCon.Warning("SIF1 stall control"); // STD == fromSIF1
 	}
 
-	if (sif1dma->qwc == 0) 
+	/*if (sif1dma->qwc == 0) 
 		if (sif1dma->chcr.MOD == NORMAL_MODE) 
 			if (!sif1.ee.end){ 
-				DevCon.Warning("sif1 irq prevented"); 
+				DevCon.Warning("sif1 irq prevented CHCR %x QWC %x", sif1dma->chcr, sif1dma->qwc); 
 				done = true; 
 				return;
-			}
+			}*/
 
 	// If there's no more to transfer.
 	if (sif1dma->qwc <= 0)
@@ -275,13 +282,27 @@ static __forceinline void Sif1End()
 // Transfer EE to IOP, putting data in the fifo as an intermediate step.
 __forceinline void SIF1Dma()
 {
+	int BusyCheck = 0;
 	Sif1Init();
 	
 	do
 	{
-		if (sif1.ee.busy) HandleEETransfer();
-		if (sif1.iop.busy) HandleIOPTransfer();
-	} while (!done);
+		//I realise this is very hacky in a way but its an easy way of checking if both are doing something
+		BusyCheck = 0;
+
+		if (sif1.ee.busy) 
+		{
+			if(sif1.fifo.free() > 0) BusyCheck++;
+			HandleEETransfer();
+		}
+
+		if (sif1.iop.busy) 
+		{
+			if(sif1.fifo.size >= 4) BusyCheck++;
+			HandleIOPTransfer();
+		}
+		
+	} while (!done && BusyCheck > 0);
 	
 	Sif1End();
 }
diff --git a/pcsx2/Vif1_Dma.cpp b/pcsx2/Vif1_Dma.cpp
index bff000a95a..aa8b92fc5f 100644
--- a/pcsx2/Vif1_Dma.cpp
+++ b/pcsx2/Vif1_Dma.cpp
@@ -300,6 +300,7 @@ __forceinline void vif1Interrupt()
 	vif1Regs->stat.VPS = VPS_IDLE; //Vif goes idle as the stall happened between commands;
 	vif1ch->chcr.STR = false;
 	g_vifCycles = 0;
+	VIF_LOG("VIF1 End");
 	hwDmacIrq(DMAC_VIF1);
 	
 }